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2023-12-12aarch64,arm: Fix branch-protection= parsingSzabolcs Nagy7-168/+116
Refactor the parsing to have a single API and fix a few parsing issues: - Different handling of "bti+none" and "none+bti": these should be rejected because "none" can only appear alone. - Accepted empty strings such as "bti++pac-ret" or "bti+", this bug was caused by using strtok_r. - Memory got leaked (str_root was never freed). And two buffers got allocated when one is enough. The callbacks now have no failure mode, only parsing can fail and all failures are handled locally. The "-mbranch-protection=" vs "target("branch-protection=")" difference in the error message is handled by a separate argument to aarch_validate_mbranch_protection. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_override_options): Update. (aarch64_handle_attr_branch_protection): Update. * config/arm/aarch-common-protos.h (aarch_parse_branch_protection): Remove. (aarch_validate_mbranch_protection): Add new argument. * config/arm/aarch-common.cc (aarch_handle_no_branch_protection): Update. (aarch_handle_standard_branch_protection): Update. (aarch_handle_pac_ret_protection): Update. (aarch_handle_pac_ret_leaf): Update. (aarch_handle_pac_ret_b_key): Update. (aarch_handle_bti_protection): Update. (aarch_parse_branch_protection): Remove. (next_tok): New. (aarch_validate_mbranch_protection): Rewrite. * config/arm/aarch-common.h (struct aarch_branch_protect_type): Add field "alone". * config/arm/arm.cc (arm_configure_build_target): Update. gcc/testsuite/ChangeLog: * gcc.target/aarch64/branch-protection-attr.c: Update. * gcc.target/aarch64/branch-protection-option.c: Update.
2023-12-12aarch64,arm: Remove accepted_branch_protection_stringSzabolcs Nagy3-27/+1
On aarch64 this caused ICE with pragma push_options since commit ae54c1b09963779c5c3914782324ff48af32e2f1 Author: Wilco Dijkstra <wilco.dijkstra@arm.com> CommitDate: 2022-06-01 18:13:57 +0100 AArch64: Cleanup option processing code The failure is at pop_options: internal compiler error: ‘global_options’ are modified in local context On arm the variable was unused. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_override_options_after_change_1): Do not override branch_protection options. (aarch64_override_options): Remove accepted_branch_protection_string. * config/arm/aarch-common.cc (BRANCH_PROTECT_STR_MAX): Remove. (aarch_parse_branch_protection): Remove accepted_branch_protection_string. * config/arm/arm.cc: Likewise.
2023-12-12tree-optimization/112736 - avoid overread with non-grouped SLP loadRichard Biener2-19/+100
The following aovids over/under-read of storage when vectorizing a non-grouped load with SLP. Instead of forcing peeling for gaps use a smaller load for the last vector which might access excess elements. This builds upon the existing optimization avoiding peeling for gaps, generalizing it to all gap widths leaving a power-of-two remaining number of elements (but it doesn't replace or improve that particular case at this point). I wonder if the poly relational compares I set up are good enough to guarantee /* remain should now be > 0 and < nunits. */. There is existing test coverage that runs into /* DR will be unused. */ always when the gap is wider than nunits. Compared to the existing gap == nunits/2 case this only adjusts the load that will cause the overrun at the end, not every load. Apart from the poly relational compares it should reliably cover these cases but I'll leave it for stage1 to remove. PR tree-optimization/112736 * tree-vect-stmts.cc (vectorizable_load): Extend optimization to avoid peeling for gaps to handle single-element non-groups we now allow with SLP. * gcc.dg/torture/pr112736.c: New testcase.
2023-12-12ipa/92606 - properly handle no_icf attribute for variablesRichard Biener3-2/+9
The following adds no_icf handling for variables where the attribute was rejected. It also fixes the check for no_icf by checking both the source and the targets decl. PR ipa/92606 gcc/c-family/ * c-attribs.cc (handle_noicf_attribute): Also allow the attribute on global variables. gcc/ * ipa-icf.cc (sem_item_optimizer::merge_classes): Check both source and alias for the no_icf attribute. * doc/extend.texi (no_icf): Document variable attribute.
2023-12-12tree-optimization/112961 - include latch in if-conversion CSERichard Biener2-2/+24
The following makes sure to also process the (empty) latch when performing CSE on the if-converted loop body. That's important to get all uses of copies propagated out on the backedge as well. To avoid CSE on the PHI nodes itself which is prohibitive (see PR90402) this temporarily adds a fake entry edge to the loop. PR tree-optimization/112961 * tree-if-conv.cc (tree_if_conversion): Instead of excluding the latch block from VN, add a fake entry edge. * g++.dg/vect/pr112961.cc: New testcase.
2023-12-12testsuite: Fix up test directive syntax errorsJakub Jelinek3-9/+9
I've noticed +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr89246-1.c: syntax error in target selector ".-4" for " dg-warning 11 "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr89246-1.c: syntax error in target selector ".-4" for " dg-warning 11 "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/simd-clones-2.c: unmatched open quote in list for " dg-final 19 { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } " +ERROR: gcc.dg/gomp/simd-clones-2.c: unmatched open quote in list for " dg-final 19 { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } " regressions. The following patch fixes those. 2023-12-12 Jakub Jelinek <jakub@redhat.com> * gcc.dg/gomp/pr87887-1.c: Add missing comment argument to dg-warning. * gcc.dg/gomp/pr89246-1.c: Likewise. * gcc.dg/gomp/simd-clones-2.c: Add missing " after dump name.
2023-12-12Only allow (int)trunc(x) to (int)x simplification with ↵Xi Ruoyao2-1/+14
-ffp-int-builtin-inexact [PR107723] With -fno-fp-int-builtin-inexact, trunc is not allowed to raise FE_INEXACT and it should produce an integral result (if the input is not NaN or Inf). Thus FE_INEXACT should not be raised. But (int)x may raise FE_INEXACT when x is a non-integer, non-NaN, and non-Inf value. C23 recommends to do so in a footnote. Thus we should not simplify (int)trunc(x) to (int)x if -fno-fp-int-builtin-inexact is in-effect. gcc/ChangeLog: PR middle-end/107723 * convert.cc (convert_to_integer_1) [case BUILT_IN_TRUNC]: Break early if !flag_fp_int_builtin_inexact and flag_trapping_math. gcc/testsuite/ChangeLog: PR middle-end/107723 * gcc.dg/torture/builtin-fp-int-inexact-trunc.c: New test.
2023-12-12aarch64: Add dg-options to prfm_imm_offset_2.cRichard Sandiford1-0/+1
gcc/testsuite/ * gcc.target/aarch64/prfm_imm_offset_2.c: Add dg-options.
2023-12-12RISC-V: Disable RVV VCOMPRESS avl propagationPan Li2-10/+61
This patch would like to disable the avl propagation for the follow reasons. According to the ISA, the first vl elements of vector register group vs2 should be extracted and packed for vcompress. And the highest element of vs2 vector may be touched by the mask, which may be eliminated by avl propagation. For example, given original vl = 4 here. We have: v0 = 0b1000 v1 = {0x1, 0x2, 0x3, 0x4} v2 = {0x5, 0x6, 0x7, 0x8} Then: vcompress v1, v2, v0 (avl = 4), v1 = {0x8, 0x2, 0x3, 0x4}. <== Correct. vcompress v1, v2, v0 (avl = 2), v1 will be unchanged. <== Wrong. Finally, we cannot propagate avl of vcompress because it may has senmatics change to the result. This patch also fix the failure of gcc.c-torture/execute/990128-1.c for the following configurations. riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Disable the avl propogation for the vcompress. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-12-12LoongArch: Fix warnings building libgccXi Ruoyao1-10/+10
We are excluding loongarch-opts.h from target libraries, but now struct loongarch_target and gcc_options are not declared in the target libraries, causing: In file included from ../.././gcc/options.h:8, from ../.././gcc/tm.h:49, from ../../../gcc/libgcc/fixed-bit.c:48: ../../../gcc/libgcc/../gcc/config/loongarch/loongarch-opts.h:57:41: warning: 'struct gcc_options' declared inside parameter list will not be visible outside of this definition or declaration 57 | struct gcc_options *opts, | ^~~~~~~~~~~ So exclude the declarations referring to the C++ structs as well. gcc/ChangeLog: * config/loongarch/loongarch-opts.h (la_target): Move into #if for loongarch-def.h. (loongarch_init_target): Likewise. (loongarch_config_target): Likewise. (loongarch_update_gcc_opt_status): Likewise.
2023-12-12LoongArch: Allow -mcmodel=extreme and model attribute with ↵Xi Ruoyao6-11/+44
-mexplicit-relocs=auto There seems no real reason to require -mexplicit-relocs=always for -mcmodel=extreme or model attribute. As the linker does not know how to relax a 3-operand la.local or la.global pseudo instruction, just emit explicit relocs for SYMBOL_PCREL64, and under TARGET_CMODEL_EXTREME also SYMBOL_GOT_DISP. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p): Return true for SYMBOL_PCREL64. Return true for SYMBOL_GOT_DISP if TARGET_CMODEL_EXTREME. (loongarch_split_symbol): Check for la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE instead of TARGET_EXPLICIT_RELOCS. (loongarch_print_operand_reloc): Likewise. (loongarch_option_override_internal): Likewise. (loongarch_handle_model_attribute): Likewise. * doc/invoke.texi (-mcmodel=extreme): Update the compatibility between it and -mexplicit-relocs=. gcc/testsuite/ChangeLog: * gcc.target/loongarch/attr-model-3.c: New test. * gcc.target/loongarch/attr-model-4.c: New test. * gcc.target/loongarch/func-call-extreme-3.c: New test. * gcc.target/loongarch/func-call-extreme-4.c: New test.
2023-12-12tree-optimization/112939 - VN PHI visiting and -ftrivial-auto-var-initRichard Biener2-1/+26
The following builds upon the last fix, making sure we only value-number to visited (un-)defs, otherwise prefer .VN_TOP. PR tree-optimization/112939 * tree-ssa-sccvn.cc (visit_phi): When all args are undefined make sure we end up with a value that was visited, otherwise fall back to .VN_TOP. * gcc.dg/pr112939.c: New testcase.
2023-12-12Don't assume it's AVX_U128_CLEAN after call_insn whose ↵liuhongt3-3/+78
abi.mode_clobber(V4DImode) deosn't contains all SSE_REGS. If the function desn't clobber any sse registers or only clobber 128-bit part, then vzeroupper isn't issued before the function exit. the status not CLEAN but ANY after the function. Also for sibling_call, it's safe to issue an vzeroupper. Also there could be missing vzeroupper since there's no mode_exit for sibling_call_p. gcc/ChangeLog: PR target/112891 * config/i386/i386.cc (ix86_avx_u128_mode_after): Return AVX_U128_ANY if callee_abi doesn't clobber all_sse_regs to align with ix86_avx_u128_mode_needed. (ix86_avx_u128_mode_needed): Return AVX_U128_ClEAN for sibling_call. gcc/testsuite/ChangeLog: * gcc.target/i386/pr112891.c: New test. * gcc.target/i386/pr112891-2.c: New test.
2023-12-12untyped calls: enable target switching [PR112334]Alexandre Oliva2-2/+21
The computation of apply_args_size and apply_result_size is saved in a static variable, so that the corresponding _mode arrays are initialized only once. That is not compatible with switchable targets, and ARM's arm_set_current_function, by saving and restoring target globals, exercises this problem with a testcase such as that in the PR, in which more than one function in the translation unit calls __builtin_apply or __builtin_return, respectively. This patch moves the _size statics into the target_builtins array, with a bit of ugliness over _plus_one so that zero initialization of the struct does the right thing. for gcc/ChangeLog PR target/112334 * builtins.h (target_builtins): Add fields for apply_args_size and apply_result_size. * builtins.cc (apply_args_size, apply_result_size): Cache results in fields rather than in static variables. (get_apply_args_size, set_apply_args_size): New. (get_apply_result_size, set_apply_result_size): New.
2023-12-12i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]Hongyu Wang2-4/+71
The ashl/lshr/ashr expanders calls ix86_expand_binary_operator, while they will be called for some post-reload split, and TARGET_APX_NDD is required for these calls to avoid force-load to memory at postreload stage. gcc/ChangeLog: PR target/112943 * config/i386/i386.md (ashl<mode>3): Add TARGET_APX_NDD to ix86_expand_binary_operator call. (<insn><mode>3): Likewise for rshift. (<insn>di3): Likewise for DImode rotate. (<insn><mode>3): Likewise for SWI124 rotate. gcc/testsuite/ChangeLog: PR target/112943 * gcc.target/i386/pr112943.c: New test.
2023-12-11analyzer: add more test coverage for tainted modulusDavid Malcolm2-0/+76
Add more test coverage for r14-6349-g0bef72539e585d. gcc/testsuite/ChangeLog: * gcc.dg/plugin/plugin.exp: Add taint-modulus.c to analyzer_kernel_plugin.c tests. * gcc.dg/plugin/taint-modulus.c: New test. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-12-12RISC-V: Add avail interface into function_group_infoFeng Wang5-475/+503
Patch v3: Fix typo and remove the modification of rvv.exp. Patch v2: Using variadic macro and add the dependency into t-riscv. In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add AVAIL argument. (read_vl): Using AVAIL argument default value. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto. (vfwcvt_rtz_xu) Ditto.: (vfwcvt_f): Ditto. (vfwcvt_x_frm): Ditto. (vfwcvt_xu_frm) Ditto.: (vfncvt_x): Ditto. (vfncvt_xu): Ditto. (vfncvt_rtz_x): Ditto. (vfncvt_rtz_xu): Ditto. (vfncvt_f): Ditto. (vfncvt_rod_f): Ditto. (vfncvt_x_frm): Ditto. (vfncvt_xu_frm): Ditto. (vfncvt_f_frm): Ditto. (vredsum): Ditto. (vredmaxu): Ditto. (vredmax): Ditto. (vredminu): Ditto. (vredmin): Ditto. (vredand): Ditto. (vredor): Ditto. (vredxor): Ditto. (vwredsum): Ditto. (vwredsumu): Ditto. (vfredusum): Ditto. (vfredosum): Ditto. (vfredmax): Ditto. (vfredmin): Ditto. (vfredusum_frm): Ditto. (vfredosum_frm): Ditto. (vfwredosum): Ditto. (vfwredusum): Ditto. (vfwredosum_frm): Ditto. (vfwredusum_frm): Ditto. (vmand): Ditto. (vmnand): Ditto. (vmandn): Ditto. (vmxor): Ditto. (vmor): Ditto. (vmnor): Ditto. (vmorn): Ditto. (vmxnor): Ditto. (vmmv): Ditto. (vmclr): Ditto. (vmset): Ditto. (vmnot): Ditto. (vcpop): Ditto. (vfirst): Ditto. (vmsbf): Ditto. (vmsif): Ditto. (vmsof): Ditto. (viota): Ditto. (vid): Ditto. (vmv_x): Ditto. (vmv_s): Ditto. (vfmv_f): Ditto. (vfmv_s): Ditto. (vslideup): Ditto. (vslidedown): Ditto. (vslide1up): Ditto. (vslide1down): Ditto. (vfslide1up): Ditto. (vfslide1down): Ditto. (vrgather): Ditto. (vrgatherei16): Ditto. (vcompress): Ditto. (vundefined): Ditto. (vreinterpret): Ditto. (vlmul_ext): Ditto. (vlmul_trunc): Ditto. (vset): Ditto. (vget): Ditto. (vcreate): Ditto. (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): Using variadic macro. * config/riscv/riscv-vector-builtins.h (struct function_group_info): Add avail function interface into struct. * config/riscv/t-riscv: Add dependency * config/riscv/riscv-vector-builtins-avail.h: New file.The definition of AVAIL marco.
2023-12-12RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]Juzhe-Zhong3-40/+52
This patch moves RVV POLY VALUE estimation from riscv.cc to riscv-v.cc for future better maintain like other target hook implementation. Committed as it is obviously a code refinement. gcc/ChangeLog: * config/riscv/riscv-protos.h (estimated_poly_value): New function. * config/riscv/riscv-v.cc (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY VALUE estimation to riscv-v.cc
2023-12-12LoongArch: Fix eh_return epilogue for normal returns.Yang Yujie4-13/+84
On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved and restored in the function prologue and epilogue if the given function calls __builtin_eh_return. This causes the return value to be overwritten on normal return paths and breaks a rare case of libgcc's _Unwind_RaiseException. gcc/ChangeLog: * config/loongarch/loongarch.cc: Do not restore the saved eh_return data registers ($r4-$r7) for a normal return of a function that calls __builtin_eh_return elsewhere. * config/loongarch/loongarch-protos.h: Same. * config/loongarch/loongarch.md: Same. gcc/testsuite/ChangeLog: * gcc.target/loongarch/eh_return-normal-return.c: New test.
2023-12-12Daily bump.GCC Administrator9-1/+526
2023-12-11testsuite: Disable -fstack-protector* for some strub testsJakub Jelinek4-4/+4
In our distro builds, we test with RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\}' because SSP is something we use widely in the distribution. 4 new strub test FAIL with that option though, as can be seen with a simple make check-gcc check-g++ RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\} dg.exp=strub-O*' - in particular, the expand dump \[(\]call\[^\n\]*strub_leave.*\n\[(\]code_label regexps see code_labels in there introduced for stack protector. The following patch fixes it by using -fno-stack-protector for these explicitly. 2023-12-11 Jakub Jelinek <jakub@redhat.com> * c-c++-common/strub-O2fni.c: Add -fno-stack-protector to dg-options. * c-c++-common/strub-O3fni.c: Likewise. * c-c++-common/strub-Os.c: Likewise. * c-c++-common/strub-Og.c: Likewise.
2023-12-11Fix regression causing ICE for structs with VLAs [PR 112488]Martin Uecker7-11/+65
A previous patch that fixed several ICEs related to size expressions of VM types (PR c/70418, ...) caused a regression for structs where a DECL_EXPR is not generated anymore although reqired. We now call add_decl_expr introduced by the previous patch from finish_struct. The function is revised with a new argument to not set the TYPE_NAME for the type to the DECL_EXPR in this specific case. PR c/112488 gcc/c * c-decl.cc (add_decl_expr): Revise. (finish_struct): Create DECL_EXPR. * c-parser.cc (c_parser_struct_or_union_specifier): Call finish_struct with expression for VLA sizes. * c-tree.h (finish_struct): Add argument. gcc/testsuite * gcc.dg/pr112488-1.c: New test. * gcc.dg/pr112488-2.c: New test. * gcc.dg/pr112898.c: New test. * gcc.misc-tests/gcov-pr85350.c: Adapt.
2023-12-11Resolve ICE in 'gcc/fortran/trans-openmp.cc:gfc_omp_call_is_alloc'Thomas Schwinge1-1/+1
Fix-up for recent commit 2505a8b41d3b74a545755a278f3750a29c1340b6 "OpenMP: Minor '!$omp allocators' cleanup", which caused: {+FAIL: gfortran.dg/gomp/allocate-5.f90 -O (internal compiler error: tree check: expected class 'type', have 'declaration' (function_decl) in gfc_omp_call_is_alloc, at fortran/trans-openmp.cc:8386)+} [-PASS:-]{+FAIL:+} gfortran.dg/gomp/allocate-5.f90 -O (test for excess errors) ..., and similarly in 'libgomp.fortran/allocators-1.f90', 'libgomp.fortran/allocators-2.f90', 'libgomp.fortran/allocators-3.f90', 'libgomp.fortran/allocators-4.f90', 'libgomp.fortran/allocators-5.f90'. gcc/fortran/ * trans-openmp.cc (gfc_omp_call_is_alloc): Resolve ICE.
2023-12-11analyzer: fix uninitialized bitmap [PR112955]David Malcolm1-0/+1
In r14-5566-g841008d3966c0f I added a new ctor for feasibility_state, but failed to call bitmap_clear on m_snodes_visited. Fixed thusly. gcc/analyzer/ChangeLog: PR analyzer/112955 * engine.cc (feasibility_state::feasibility_state): Initialize m_snodes_visited. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-12-11Treat "p" in asms as addressing VOIDmodeRichard Sandiford3-8/+15
check_asm_operands was inconsistent about how it handled "p" after RA compared to before RA. Before RA it tested the address with a void (unknown) memory mode: case CT_ADDRESS: /* Every address operand can be reloaded to fit. */ result = result || address_operand (op, VOIDmode); break; After RA it deferred to constrain_operands, which used the mode of the operand: if ((GET_MODE (op) == VOIDmode || SCALAR_INT_MODE_P (GET_MODE (op))) && (strict <= 0 || (strict_memory_address_p (recog_data.operand_mode[opno], op)))) win = true; Using the mode of the operand is necessary for special predicates, where it is used to give the memory mode. But for asms, the operand mode is simply the mode of the address itself (so DImode on 64-bit targets), which doesn't say anything about the addressed memory. This patch uses VOIDmode for asms but continues to use the operand mode for .md insns. It's needed to avoid a regression in the testcase with the late-combine pass. Fixing this made me realise that recog_level2 was doing duplicate work for asms after RA. gcc/ * recog.cc (constrain_operands): Pass VOIDmode to strict_memory_address_p for 'p' constraints in asms. * rtl-ssa/changes.cc (recog_level2): Skip redundant constrain_operands for asms. gcc/testsuite/ * gcc.target/aarch64/prfm_imm_offset_2.c: New test.
2023-12-11testsuite: update manglingJason Merrill3-0/+26
Since r14-6064-gc3f281a0c1ca50 this test was checking for the wrong mangling, but it still passed on targets that support ABI compatibility aliases. Let's avoid generating those aliases when checking mangling. gcc/ChangeLog: * common.opt: Add comment. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-explicit-inst1.C: Specify ABI v18. * g++.dg/cpp2a/concepts-explicit-inst1a.C: New test.
2023-12-11-finline-stringops: avoid too-wide smallest_int_mode_for_size [PR112784]Alexandre Oliva2-11/+21
smallest_int_mode_for_size may abort when the requested mode is not available. Call int_mode_for_size instead, that signals the unsatisfiable request in a more graceful way. for gcc/ChangeLog PR middle-end/112784 * expr.cc (emit_block_move_via_loop): Call int_mode_for_size for maybe-too-wide sizes. (emit_block_cmp_via_loop): Likewise. for gcc/testsuite/ChangeLog PR middle-end/112784 * gcc.target/i386/avx512cd-inline-stringops-pr112784.c: New.
2023-12-11-finline-stringops: check base blksize for memset [PR112778]Alexandre Oliva2-9/+58
The recently-added logic for -finline-stringops=memset introduced an assumption that doesn't necessarily hold, namely, that can_store_by_pieces of a larger size implies can_store_by_pieces by smaller sizes. Checks for all sizes the by-multiple-pieces machinery might use before committing to an expansion pattern. for gcc/ChangeLog PR target/112778 * builtins.cc (can_store_by_multiple_pieces): New. (try_store_by_multiple_pieces): Call it. for gcc/testsuite/ChangeLog PR target/112778 * gcc.dg/inline-mem-cmp-pr112778.c: New.
2023-12-11-finline-stringops: don't assume ptr_mode ptr in memset [PR112804]Alexandre Oliva2-1/+8
On aarch64 -milp32, and presumably on other such targets, ptr can be in a different mode than ptr_mode in the testcase. Cope with it. for gcc/ChangeLog PR target/112804 * builtins.cc (try_store_by_multiple_pieces): Use ptr's mode for the increment. for gcc/testsuite/ChangeLog PR target/112804 * gcc.target/aarch64/inline-mem-set-pr112804.c: New.
2023-12-11multiflags: fix doc warningAlexandre Oliva1-1/+1
Comply with dubious doc warning that after an @xref there must be a comma or a period, not a close parentheses. for gcc/ChangeLog * doc/invoke.texi (multiflags): Add period after @xref to silence warning.
2023-12-11strub: disable on rl78Alexandre Oliva1-0/+5
rl78 allocation of virtual registers to physical registers doesn't operate on asm statements, and strub uses asm statements in the runtime and in the generated code, to the point that the runtime won't build. Force strub disabled on that target. for gcc/ChangeLog * config/rl78/rl78.cc (TARGET_HAVE_STRUB_SUPPORT_FOR): Disable.
2023-12-11strub: add note on attribute accessAlexandre Oliva1-1/+10
Document why attribute access doesn't need the same treatment as fn spec, and check that the assumption behind it holds. for gcc/ChangeLog * ipa-strub.cc (pass_ipa_strub::execute): Check that we don't add indirection to pointer parameters, and document attribute access non-interactions.
2023-12-11PR rtl-optimization/112380: Defend against CLOBBERs in combine.ccRoger Sayle2-3/+39
This patch addresses PR rtl-optimization/112380, an ICE-on-valid regression where a (clobber (const_int 0)) encounters a sanity checking gcc_assert (at line 7554) in simplify-rtx.cc. These CLOBBERs are used internally by GCC's combine pass much like error_mark_node is used by various language front-ends. The solutions are either to handle/accept these CLOBBERs through-out (or in more places in) the middle-end's RTL optimizers, including functions in simplify-rtx.cc that are used by passes other than combine, and/or attempt to prevent these CLOBBERs escaping from try_combine into the RTX/RTL stream. The benefit of the second approach is that it actually allows for better optimization: when try_combine fails to simplify an expression instead of substituting a CLOBBER to avoid the instruction pattern being recognized, noticing the CLOBBER often allows combine to attempt alternate simplifications/transformations looking for those that can be recognized. This first alternative is the minimal fix to address the CLOBBER encountered in the bugzilla PR. 2023-12-11 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog PR rtl-optimization/112380 * combine.cc (expand_field_assignment): Check if gen_lowpart returned a CLOBBER, and avoid calling gen_simplify_binary with it if so. gcc/testsuite/ChangeLog PR rtl-optimization/112380 * gcc.dg/pr112380.c: New test case.
2023-12-11Testsuite: restrict test to nonpic targetsFrancois-Xavier Coudert1-0/+1
The test is currently failing on x86_64-apple-darwin. gcc/testsuite/ChangeLog: PR testsuite/112297 * gcc.target/i386/pr100936.c: Require nonpic target.
2023-12-11c++: add fixed testcase [PR63378]Patrick Palka1-0/+20
We accept this testcase since r12-4453-g79802c5dcc043a. PR c++/63378 gcc/testsuite/ChangeLog: * g++.dg/template/fnspec3.C: New test.
2023-12-11aarch64: Fix wrong code for bfloat when f16 is enabled [PR 111867]Andrew Pinski1-0/+4
The problem here is when f16 is enabled, movbf_aarch64 accepts `Ufc` as a constraint: [ w , Ufc ; fconsts , fp16 ] fmov\t%h0, %1 But that is for fmov values and in this case fmov represents f16 rather than bfloat16 values. This means we would get the wrong value in the register. Built and tested for aarch64-linux-gnu with no regressions. Also tested with `-march=armv9-a+sve2, gcc.dg/torture/bfloat16-basic.c and gcc.dg/torture/bfloat16-builtin.c no longer fail. gcc/ChangeLog: PR target/111867 * config/aarch64/aarch64.cc (aarch64_float_const_representable_p): For BFmode, only accept +0.0. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2023-12-11MATCH: (convert)(zero_one !=/== 0/1) for outer type and zero_one type are ↵Andrew Pinski9-63/+103
the same When I moved two_value to match.pd, I removed the check for the {0,+-1} as I had placed it after the {0,+-1} case for cond in match.pd. In the case of {0,+-1} and non boolean, before we would optmize those case to just `(convert)a` but after we would get `(convert)(a != 0)` which was not handled anyways to just `(convert)a`. So this adds a pattern to match `(convert)(zeroone != 0)` and simplify to `(convert)zeroone`. Also this optimizes (convert)(zeroone == 0) into (zeroone^1) if the type match. Removing the opposite transformation from fold. The opposite transformation was added with https://gcc.gnu.org/pipermail/gcc-patches/2006-February/190514.html It is no longer considered the canonicalization either, even VRP will transform it back into `(~a) & 1` so removing it is a good idea. Note the testcase pr69270.c needed a slight update due to not matching exactly a scan pattern, this update makes it more robust and will match before and afterwards and if there are other changes in this area too. Note the testcase gcc.target/i386/pr110790-2.c needs a slight update for better code generation in LP64 bit mode. Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: PR tree-optimization/111972 PR tree-optimization/110637 * match.pd (`(convert)(zeroone !=/== CST)`): Match and simplify to ((convert)zeroone){,^1}. * fold-const.cc (fold_binary_loc): Remove transformation of `(~a) & 1` and `(a ^ 1) & 1` into `(convert)(a == 0)`. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr110637-1.c: New test. * gcc.dg/tree-ssa/pr110637-2.c: New test. * gcc.dg/tree-ssa/pr110637-3.c: New test. * gcc.dg/tree-ssa/pr111972-1.c: New test. * gcc.dg/tree-ssa/pr69270.c: Update testcase. * gcc.target/i386/pr110790-2.c: Update testcase. * gcc.dg/fold-even-1.c: Removed. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2023-12-11analyzer: Remove check of unsigned_char in ↵Andrew Pinski1-3/+0
maybe_undo_optimize_bit_field_compare. The check for the type seems unnecessary and gets in the way sometimes. Also with a patch I am working on for match.pd, it causes a failure to happen. Before my patch the IR was: _1 = BIT_FIELD_REF <s, 8, 16>; _2 = _1 & 1; _3 = _2 != 0; _4 = (int) _3; __analyzer_eval (_4); Where _2 was an unsigned char type. And After my patch we have: _1 = BIT_FIELD_REF <s, 8, 16>; _2 = (int) _1; _3 = _2 & 1; __analyzer_eval (_3); But in this case, the BIT_AND_EXPR is in an int type. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/analyzer/ChangeLog: * region-model-manager.cc (maybe_undo_optimize_bit_field_compare): Remove the check for type being unsigned_char_type_node.
2023-12-11expr: catch more `a*bool` while expanding [PR 112935]Andrew Pinski1-2/+3
After r14-1655-g52c92fb3f40050 (and the other commits which touch zero_one_valued_p), we end up with a with `bool * a` but where the bool is an SSA name that might not have non-zero bits set on it (to 0x1) even though it does the non-zero bits would be 0x1. The case of coremarks, it is only phiopt4 which adds the new ssa name and nothing afterwards updates the nonzero bits on it. This fixes the regression by using gimple_zero_one_valued_p rather than tree_nonzero_bits to match the cases where the SSA_NAME didn't have the non-zero bits set. gimple_zero_one_valued_p handles one level of cast and also and an `&`. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: PR middle-end/112935 * expr.cc (expand_expr_real_2): Use gimple_zero_one_valued_p instead of tree_nonzero_bits to find boolean defined expressions. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2023-12-11[PATCH] wrong code on m68k with -mlong-jump-table-offsets and -malign-int ↵Mikael Pettersson3-6/+6
(PR target/112413) On m68k the compiler assumes that the PC-relative jump-via-jump-table instruction and the jump table are adjacent with no padding in between. When -mlong-jump-table-offsets is combined with -malign-int, a 2-byte nop may be inserted before the jump table, causing the jump to add the fetched offset to the wrong PC base and thus jump to the wrong address. Fixed by referencing the jump table via its label. On the test case in the PR the object code change is (the moveal at 16 is the nop): a: 6536 bcss 42 <f+0x42> c: e588 lsll #2,%d0 e: 203b 0808 movel %pc@(18 <f+0x18>,%d0:l),%d0 - 12: 4efb 0802 jmp %pc@(16 <f+0x16>,%d0:l) + 12: 4efb 0804 jmp %pc@(18 <f+0x18>,%d0:l) 16: 284c moveal %a4,%a4 18: 0000 0020 orib #32,%d0 1c: 0000 002c orib #44,%d0 Bootstrapped and tested on m68k-linux-gnu, no regressions. Note: I don't have commit rights to I would need assistance applying this. PR target/112413 gcc/ * config/m68k/linux.h (ASM_RETURN_CASE_JUMP): For TARGET_LONG_JUMP_TABLE_OFFSETS, reference the jump table via its label. * config/m68k/m68kelf.h (ASM_RETURN_CASE_JUMP): Likewise. * config/m68k/netbsd-elf.h (ASM_RETURN_CASE_JUMP): Likewise.
2023-12-11aarch64: enable mixed-types for aarch64 simdclonesAndre Vieira35-113/+646
This patch enables the use of mixed-types for simd clones for AArch64, adds aarch64 as a target_vect_simd_clones and corrects the way the simdlen is chosen for non-specified simdlen clauses according to the 'Vector Function Application Binary Interface Specification for AArch64'. Additionally this patch also restricts combinations of simdlen and return/argument types that map to vectors larger than 128 bits as we currently do not have a way to represent these types in a way that is consistent internally and externally. gcc/ChangeLog: * config/aarch64/aarch64.cc (lane_size): New function. (aarch64_simd_clone_compute_vecsize_and_simdlen): Determine simdlen according to NDS rule and reject combination of simdlen and types that lead to vectors larger than 128bits. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add aarch64 targets to vect_simd_clones. * c-c++-common/gomp/declare-variant-14.c: Adapt test for aarch64. * c-c++-common/gomp/pr60823-1.c: Likewise. * c-c++-common/gomp/pr60823-2.c: Likewise. * c-c++-common/gomp/pr60823-3.c: Likewise. * g++.dg/gomp/attrs-10.C: Likewise. * g++.dg/gomp/declare-simd-1.C: Likewise. * g++.dg/gomp/declare-simd-3.C: Likewise. * g++.dg/gomp/declare-simd-4.C: Likewise. * g++.dg/gomp/declare-simd-7.C: Likewise. * g++.dg/gomp/declare-simd-8.C: Likewise. * g++.dg/gomp/pr88182.C: Likewise. * gcc.dg/declare-simd.c: Likewise. * gcc.dg/gomp/declare-simd-1.c: Likewise. * gcc.dg/gomp/declare-simd-3.c: Likewise. * gcc.dg/gomp/pr87887-1.c: Likewise. * gcc.dg/gomp/pr87895-1.c: Likewise. * gcc.dg/gomp/pr89246-1.c: Likewise. * gcc.dg/gomp/pr99542.c: Likewise. * gcc.dg/gomp/simd-clones-2.c: Likewise. * gcc.dg/vect/vect-simd-clone-1.c: Likewise. * gcc.dg/vect/vect-simd-clone-2.c: Likewise. * gcc.dg/vect/vect-simd-clone-4.c: Likewise. * gcc.dg/vect/vect-simd-clone-5.c: Likewise. * gcc.dg/vect/vect-simd-clone-6.c: Likewise. * gcc.dg/vect/vect-simd-clone-7.c: Likewise. * gcc.dg/vect/vect-simd-clone-8.c: Likewise. * gfortran.dg/gomp/declare-simd-2.f90: Likewise. * gfortran.dg/gomp/declare-simd-coarray-lib.f90: Likewise. * gfortran.dg/gomp/declare-variant-14.f90: Likewise. * gfortran.dg/gomp/pr79154-1.f90: Likewise. * gfortran.dg/gomp/pr83977.f90: Likewise. libgomp/ChangeLog: * testsuite/libgomp.c/declare-variant-1.c: Adapt test for aarch64. * testsuite/libgomp.fortran/declare-simd-1.f90: Likewise.
2023-12-11c++: alias CTAD and specializations tablePatrick Palka4-1/+29
A rewritten guide for alias CTAD isn't really a specialization of the original guide, so we shouldn't register it as such. This avoids an ICE in the below modules testcase for which we otherwise crash due to the guide's empty DECL_CONTEXT when walking the specializations table. It also preemptively avoids the same ICE in modules/concept-6 in C++23 mode with the inherited CTAD patch. gcc/cp/ChangeLog: * pt.cc (alias_ctad_tweaks): Pass use_spec_table=false to tsubst_decl. gcc/testsuite/ChangeLog: * g++.dg/modules/concept-8.h: New test. * g++.dg/modules/concept-8_a.H: New test. * g++.dg/modules/concept-8_b.C: New test.
2023-12-11RISC-V: testsuite: Fix strcmp-run.c test.Robin Dapp3-14/+15
This fixes expectations in the strcmp-run test which would sometimes fail with newlib. The test expects libc strcmp return values and asserts the vectorized result is similar to those. Therefore hard-code the expected results instead of relying on a strcmp call. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/builtin/strcmp-run.c: Adjust test expectation and target selector. * gcc.target/riscv/rvv/autovec/builtin/strlen-run.c: Adjust target selector. * gcc.target/riscv/rvv/autovec/builtin/strncmp-run.c: Ditto.
2023-12-11OpenMP: Support acquires/release in 'omp require atomic_default_mem_order'Tobias Burnus16-32/+291
This is an OpenMP 5.2 feature. gcc/c/ChangeLog: * c-parser.cc (c_parser_omp_requires): Handle acquires/release in atomic_default_mem_order clause. (c_parser_omp_atomic): Update. gcc/cp/ChangeLog: * parser.cc (cp_parser_omp_requires): Handle acquires/release in atomic_default_mem_order clause. (cp_parser_omp_atomic): Update. gcc/fortran/ChangeLog: * gfortran.h (enum gfc_omp_requires_kind): Add OMP_REQ_ATOMIC_MEM_ORDER_ACQUIRE and OMP_REQ_ATOMIC_MEM_ORDER_RELEASE. (gfc_namespace): Add a 7th bit to omp_requires. * module.cc (enum ab_attribute): Add AB_OMP_REQ_MEM_ORDER_ACQUIRE and AB_OMP_REQ_MEM_ORDER_RELEASE (mio_symbol_attribute): Handle it. * openmp.cc (gfc_omp_requires_add_clause): Update for acquire/release. (gfc_match_omp_requires): Likewise. (gfc_match_omp_atomic): Handle them for atomic_default_mem_order. * parse.cc: Likewise. gcc/testsuite/ChangeLog: * c-c++-common/gomp/requires-3.c: Update for now valid code. * gfortran.dg/gomp/requires-3.f90: Likewise. * gfortran.dg/gomp/requires-2.f90: Update dg-error. * gfortran.dg/gomp/requires-5.f90: Likewise. * c-c++-common/gomp/requires-5.c: New test. * c-c++-common/gomp/requires-6.c: New test. * c-c++-common/gomp/requires-7.c: New test. * c-c++-common/gomp/requires-8.c: New test. * gfortran.dg/gomp/requires-10.f90: New test. * gfortran.dg/gomp/requires-11.f90: New test.
2023-12-11OpenMP: Minor '!$omp allocators' cleanupTobias Burnus1-2/+6
gcc/fortran/ChangeLog: * trans-openmp.cc (gfc_omp_call_add_alloc, gfc_omp_call_is_alloc): Set 'fn spec'. libgomp/ChangeLog: * libgomp_g.h (GOMP_add_alloc, GOMP_is_alloc): Add.
2023-12-11ada: Fix Ada bootstrap on FreeBSDRainer Orth1-1/+6
Ada bootstrap on FreeBSD/amd64 was also broken by the recent warning changes: terminals.c: In function 'allocate_pty_desc': terminals.c:1200:12: error: implicit declaration of function 'openpty'; did you mean 'openat'? [-Wimplicit-function-declaration] 1200 | status = openpty (&master_fd, &slave_fd, NULL, NULL, NULL); | ^~~~~~~ | openat terminals.c: At top level: terminals.c:1268:9: warning: "TABDLY" redefined 1268 | #define TABDLY 0 | ^~~~~~ In file included from /usr/include/termios.h:38, from terminals.c:1109: /usr/include/sys/_termios.h:111:9: note: this is the location of the previous definition 111 | #define TABDLY 0x00000004 /* tab delay mask */ | ^~~~~~ make[7]: *** [../gcc-interface/Makefile:302: terminals.o] Error 1 Fixed by including the necessary header and guarding the fallback definition of TABDLY. This allowed a 64-bit-only bootstrap on x86_64-unknown-freebsd14.0 to complete successfully. 2023-12-11 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> gcc/ada: * terminals.c [__FreeBSD__]: Include <libutil.h>. (TABDLY): Only define if missing.
2023-12-11RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASSJuzhe-Zhong2-3/+29
This patch fixes an ICE on record_use during RTL_SSA initialization RISC-V backend VSETVL PASS. This is the ICE: 0x11a8603 partial_subreg_p(machine_mode, machine_mode) ../../../../gcc/gcc/rtl.h:3187 0x3b695eb rtl_ssa::function_info::record_use(rtl_ssa::function_info::build_info&, rtl_ssa::insn_info*, rtx_obj_reference) ../../../../gcc/gcc/rtl-ssa/insns.cc:524 In record_use: if (HARD_REGISTER_NUM_P (regno) && partial_subreg_p (use->mode (), mode)) Assertion failed on partial_subreg_p which is: inline bool partial_subreg_p (machine_mode outermode, machine_mode innermode) { /* Modes involved in a subreg must be ordered. In particular, we must always know at compile time whether the subreg is paradoxical. */ poly_int64 outer_prec = GET_MODE_PRECISION (outermode); poly_int64 inner_prec = GET_MODE_PRECISION (innermode); gcc_checking_assert (ordered_p (outer_prec, inner_prec)); -----> cause ICE. return maybe_lt (outer_prec, inner_prec); } RISC-V VSETVL PASS is an advanced lazy vsetvl insertion PASS after RA (register allocation). The rootcause is that we have a pattern (reduction instruction) that includes both VLA (length-agnostic) and VLS (fixed-length) modes. (insn 168 173 170 31 (set (reg:RVVM1SI 101 v5 [311]) (unspec:RVVM1SI [ (unspec:V32BI [ (const_vector:V32BI [ (const_int 1 [0x1]) repeated x32 ]) (reg:DI 30 t5 [312]) (const_int 2 [0x2]) repeated x2 (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (unspec:RVVM1SI [ (reg:V32SI 96 v0 [orig:185 vect__96.40 ] [185]) -----> VLS mode NUNITS = 32 elements. (reg:RVVM1SI 113 v17 [439]) -----> VLA mode NUNITS = [8, 8] elements. ] UNSPEC_REDUC_XOR) (unspec:RVVM1SI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF) ] UNSPEC_REDUC)) 15948 {pred_redxorv32si} In this case, record_use is trying to check partial_subreg_p (use->mode (), mode) for RTX = (reg:V32SI 96 v0 [orig:185 vect__96.40 ] [185]). use->mode () == V32SImode, wheras mode = RVVM1SImode. Then it ICE since they are !ordered_p. Set the use mode as the biggest mode which is natural fall back mode. gcc/ChangeLog: * rtl-ssa/insns.cc (function_info::record_use): Add !ordered_p case. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: New test.
2023-12-11RISC-V: Robostify shuffle index used by vrgather and fix regressionJuzhe-Zhong2-33/+49
Notice there are some regression FAILs: FAIL: gcc.target/riscv/rvv/autovec/pr110950.c -O3 -ftree-vectorize scan-assembler-times vslide1up\\.vx 1 FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax scan-assembler-times vrgather\\.vv\\tv[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+ 19 FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax scan-assembler-times vrgatherei16\\.vv\\tv[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+ 12 FAIL: gcc.target/riscv/rvv/autovec/vls/perm-4.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vrgather\\.vv\\tv[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+ 19 FAIL: gcc.target/riscv/rvv/autovec/vls/perm-4.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vrgatherei16\\.vv\\tv[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+ 12 pr110950 is not a regression, adapt testcase is enough. The rest FAILs which is caused by this patch: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d9dd06ad51b7479f09acb88adf404664a1e18b2a need to be recovered back. Robostify the gather index to fixe those FAILs. gcc/ChangeLog: * config/riscv/riscv-v.cc (get_gather_index_mode): New function. (shuffle_series_patterns): Robostify shuffle index. (shuffle_generic_patterns): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr110950.c: Adapt test.
2023-12-11Testsuite, asan, darwin: Adjust output patternFrancois-Xavier Coudert1-1/+1
Since the last import from upstream libsanitizer, the output has changed and now looks more like this: READ of size 6 at 0x7ff7beb2a144 thread T0 #0 0x101cf7796 in MemcmpInterceptorCommon(void*, int (*)(void const*, void const*, unsigned long), void const*, void const*, unsigned long) sanitizer_common_interceptors.inc:813 #1 0x101cf7b99 in memcmp sanitizer_common_interceptors.inc:840 #2 0x108a0c39f in __stack_chk_guard+0xf (dyld:x86_64+0x8039f) so let's adjust the pattern accordingly. gcc/testsuite/ChangeLog: * c-c++-common/asan/memcmp-1.c: Adjust pattern on darwin.
2023-12-11aarch64: arm_neon.h - Fix -Wincompatible-pointer-types errorsVictor Do Nascimento1-13/+21
In the Linux kernel, u64/s64 are [un]signed long long, not [un]signed long. This means that when the `arm_neon.h' header is used by the kernel, any use of the `uint64_t' / `in64_t' types needs to be correctly cast to the correct `__builtin_aarch64_simd_di' / `__builtin_aarch64_simd_df' types when calling the relevant ACLE builtins. This patch adds the necessary fixes to ensure that `vstl1_*' and `vldap1_*' intrinsics are correctly defined for use by the kernel. gcc/ChangeLog: * config/aarch64/arm_neon.h (vldap1_lane_u64): Add `const' to `__builtin_aarch64_simd_di *' cast. (vldap1q_lane_u64): Likewise. (vldap1_lane_s64): Cast __src to `const __builtin_aarch64_simd_di *'. (vldap1q_lane_s64): Likewise. (vldap1_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'. (vldap1q_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'. (vldap1_lane_p64): Add `const' to `__builtin_aarch64_simd_di *' cast. (vldap1q_lane_p64): Add `const' to `__builtin_aarch64_simd_di *' cast. (vstl1_lane_u64): remove stray `const'. (vstl1_lane_s64): Cast __src to `__builtin_aarch64_simd_di *'. (vstl1q_lane_s64): Likewise. (vstl1_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'. (vstl1q_lane_f64): Likewise.
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