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2025-01-20aarch64: Add missing simd requirements for INS [PR118531]Richard Sandiford4-3/+30
2025-01-20d: Fix failing test with 32-bit compiler [PR114434]Iain Buclaw1-2/+2
2025-01-20Fortran: do not copy back for parameter actual arguments [PR81978]Harald Anlauf3-4/+124
2025-01-20c++: Handle RAW_DATA_CST in make_tree_vector_from_ctor [PR118528]Jakub Jelinek3-1/+57
2025-01-20RISC-V: Correct the mode that is causing the program to fail for XTheadCondMovJin Ma2-2/+14
2025-01-20inline: Purge the abnormal edges as needed in fold_marked_statements [PR118077]Andrew Pinski2-2/+43
2025-01-20arm, testsuite: fix fast-math-bb-slp-complex-mla-float.c dg-add-optionsChristophe Lyon1-1/+1
2025-01-20arm, testsuite: remove duplicate dg-add-options arm_v8_3a_complex_neonChristophe Lyon2-2/+0
2025-01-20tree-optimization/117875 - missed SLP vectorizationRichard Biener1-1/+2
2025-01-20LoongArch: Improve reassociation for bitwise operation and left shift [PR 115...Xi Ruoyao5-34/+239
2025-01-20LoongArch: Simplify using bstr{ins,pick} instructions for andXi Ruoyao4-48/+53
2025-01-20testsuite: Fix name of PR116348 test caseXi Ruoyao1-0/+0
2025-01-20tree-optimization/118552 - failed LC SSA update after unrollingRichard Biener2-3/+44
2025-01-20nvptx: Gracefully handle '-mptx=3.1' if neither sm_30 nor sm_35 multilib vari...Thomas Schwinge1-3/+6
2025-01-20tree, c++: Consider TARGET_EXPR invariant like SAVE_EXPR [PR118509]Jakub Jelinek3-1/+25
2025-01-20tree-ssa-dce: Fix calloc handling [PR118224]Jakub Jelinek2-1/+3
2025-01-20s390: Update vec_(load,store)_len(,_r)Stefan Schulze Frielinghaus3-20/+28
2025-01-20s390: Vector shift: Add 128-bit integer supportStefan Schulze Frielinghaus14-102/+570
2025-01-20s390: arch15: Vector maximum/minimum: Add 128-bit integer supportStefan Schulze Frielinghaus6-29/+235
2025-01-20s390: arch15: Vector load positive: Add 128-bit integer supportStefan Schulze Frielinghaus4-5/+73
2025-01-20s390: arch15: Vector compare: Add 128-bit integer supportStefan Schulze Frielinghaus5-60/+143
2025-01-20s390: arch15: Vector devide/remainderStefan Schulze Frielinghaus9-0/+228
2025-01-20s390: arch15: Count leading/trailing zerosStefan Schulze Frielinghaus5-17/+52
2025-01-20s390: arch15: Vector generate element masksStefan Schulze Frielinghaus5-0/+38
2025-01-20s390: arch15: Vector evalStefan Schulze Frielinghaus14-0/+154
2025-01-20s390: arch15: Vector blendStefan Schulze Frielinghaus5-0/+56
2025-01-20s390: arch15: Bit deposit and extractStefan Schulze Frielinghaus3-0/+36
2025-01-20s390: arch15: Load indexed addressStefan Schulze Frielinghaus8-0/+358
2025-01-20s390: arch15: New instruction variants supporting 128-bit integerStefan Schulze Frielinghaus5-124/+329
2025-01-20s390: arch15: Prepare for future builtinsStefan Schulze Frielinghaus4-0/+38
2025-01-20s390: Bump __VEC__ and add 128-bit integer zvector typesStefan Schulze Frielinghaus2-2/+22
2025-01-20s390: arch15: Prepare for a future architectureStefan Schulze Frielinghaus9-5/+45
2025-01-20s390: Sort definitions in vecintrin.hStefan Schulze Frielinghaus1-114/+115
2025-01-20s390: Stay scalar for TOINTVEC/tointvecStefan Schulze Frielinghaus1-6/+6
2025-01-20RISC-V: Add sifive_vector.hKito Cheng2-1/+33
2025-01-20i386: Fix wrong insn generated by shld/shrd ndd split [PR118510]Hongyu Wang2-32/+26
2025-01-20Daily bump.GCC Administrator3-1/+31
2025-01-19i386: Reorder *movdi_internal ISA attribute by ascending alternative indexUros Bizjak1-2/+2
2025-01-19i386/testsuite: Fix gcc.target/i386/pr118067*.c testsUros Bizjak2-3/+3
2025-01-19Regenerate sparc.opt.urlsMark Wielaard1-0/+3
2025-01-19testsuite: Fixes for test case pr117546.cDimitar Dimitrov1-1/+3
2025-01-19doc: Move modula2.org link to httpsGerald Pfeifer1-1/+1
2025-01-19doc: Adjust link to OpenMP specificationsGerald Pfeifer1-1/+1
2025-01-19Daily bump.GCC Administrator5-1/+252
2025-01-18d: Merge upstream dmd, druntime d115713410, phobos 1b242048c.Iain Buclaw44-361/+258
2025-01-18c++: Copy over further 2 flags for !TREE_PUBLIC in copy_linkage [PR118513]Jakub Jelinek3-0/+39
2025-01-18[RISC-V][PR target/116308] Fix generation of initial RTL for atomicsJeff Law2-3/+10
2025-01-18Fix uniqueness of symtab_node::get_dump_name.Michal Jires7-23/+26
2025-01-18Fix bootstrap failure on SPARC with -O3 -mcpu=niagara4Eric Botcazou9-47/+81
2025-01-18RISC-V: Disable RV64-only crc testcases for RV32Bohan Lei2-6/+4