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2022-10-11Implement ABS_EXPR operator for frange.Aldy Hernandez2-0/+108
Implementing ABS_EXPR allows us to fold certain __builtin_inf calls since they are expanded into calls to involving ABS_EXPR. This is an adaptation of the integer version. gcc/ChangeLog: * range-op-float.cc (class foperator_abs): New. (floating_op_table::floating_op_table): Add ABS_EXPR entry. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/vrp-float-abs-1.c: New test.
2022-10-11Implement op1_range operators for unordered comparisons.Aldy Hernandez1-0/+205
gcc/ChangeLog: * range-op-float.cc (foperator_unordered_le::op1_range): New. (foperator_unordered_le::op2_range): New. (foperator_unordered_gt::op1_range): New. (foperator_unordered_gt::op2_range): New. (foperator_unordered_ge::op1_range): New. (foperator_unordered_ge::op2_range): New. (foperator_unordered_equal::op1_range): New.
2022-10-11Share common ordered comparison code with UN*_EXPR.Aldy Hernandez1-12/+128
Most unordered comparisons can use the result from the ordered version, if the operands are known not to be NAN or if the result is true. gcc/ChangeLog: * range-op-float.cc (class foperator_unordered_lt): New. (class foperator_relop_unknown): Remove (class foperator_unordered_le): New. (class foperator_unordered_gt): New. (class foperator_unordered_ge): New. (class foperator_unordered_equal): New. (floating_op_table::floating_op_table): Replace all UN_EXPR entries with their appropriate fop_unordered_* counterpart.
2022-10-11Move TRUE case first in range-op.cc.Aldy Hernandez1-21/+21
It's incredibly annoying that some of the BRS_TRUE cases come after BRS_FALSE, if only because we're not consistent. Having random ordering increases the changes of thinkos when adapting the irange code to floats. gcc/ChangeLog: * range-op.cc (operator_equal::op1_range): Move BRS_TRUE case up. (operator_lt::op2_range): Same. (operator_le::op2_range): Same. (operator_gt::op2_range): Same. (operator_ge::op2_range): Same.
2022-10-11tree-optimization/107212 - SLP reduction of reduction pathsRichard Biener3-7/+63
The following fixes an issue with how we handle epilogue generation for SLP reductions of reduction paths where the actual live lanes are not "canonical". We need to make sure to identify all live lanes as reductions and thus have to iterate over all participating SLP lanes when walking the reduction SSA use-def chain. Also the previous attempt likely to mitigate such issue in vectorizable_live_operation is misguided and has to be removed. PR tree-optimization/107212 * tree-vect-loop.cc (vectorizable_reduction): Make sure to set STMT_VINFO_REDUC_DEF for all live lanes in a SLP reduction. (vectorizable_live_operation): Do not pun to the SLP node representative for reduction epilogue generation. * gcc.dg/vect/pr107212-1.c: New testcase. * gcc.dg/vect/pr107212-2.c: Likewise.
2022-10-11amdgcn: vector testsuite tweaksAndrew Stubbs14-14/+31
The testsuite needs a few tweaks following my patches to add multiple vector sizes for amdgcn. gcc/testsuite/ChangeLog: * gcc.dg/pr104464.c: Xfail on amdgcn. * gcc.dg/signbit-2.c: Likewise. * gcc.dg/signbit-5.c: Likewise. * gcc.dg/vect/bb-slp-68.c: Likewise. * gcc.dg/vect/bb-slp-cond-1.c: Change expectations on amdgcn. * gcc.dg/vect/bb-slp-subgroups-3.c: Likewise. * gcc.dg/vect/no-vfa-vect-depend-2.c: Change expectations for multiple vector sizes. * gcc.dg/vect/pr33953.c: Likewise. * gcc.dg/vect/pr65947-12.c: Likewise. * gcc.dg/vect/pr65947-13.c: Likewise. * gcc.dg/vect/pr80631-2.c: Likewise. * gcc.dg/vect/slp-reduc-4.c: Likewise. * gcc.dg/vect/trapv-vect-reduc-4.c: Likewise. * lib/target-supports.exp (available_vector_sizes): Add more sizes for amdgcn.
2022-10-11amdgcn: Add vector integer negate insnAndrew Stubbs1-0/+13
Another example of the vectorizer needing explicit insns where the scalar expander just works. gcc/ChangeLog: * config/gcn/gcn-valu.md (neg<mode>2): New define_expand.
2022-10-11amdgcn: vec_init for multiple vector sizesAndrew Stubbs2-26/+143
Implements vec_init when the input is a vector of smaller vectors, or of vector MEM types, or a smaller vector duplicated several times. gcc/ChangeLog: * config/gcn/gcn-valu.md (vec_init<V_ALL:mode><V_ALL_ALT:mode>): New. * config/gcn/gcn.cc (GEN_VN): Add andvNsi3, subvNsi3. (GEN_VNM): Add gathervNm_expr. (GEN_VN_NOEXEC): Add vec_seriesvNsi. (gcn_expand_vector_init): Add initialization of vectors from smaller vectors.
2022-10-11amdgcn: Add vec_extract for partial vectorsAndrew Stubbs3-1/+44
Add vec_extract expanders for all valid pairs of vector types. gcc/ChangeLog: * config/gcn/gcn-protos.h (get_exec): Add prototypes for two variants. * config/gcn/gcn-valu.md (vec_extract<V_ALL:mode><V_ALL_ALT:mode>): New define_expand. * config/gcn/gcn.cc (get_exec): Export the existing function. Add a new overload variant.
2022-10-11amdgcn: Resolve insn conditions at compile timeAndrew Stubbs2-4/+30
GET_MODE_NUNITS isn't a compile time constant, so we end up with many impossible insns in the machine description. Adding MODE_VF allows the insns to be eliminated completely. gcc/ChangeLog: * config/gcn/gcn-valu.md (<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): Use MODE_VF. (<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): Likewise. * config/gcn/gcn.h (MODE_VF): New macro.
2022-10-11amdgcn: add multiple vector sizesAndrew Stubbs4-425/+938
The vectors sizes are simulated using implicit masking, but they make life easier for the autovectorizer and SLP passes. gcc/ChangeLog: * config/gcn/gcn-modes.def (VECTOR_MODE): Add new modes V32QI, V32HI, V32SI, V32DI, V32TI, V32HF, V32SF, V32DF, V16QI, V16HI, V16SI, V16DI, V16TI, V16HF, V16SF, V16DF, V8QI, V8HI, V8SI, V8DI, V8TI, V8HF, V8SF, V8DF, V4QI, V4HI, V4SI, V4DI, V4TI, V4HF, V4SF, V4DF, V2QI, V2HI, V2SI, V2DI, V2TI, V2HF, V2SF, V2DF. (ADJUST_ALIGNMENT): Likewise. * config/gcn/gcn-protos.h (gcn_full_exec): Delete. (gcn_full_exec_reg): Delete. (gcn_scalar_exec): Delete. (gcn_scalar_exec_reg): Delete. (vgpr_1reg_mode_p): Use inner mode to identify vector registers. (vgpr_2reg_mode_p): Likewise. (vgpr_vector_mode_p): Use VECTOR_MODE_P. * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF, V_QIHI, V_1REG, V_INT_1REG, V_INT_1REG_ALT, V_FP_1REG, V_2REG, V_noQI, V_noHI, V_INT_noQI, V_INT_noHI, V_ALL, V_ALL_ALT, V_INT, V_FP): Add additional vector modes. (V64_SI, V64_DI, V64_ALL, V64_FP): New iterators. (scalar_mode, SCALAR_MODE, vnsi, VnSI, vndi, VnDI, sdwa): Add additional vector mode mappings. (mov<mode>): Implement vector length conversions. (ldexp<mode>3<exec>): Use VnSI. (frexp<mode>_exp2<exec>): Likewise. (VCVT_MODE, VCVT_FMODE, VCVT_IMODE): Add additional vector modes. (reduc_<reduc_op>_scal_<mode>): Use V64_ALL. (fold_left_plus_<mode>): Use V64_FP. (*<reduc_op>_dpp_shr_<mode>): Use V64_1REG. (*<reduc_op>_dpp_shr_<mode>): Use V64_DI. (*plus_carry_dpp_shr_<mode>): Use V64_INT_1REG. (*plus_carry_in_dpp_shr_<mode>): Use V64_SI. (*plus_carry_dpp_shr_<mode>): Use V64_DI. (mov_from_lane63_<mode>): Use V64_2REG. * config/gcn/gcn.cc (VnMODE): New function. (gcn_can_change_mode_class): Support multiple vector sizes. (gcn_modes_tieable_p): Likewise. (gcn_operand_part): Likewise. (gcn_scalar_exec): Delete function. (gcn_scalar_exec_reg): Delete function. (gcn_full_exec): Delete function. (gcn_full_exec_reg): Delete function. (gcn_inline_fp_constant_p): Support multiple vector sizes. (gcn_fp_constant_p): Likewise. (A): New macro. (GEN_VN_NOEXEC): New macro. (GEN_VNM_NOEXEC): New macro. (GEN_VN): New macro. (GEN_VNM): New macro. (GET_VN_FN): New macro. (CODE_FOR): New macro. (CODE_FOR_OP): New macro. (gen_mov_with_exec): Delete function. (gen_duplicate_load): Delete function. (gcn_expand_vector_init): Support multiple vector sizes. (strided_constant): Likewise. (gcn_addr_space_legitimize_address): Likewise. (gcn_expand_scalar_to_vector_address): Likewise. (gcn_expand_scaled_offsets): Likewise. (gcn_secondary_reload): Likewise. (gcn_valid_cvt_p): Likewise. (gcn_expand_builtin_1): Likewise. (gcn_make_vec_perm_address): Likewise. (gcn_vectorize_vec_perm_const): Likewise. (gcn_vector_mode_supported_p): Likewise. (gcn_autovectorize_vector_modes): New hook. (gcn_related_vector_mode): Support multiple vector sizes. (gcn_expand_dpp_shr_insn): Add FIXME comment. (gcn_md_reorg): Support multiple vector sizes. (print_reg): Likewise. (print_operand): Likewise. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): New hook.
2022-10-11vect: Teach vectorizer how to handle bitfield accessesAndre Vieira14-31/+1079
gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test.
2022-10-11Add define_insn_and_split to support general version of "kxnor".liuhongt2-0/+109
For genereal_reg_operand, it will be splitted into xor + not. For mask_reg_operand, it will be splitted with UNSPEC_MASK_OP just like what we did for other logic operations. The patch will optimize xor+not to kxnor when possible. gcc/ChangeLog: PR target/107093 * config/i386/i386.md (*notxor<mode>_1): New post_reload define_insn_and_split. (*notxorqi_1): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr107093.c: New test.
2022-10-11[PR107195] Set range to zero when nonzero mask is 0.Aldy Hernandez3-0/+36
When solving 0 = _15 & 1, we calculate _15 as: [irange] int [-INF, -2][0, +INF] NONZERO 0xfffffffe The known value of _15 is [0, 1] NONZERO 0x1 which is intersected with the above, yielding: [0, 1] NONZERO 0x0 This eventually gets copied to a _Bool [0, 1] NONZERO 0x0. This is problematic because here we have a bool which is zero, but returns false for irange::zero_p, since the latter does not look at nonzero bits. This causes logical_combine to assume the range is not-zero, and all hell breaks loose. I think we should just normalize a nonzero mask of 0 to [0, 0] at creation, thus avoiding all this. PR tree-optimization/107195 gcc/ChangeLog: * value-range.cc (irange::set_range_from_nonzero_bits): Set range to [0,0] when nonzero mask is 0. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr107195-1.c: New test. * gcc.dg/tree-ssa/pr107195-2.c: New test.
2022-10-11Generic configury support for shared libs on VxWorksOlivier Hainque2-2/+55
This change adds the configury bits to activate the build of shared libs on VxWorks ports configured with --enable-shared, for libraries variants where this is generally supported (rtp, code model !large - currently not compatible with -fPIC). Set lt_cv_deplibs_check_method in libtool.m4, so the build of libraries know how to establish dependencies. This is useful in configurations such as aarch64 where proper support of LSE relies on accurate dependency information between libstdc++ and libgcc_s to begin with. Regenerate configure scripts to reflect libtool.m4 change. 2022-10-09 Olivier Hainque <hainque@adacore.com> * libtool.m4 (*vxworks*): When enable_shared, set dynamic_linker and friends for rtp !large. Assume the linker has the required abilities and set lt_cv_deplibs_check_method. gcc/ * config.gcc (*vxworks*): Add t-slibgcc fragment if enable_shared. libgcc/ * config.host (*vxworks*): When enable_shared, add libgcc and crtstuff "shared" fragments for rtp except large code model. (aarch64*-wrs-vxworks7*): Remove t-slibgcc-libgcc from the list of fragments. 2022-10-09 Olivier Hainque <hainque@adacore.com> gcc/ * configure: Regenerate. libatomic/ * configure: Regenerate. libbacktrace/ * configure: Regenerate. libcc1/ * configure: Regenerate. libffi/ * configure: Regenerate. libgfortran/ * configure: Regenerate. libgomp/ * configure: Regenerate. libitm/ * configure: Regenerate. libobjc/ * configure: Regenerate. liboffloadmic/ * configure: Regenerate. liboffloadmic/ * plugin/configure: Regenerate. libphobos/ * configure: Regenerate. libquadmath/ * configure: Regenerate. libsanitizer/ * configure: Regenerate. libssp/ * configure: Regenerate. libstdc++-v3/ * configure: Regenerate. libvtv/ * configure: Regenerate. lto-plugin/ * configure: Regenerate. zlib/ * configure: Regenerate.
2022-10-11Tigthen the addition of -lgcc_eh to vxworks_libgcc_specOlivier Hainque1-4/+44
This change refines VXWORKS_LIBGCC_SPEC wrt the inclusion of -lgcc_eh. Unless the compiler features support for dual sjlj and table based eh, libgcc_eh.a is available only with multilib variants for which we build a shared lib (mrtp on VxWorks). Rework logic to handle absence of libgcc_s for -mrtp -mcmodel=large, using a conditional expr kind of spec. The gthread support in libgcc_eh might resort to libgcc functions on some targets, e.g. cas synchronisation routines on aarch64. Arrange to append -lgcc also after -lgcc_eh in VXWORKS_LIBGCC_SPEC. 2022-10-09 Olivier Hainque <hainque@adacore.com> gcc/ * config/vxworks.h (VX_LGCC_EH_SO0, VX_LGCC_EH_SO1): New internal macros. (VXWORKS_LIBGCC_SPEC): Use them and document.
2022-10-11ranger: add override keywordMartin Liska1-1/+1
Fixes the following clang warning: gcc/gimple-range-op.cc:310:16: warning: 'fold_range' overrides a member function but is not marked 'override' [-Winconsistent-missing-override] gcc/ChangeLog: * gimple-range-op.cc: Add override keyword.
2022-10-10Fix PR107193.Eugene Rozenfeld1-3/+4
The bug was introduced in f30e9fd33e56a5a721346ea6140722e1b193db42. A variable (cur_locus_e) was incorrectly declared inside a loop. I also moved two other declarations (last and locus) down to make the code more clear. Tested on x86_64-pc-linux-gnu. gcc/ChangeLog: PR debug/107193 * tree-cfg.cc (assign_discriminators): Move declaration of cur_locus_e out of the loop.
2022-10-11Optimize nested permutation to single VEC_PERM_EXPR [PR54346]Liwei Xu2-0/+54
This patch implemented the optimization in PR 54346, which Merges c = VEC_PERM_EXPR <a, b, VCST0>; d = VEC_PERM_EXPR <c, c, VCST1>; to d = VEC_PERM_EXPR <a, b, NEW_VCST>; Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} tree-ssa/forwprop-19.c fail to pass but I'm not sure whether it is ok to removed it. gcc/ChangeLog: PR tree-optimization/54346 * match.pd: Merge the index of VCST then generates the new vec_perm. gcc/testsuite/ChangeLog: * gcc.dg/pr54346.c: New test. Co-authored-by: liuhongt <hongtao.liu@intel.com>
2022-10-11[PR rtl-optimization/107182] Clear EDGE_CROSSING for jump->ret optimizationJeff Law1-0/+1
When turning a jump to a return into a return, we need to clear EDGE_CROSSING of the fallthru edge to prevent a checking failure. I considered not applying the transformation when the edge has EDGE_CROSSING set, but it still seems like we ought to eliminate the unnecessary jump in that case. gcc/ PR rtl-optimization/107182 * cfgrtl.cc (fixup_reorder_chain): When optimizing a jump to a return, clear EDGE_CROSSING on the appropriate edge.
2022-10-11RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" ↵Ju-Zhe Zhong3-25/+25
into "name". gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move from config/riscv/riscv-vector-builtins.h. (DEF_RVV_TYPE): Change USER_NAME to NAME. (register_vector_type): Change user_name to name. * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Change USER_NAME to NAME. * config/riscv/riscv-vector-builtins.h (struct vector_type_info): Move to riscv-vector-builtins.cc. (DEF_RVV_TYPE): Change USER_NAME to NAME. Reviewed-by: Kito Cheng <kito.cheng@sifive.com>
2022-10-11RISC-V: Add missing vsetvl instruction type.Ju-Zhe Zhong1-1/+2
When implementing built-in framework, I notice I missed vsetvl instruction type, so add it in a single patch preparing for the following patches. gcc/ChangeLog: * config/riscv/riscv.md: Add vsetvl instruction type. Reviewed-by: Kito Cheng <kito.cheng@sifive.com>
2022-10-11Daily bump.GCC Administrator6-1/+240
2022-10-10c++: Lambda context manglingNathan Sidwell10-6/+71
VAR and FIELD decls can become part of a lambda context, when the lambda is 'attached' to that entity (It's a C++20 ODR thing that was discovered with modules, but is actually separate.) We were not marking those decls as substitution candidates, leading to demangling failures and variance from other compilers. This patch bumps the ABI, and adds the contexts them to the substitution table. This is the intent of the ABI. gcc/ * common.opt (-fabi-version=): Document 18. * doc/invoke.texi (-fabi-version): Document 18. gcc/c-family/ * c-opts.cc (c_common_post_options): Bump abi to 18. gcc/cp/ * mangle.cc (write_prefix): Add VAR_DECL & FIELD_DECL to substitution table under abi=18. Note possible mismatch. gcc/testsuite/ * g++.dg/abi/lambda-ctx1-17.C: New. * g++.dg/abi/lambda-ctx1-18.C: New. * g++.dg/abi/lambda-ctx1-18vs17.C: New. * g++.dg/abi/lambda-ctx1.h: New. * g++.dg/abi/lambda-vis.C: Adjust expected mangles. * g++.dg/abi/macro0.C: Adjust.
2022-10-10compiler: treat S("") as a string constantIan Lance Taylor2-1/+4
The compiler neglected to notice that a conversion from a string constant to a string type was a valid string constant. No test case because this only caused a compiler failure when compiling without optimization, which is not the normal case, and is not a case that we test. Fixes golang/go#56113 Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/441555
2022-10-10compiler: only build thunk struct type when it is neededIan Lance Taylor3-30/+11
Instead of building the thunk struct type in the determine_types pass, build it when we need it. That ensures that we are consistent in determining whether an argument is constant. We no longer need to add a field for a call to recover, as the simplify_thunk_statements pass runs after the build_recover_thunks pass, so the additional argument will already have been added to the call. The test case is https://go.dev/cl/440297. Fixes golang/go#56109 Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/440298
2022-10-10c-family: ICE with [[gnu::nocf_check]] [PR106937]Marek Polacek4-45/+86
When getting the name of an attribute, we ought to use get_attribute_name, which handles both [[]] and __attribute__(()) forms. Failure to do so may result in an ICE, like here. pp_c_attributes_display wasn't able to print the [[]] form of attributes, so this patch teaches it to. When printing a pointer to function with a standard attribute, the attribute should be printed after the parameter-list. With this patch we print: aka 'void (*)(int) [[gnu::nocf_check]]' or, in C++ with noexcept: aka 'void (*)(int) noexcept [[gnu::nocf_check]]' pp_c_attributes has been unused since its introduction in r56273 so this patch removes it. PR c++/106937 gcc/c-family/ChangeLog: * c-pretty-print.cc (pp_c_specifier_qualifier_list): Print only GNU attributes here. (c_pretty_printer::direct_abstract_declarator): Print the standard [[]] attributes here. (pp_c_attributes): Remove. (pp_c_attributes_display): Print the [[]] form if appropriate. Use get_attribute_name. Don't print a trailing space when printing the [[]] form. * c-pretty-print.h (pp_c_attributes): Remove. gcc/cp/ChangeLog: * error.cc: Include "attribs.h". (dump_type_prefix): Print only GNU attributes here. (dump_type_suffix): Print standard attributes here. gcc/testsuite/ChangeLog: * c-c++-common/pointer-to-fn1.c: New test.
2022-10-10Don't ICE running selftests if errors were raised [PR99723]Andrea Corallo1-1/+1
Hi all this is to address PR 99723. In the PR GCC crashes as the initialization of common trees is not performed as no compilation is happening, this is because we raise an error earlier while processing the arch flags. This patch changes the code to execute selftests only if no errors where raised before. Bootstrapped on aarch64, okay for trunk? Best Regards Andrea 2022-09-27 Andrea Corallo <andrea.corallo@arm.com> PR other/99723 * toplev.cc (toplev::main): Don't run self tests in case of previous error.
2022-10-10RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h ↵Kito Cheng1-0/+11
from C library For RISC-V linux/glibc toolchain will got header file not found when including stdint.h if multilib is not enabled, it because some header file will try to include gnu/stubs-<ABI-NAME>.h from the system, however it only generated when multilib enabled. In order to prevent that, we introduce a wrapper for riscv_vector.h, include stdint-gcc.h rather than the default stdint.h. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/riscv_vector.h: New. Reported-by: Christoph Müllner <christoph.muellner@vrull.eu> Tested-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
2022-10-10RISC-V: Adjust testcase for rvv/base/user-1.cKito Cheng1-1/+1
The -march option check isn't precise enough, -march=rv*v* also mach any zve extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/user-1.c: Add dg-options and drop dg-skip-if. Reported-by: Christoph Müllner <christoph.muellner@vrull.eu> Tested-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
2022-10-10RISC-V: Add newline to the end of file [NFC]Kito Cheng12-12/+12
gcc/ChangeLog: * config/riscv/riscv-c.cc: Add newline to the end of file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pragma-1.c: Add newline to the end of file. * gcc.target/riscv/rvv/base/pragma-2.c: Ditto. * gcc.target/riscv/rvv/base/pragma-3.c: Ditto. * gcc.target/riscv/rvv/base/user-1.c: Ditto. * gcc.target/riscv/rvv/base/user-2.c: Ditto. * gcc.target/riscv/rvv/base/user-3.c: Ditto. * gcc.target/riscv/rvv/base/user-4.c: Ditto. * gcc.target/riscv/rvv/base/user-5.c: Ditto. * gcc.target/riscv/rvv/base/user-6.c: Ditto. * gcc.target/riscv/rvv/base/vread_csr.c: Ditto. * gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
2022-10-10Make range-op-float entries public.Aldy Hernandez1-9/+7
gcc/ChangeLog: * range-op-float.cc (class foperator_identity): Make members public. (class foperator_equal): Same. (class foperator_not_equal): Same. (class foperator_lt): Same. (class foperator_le): Same. (class foperator_gt): Same. (class foperator_ge): Same. (class foperator_unordered): Same. (class foperator_ordered): Same.
2022-10-10Add frange::maybe_isnan (bool sign).Aldy Hernandez1-0/+13
It is useful to know if there's the possiblity of a NAN with a given sign. This is to complement maybe_isnan(void) which returns TRUE for a NAN of any sign. A follow-up patch implementing ABS will make use of this. gcc/ChangeLog: * value-range.h (frange::maybe_isnan): New.
2022-10-10The true side of x != x should set NAN.Aldy Hernandez1-2/+5
gcc/ChangeLog: * range-op-float.cc (foperator_not_equal::op1_range): Set NAN on TRUE side for x != x.
2022-10-10x UNORD x should set NAN on the TRUE side (and !NAN on the FALSE side).Aldy Hernandez1-3/+7
gcc/ChangeLog: * range-op-float.cc (foperator_unordered::op1_range): Set NAN when operands are equal and result is TRUE.
2022-10-10Return non-legacy ranges in range.h.Aldy Hernandez1-3/+3
int_range<1> is a legacy range (think anti ranges, legacy VRP, etc). There is a penalty for converting anything built with <1> to non-legacy. Since most of the uses of these functions are now ranger, we can save a miniscule amount of time by converting them to non-legacy. gcc/ChangeLog: * range.h (range_true): Return int_range<2>. (range_false): Same. (range_true_and_false): Same.
2022-10-10Require fgraphite effective target for pr107153.c test [PR107153]Jakub Jelinek1-1/+1
The test uses -floop-parallelize-all which emits a sorry when graphite isn't configured in. 2022-10-10 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/107153 * gcc.dg/autopar/pr107153.c: Require fgraphite effective target.
2022-10-10Add op1_range for __builtin_signbit.Aldy Hernandez2-0/+35
This is the op1_range range-op entry for __builtin_signbit. It allows us to wind back through a call to signbit. For example, on the true side of if (__builtin_signbit(x_5) != 0) we can crop down the range of x_5 to: [frange] float [-Inf, -0.0 (-0x0.0p+0)] -NAN Similarly on the false side, we can crop to: [frange] float [0.0 (0x0.0p+0), +Inf] +NAN Tested on x86-64 Linux. gcc/ChangeLog: * gimple-range-op.cc: Add op1_range entry for __builtin_signbit. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/vrp-float-signbit-3.c: New test.
2022-10-10Fix unrecognizable insn of cvtss2si.liuhongt2-2/+10
Adjust lrintmn2 operand preidcates according to real instructions. gcc/ChangeLog: PR target/107185 * config/i386/i386.md (lrint<MODEF:mode><SWI48:mode>2): Swap predicate of operands[0] and operands[1]. gcc/testsuite/ChangeLog: * gcc.target/i386/pr107185.c: New test.
2022-10-10openmp, fortran: Fix up IFN_ASSUME callJakub Jelinek1-2/+5
Like in other spots in trans-openmp.cc that create a TARGET_EXPR, the slot has to be created with create_tmp_var_raw, because gfc_create_var adds the var to BLOCK_VARS and that ICEs during expansion because gimple_add_tmp_var_fn has: gcc_assert (!DECL_CHAIN (tmp) && !DECL_SEEN_IN_BIND_EXPR_P (tmp)); assertion. Also, both C/C++ ensure the argument to IFN_ASSUME has boolean_type_node, it is easier if Fortran does that too. 2022-10-10 Jakub Jelinek <jakub@redhat.com> * trans-openmp.cc (gfc_trans_omp_assume): Use create_tmp_var_raw instead of gfc_create_var for TARGET_EXPR slot creation. Create it with boolean_type_node and convert.
2022-10-10arc: Remove obsolete mRcq and mRcw options.Claudiu Zissulescu3-12/+8
gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove Rcq and Rcw options. * config/arc/arc.opt (mRcq): Ignore option, preserve it for backwards compatibility. (mRcw): Likewise. * doc/invoke.texi (mRcw, mRcq): Update document. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-10-10arc: Remove Rcq constraint.Claudiu Zissulescu3-116/+104
gcc/ * config/arc/arc.cc (arc_check_short_reg_p): New function. (arc_address_cost): Replace satisfies_constraint_Rcq with the above new function. (arc_output_addsi): Likewise. (split_addsi): Likewise. (split_subsi): Likewise. * config/arc/arc.md (movqi_insn): Remove Rcq constraint. (movhi_insn): Likewise. (movsi_insn): Likewise. (tst_movb): Likewise. (tst): Likewise. (tst_bitfield): Likewise. (abssi2): Likewise. (addsi3_mixed): Likewise. (mulhisi3_reg): Likewise. (umulhisi3_reg): Likewise. (mulsi_600): Likewise. (mul64): Likewise. (subsi3_insn): Likewise. (bicsi3_insn): Likewise. (xorsi3): Likewise. (negsi2): Likewise. (one_cmplsi2): Likewise. (lshrsi3_insn): Likewise. (cmpsi_cc_insn_mixed): Likewise. (cmpsi_cc_zn_insn): Likewise. (btst): Likewise. (cmpsi_cc_z_insn): Likewise. (cmpsi_cc_c_insn): Likewise. (indirect_jump): Likewise. (casesi_jump): Likewise. (call_i): Likewise. (call_value_i): Likewise. (bbit): Likewise. (abssf2): Likewise. (ashlsi2_cnt1): Likewise. (lshrsi3_cnt1): Likewise. (ashrsi3_cnt1): Likewise. * config/arc/constraints.md (Rcq): Remove. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-10-10arc: Remove Rcw constraintClaudiu Zissulescu2-124/+110
gcc/Changelog: * config/arc/arc.md (smaxsi3): Remove Rcw. (sminsi3): Likewise. (addsi3_mixed): Likewise. (add_f_2): Likewise. (subsi3_insn): Likewise. (sub_f): Likewise. (sub_n): Likewise. (bset): Likewise. (bxor): Likewise. (bclr): Likewise. (bset_insn): Likewise. (bxor_insn): Likewise. (bclr_insn): Likewise. (bmsk_insn): Likewise. (bicsi3_insn): Likewise. (xorsi3): Likewise. (negsi2): Likewise. (lshrsi3_insn): Likewise. (abssf2): Likewise. (negsf2): Likewise. * config/arc/constraints.md(Rcw): Remove it. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-10-10arc: Remove Rcr constraintClaudiu Zissulescu3-29/+19
gcc/ChangeLog: * config/arc/arc.md(mulsi3_700): Remove Rcr. (mulsi3_highpart): Likewise. (umulsi3_highpart_i): Likewise. (umulsi3_highpart_int): Likewise. (macd): Likewise. (macdu): Likewise. * config/arc/constraints.md (Rcr): Remove it. gcc/testsuite/ChangeLog: * gcc.target/arc/tmac-2.c: Update test. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-10-10arc: Use negative enter pattern instruction's offsetsClaudiu Zissulescu2-3/+31
The enter pattern instruction contains the necessary information for the dwarf machinery to generate the appropriate dwarf code. This patch is fixing the register offsets related to CFA, and adds a test. gcc/ * config/arc/arc.cc (arc_save_callee_enter): Use negative offsets. gcc/testsuite * gcc.target/arc/enter-dw2-1.c: New file. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-10-10Daily bump.GCC Administrator3-1/+37
2022-10-09pru: Add cbranchdi4 patternDimitar Dimitrov7-0/+388
Manually expanding into 32-bit comparisons is much more efficient than the default expansion into word-size comparisons. Note that word for PRU is 8-bit. PR target/106562 gcc/ChangeLog: * config/pru/pru-protos.h (pru_noteq_condition): New function declaration. * config/pru/pru.cc (pru_noteq_condition): New function. * config/pru/pru.md (cbranchdi4): Define new pattern. gcc/testsuite/ChangeLog: * gcc.target/pru/pr106562-1.c: New test. * gcc.target/pru/pr106562-2.c: New test. * gcc.target/pru/pr106562-3.c: New test. * gcc.target/pru/pr106562-4.c: New test. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2022-10-09pru: Optimize DI shiftsDimitar Dimitrov3-0/+302
If the number of shift positions is a constant, then the DI shift operation is expanded to a sequence of 2 to 4 machine instructions. That is more efficient than the default action to call libgcc. gcc/ChangeLog: * config/pru/pru.md (lshrdi3): New expand pattern. (ashldi3): Ditto. gcc/testsuite/ChangeLog: * gcc.target/pru/ashiftdi-1.c: New test. * gcc.target/pru/lshiftrtdi-1.c: New test. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2022-10-09MIPS: improve -march=native arch detectionYunQiang Su5-7/+38
If we cannot get info from options and cpuinfo, we try to get from: 1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7 2. _MIPS_ARCH from host compiler. mnan=2008 option is also used if __mips_nan2008__ is used. This can fix the wrong loader usage on r5/r6 platform with -march=native. gcc/ChangeLog: * config.gcc: set with_arch to default_mips_arch if no defined. * config/mips/driver-native.cc (host_detect_local_cpu): try getauxval(AT_BASE_PLATFORM) and _MIPS_ARCH, too. pass -mnan=2008 if __mips_nan2008__ is defined. * config.in: define HAVE_SYS_AUXV_H and HAVE_GETAUXVAL. * configure.ac: detect sys/auxv.h and getauxval. * configure: regenerated.
2022-10-09Daily bump.GCC Administrator4-1/+55
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