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2021-05-03[Ada] Error message on invalid prefixed procedure callEd Schonberg1-0/+10
gcc/ada/ * sem_ch4.adb (Try_Object_Operation): When a prefixed call is overloaded and illegal, and the All_Errors flag is off, generate an error message if the re-analysis of some candidate interpretation fails to produce one.
2021-05-03[Ada] Rename package instead of each routineDmitriy Anisimkov2-41/+5
gcc/ada/ * libgnat/g-casuti.adb: Replace with "pragma No_Body". * libgnat/g-casuti.ads: Replace with a package renaming.
2021-05-03[Ada] Fix attributes Version and Body_Version for concurrent unitsPiotr Trojanek1-9/+8
gcc/ada/ * sem_attr.adb (Check_Program_Unit): Fix references to Concurrent_Kind and Is_Concurrent_Type; avoid repeated calls to Entity.
2021-05-03[Ada] Allow attributes Version and Body_Version prefixed by entriesPiotr Trojanek1-10/+6
gcc/ada/ * sem_attr.adb (Check_Program_Unit): Replace tests for Task_Kind and Protected_Kind with a collective test for Concurrent_Kind; likewise, replace calls to Is_Task_Type and Is_Protected_Type with a collective call to Is_Concurrent_Type; simplify into a single membership test; add missing Entry_Kind alternative.
2021-05-03[Ada] Fix typos in calls to Error_Msg_NEPiotr Trojanek3-3/+3
gcc/ada/ * sem_aggr.adb (Resolve_Record_Aggregate): Fix casing in error message. * sem_ch3.adb (Add_Internal_Interface_Entities): Fix unbalanced parens. * sem_elim.adb (Eliminate_Error_Msg): Add insertion character.
2021-05-03[Ada] Fix calls to Error_Msg_NE instead of Error_Msg_NPiotr Trojanek5-18/+16
gcc/ada/ * freeze.adb (Freeze_Profile): Replace Error_Msg_NE with Error_Msg_N; change to continuation message. * sem_cat.adb, sem_ch10.adb, sem_ch12.adb, sem_ch5.adb: Replace calls to Error_Msg_NE with calls to Error_Msg_N.
2021-05-03[Ada] Remove leading and trailing spaces in error messagesPiotr Trojanek13-27/+27
gcc/ada/ * exp_disp.adb, sem_aggr.adb, sem_cat.adb, sem_ch10.adb, sem_ch12.adb, sem_ch3.adb, sem_ch4.adb, sem_ch5.adb, sem_ch6.adb, sem_ch8.adb, sem_ch9.adb, sem_prag.adb, sem_res.adb: Remove extra leading and trailing space in error messages.
2021-05-03[Ada] Remove confusing warning on type exportArnaud Charlet1-4/+0
gcc/ada/ * sem_prag.adb (Set_Exported): Do not warn on exporting a type.
2021-05-03[Ada] Spurious warning about premature use of selected componentEd Schonberg1-0/+11
gcc/ada/ * sem_warn.adb (Check_References): Do not emit warning on a selected component when enclosing type has no discriminant and type of component has partial initialization.
2021-05-03[Ada] Expansion in _postconditions confusing CodePeerJustin Squirek4-38/+78
gcc/ada/ * contracts.adb (Build_Postconditions_Procedure): Remove internally generated if statement used to control finalization actions. * exp_ch6.adb (Add_Return, Expand_Non_Function_Return, Expand_Simple_Function_Return): Add if statement around _postconditions to control finalization. * exp_ch7.adb (Build_Finalizer): Likewise. * sem_prag.adb (Find_Related_Declaration_Or_Body): Add case to handle Context itself being a handled sequence of statements.
2021-05-03[Ada] Spurious accessibility error on call in return statementJustin Squirek1-0/+11
gcc/ada/ * sem_util.adb (In_Return_Value): Modified to detect when implicit dereference is specified on the return type of a function call within the expression being checked.
2021-05-03[Ada] Crash on aggregate in function call in object declarationEd Schonberg1-2/+6
gcc/ada/ * exp_aggr.adb (Expand_Array_Aggregate): If the parent node of the aggregate is a subprogram call there is no target in which to build the aggregate, and it has to be expanded into component assignments.
2021-05-03[Ada] Code and style cleanups for CUDAPiotr Trojanek3-43/+42
gcc/ada/ * exp_prag.adb (Expand_Pragma_CUDA_Execute): Refill comments; remove periods after single-line comments; use procedural variant of Next_Entity. * gnat_cuda.adb: Refill comments; remove periods after single-line comments; replace calls to UI_From_Int with constants; change iteration bounds so they match the comments. * sem_prag.adb (Analyze_Pragma): Add checks for malformed pragma CUDA_Kernel aggregate; simplify processing of pragma CUDA_Global with Check_Arg_Count; sync comment with code for CUDA_Global.
2021-05-03[Ada] No_Implicit_Loops restriction and pragma AssertArnaud Charlet1-7/+36
gcc/ada/ * tbuild.adb (Make_Implicit_Loop_Statement): Disable restriction checking on dead paths.
2021-05-03[Ada] Spurious warning on postcondition and resultArnaud Charlet1-28/+2
gcc/ada/ * sem_util.adb (Check_Result_And_Post_State): Replace custom Has_In_Out_Parameter with existing Has_Out_Or_In_Out_Parameter flag which corresponds exactly to what we need.
2021-05-03[Ada] Code cleanupArnaud Charlet1-2/+0
gcc/ada/ * libgnat/a-ztcoio.adb: Remove unused with clause.
2021-05-03[Ada] Cleanup processing of aspect Dynamic_PredicatePiotr Trojanek1-15/+7
gcc/ada/ * sem_ch13.adb (Build_Predicate_Functions): Fix typo in comment. (Resolve_Aspect_Expressions): Fix typo in comment; remove redundant check for no aspects; simplify with Discard_Node.
2021-05-03[Ada] Compiler aborts on a constrained subtype of a predicated typeEd Schonberg2-9/+13
gcc/ada/ * sem_util.adb (Build_Constrained_Itype): Remove prior patch, issue is better handled in Sem_Ch13.Build_Predicate_Functions. * sem_ch13.adb (Build_Predicate_Functions): Do not build predicate function for an Itype with a defined Predicated_Parent, even if that designated parent does not yet have a Predicate_Function. This can happen in instance bodies nested within a generic unit.
2021-05-03Daily bump.GCC Administrator3-1/+51
2021-05-02aix: Redesign section encoding and selectionDavid Edelsohn9-110/+133
AIX symbol references can refer to either the symbol (a label) or a symbol with a qualifier (the storage mapping class). The storage mapping class provide information about the underlying COFF section into which the symbol will be placed, e.g. [RO] for read-only in the text section, [RW] for read-writer in the data section, or [BS] for the BSS section. A label is distinct from a qualname in the assembler language, e.g., foo and foo[RW] are different, but the symbol table of an object file strips the storage mapping class from the name, so that it no longer is relevant when referring to symbols across object files and libraries. .csect .data[RW] i: is a label "i" in the .data CSECT, which has storage mapping class [RW] so that it is placed in the read-write COFF section. .csect i[RW] is a CSECT "i[RW]". BSS does not allow interior labels. The AIX port of GCC had been emitting the storage mapping class where appropriate but not consistently using the storage mapping class on the DECL or SYM name. This patch updates the section encoding to properly place storage mapping class on symbol names and remove the decorations placed when emitting the symbol. The mapping classes correspond to sections and the encoding choices must exactly match the section choices made by get_section, so the logic for the computation of reloc in get_variable_section is split into its own function that XCOFF encode section info can call. gcc/ChangeLog: * varasm.c (compute_reloc_for_var): Split out from... (get_variable_section): Use it. * output.h (compute_reloc_for_var): Declare. * config/rs6000/rs6000-protos.h (rs6000_xcoff_asm_output_aligned_decl_common): Change alignment to unsigned int. * config/rs6000/rs6000.c (rs6000_legitimize_tls_address_aix): Don't append storage mapping class to symbol. (rs6000_xcoff_asm_named_section): Add BS and UL mapping classes. Don't convert TLS BSS to common. (rs6000_xcoff_unique_section): Don't fall back to select_secton. (rs6000_xcoff_section_type_flags): Add SECTION_BSS if DECL is bss_initializer. (rs6000_xcoff_asm_globalize_decl_name): Don't strip storage mapping class. (rs6000_xcoff_asm_output_aligned_decl_common): Align is unsigned int. If align is 0 from TLS class, use the same rules as varasm.c If not common, switch to BSS section manually. If common, emit appropriate comm or lcomm directive. (rs6000_xcoff_encode_section_info): Add logic to append all storage mapping classes. (rs6000_asm_weaken_decl): Adjust for qualname symbols. * config/rs6000/xcoff.h (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Use rs6000_xcoff_asm_output_aligned_decl_common. (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Use rs6000_xcoff_asm_output_aligned_decl_common. (ASM_OUTPUT_TLS_COMMON): Use rs6000_xcoff_asm_output_aligned_decl_common. gcc/testsuite/ChangeLog: * g++.dg/ext/visibility/fvisibility-inlines-hidden-4.C: Expect [BS] mapping class on AIX. * gcc.c-torture/compile/pr61159.c: XFAIL on AIX. * gcc.c-torture/execute/alias-2.c: Same. * gcc.dg/alias-7.c: Same.
2021-05-02nvptx: Fix up nvptx build against latest libstdc++ [PR100375]Jakub Jelinek1-5/+5
The r12-220-gd96db15967e78d7cecea3b1cf3169ceb924678ac change deprecated some non-standard std::pair constructors and that apparently broke nvptx.c build, where pseudo_node_t is std::pair<struct basic_block_def *, int> and so nullptr (or NULL) needs to be used for the first argument of the ctors instead of 0. 2021-05-02 Jakub Jelinek <jakub@redhat.com> PR target/100375 * config/nvptx/nvptx.c (nvptx_sese_pseudo): Use nullptr instead of 0 as first argument of pseudo_node_t constructors.
2021-05-02i386: Fix up plugin header install on x86 [PR100336]Jakub Jelinek1-1/+2
The recent addition of i386-isa.def which is included from i386.h results in failures to build gcc plugins, the i386.h header is installed, but i386-isa.def is not. 2021-05-02 Jakub Jelinek <jakub@redhat.com> PR target/100336 * config/i386/t-i386 (TM_H): Add $(srcdir)/config/i386/i386-isa.def.
2021-05-02Daily bump.GCC Administrator3-1/+26
2021-05-01c++: C++11 range-for and ovl/lkp_iteratorJason Merrill3-47/+55
We can't use C++11 range-based 'for' over a tree directly, because we don't know what kind of range we want to use it as. I suppose in some cases we could guess, but it seems better to tersely make it explicit. This patch adds range adaptors ovl_range and lkp_range for use as the range of a range-for, e.g. for (tree fn : lkp_range (fns)) { ... } This patch also removes the private copy ops from ovl_iterator; it's necessary for range-for, and these are effectively C++ forward_iterators, which allow copying, so I don't see a reason to prevent it. A bit more would need to be done to make them actually conform as C++11 forward iterators, but I don't think we particularly want to #include <iterator> yet. gcc/cp/ChangeLog: * cp-tree.h (class ovl_iterator): Allow copying. Add op==. (class ovl_range, class lkp_range): New. * call.c (build_op_call_1, add_candidates): Use them. (build_op_delete_call, has_trivial_copy_assign_p): Likewise. (has_trivial_copy_p): Likewise. * class.c (handle_using_decl, get_basefndecls): Likewise. (maybe_warn_about_overly_private_class): Likewise. (warn_hidden, add_implicitly_declared_members): Likewise. (check_methods, clone_constructors_and_destructors): Likewise. (type_has_user_nondefault_constructor): Likewise.
2021-05-01Add GTY support for irange.Aldy Hernandez2-42/+56
Right now we have GTY support for static storage iranges (int_range<>). However, there's no reason why the base class can't be used with GC, other than it was an oversight. For that matter, the base class has a pointer to the sub-range storage, so we can use the same implementation for both. This patch does so. I have also removed the DEFINE_INT_RANGE_GC_STUBS stuff, and have documented why we need a separate gt_pch_nx (int_range<1> *&) version. This has to do with hash-traits.h, which ipa-prop.c is using to store a value_range. The header file hash-traits.h is defining an extern of gt_pch_nx (int_range<1> *&) etc, instead of calling the more generic (int_range<1> *) which is already available. It seems suspect that has-traits.h has their own externs for GC functions, and if someone has a better solution, I'd be glad to hear it. gcc/ChangeLog: * value-range.cc (DEFINE_INT_RANGE_GC_STUBS): Remove. (gt_pch_nx (int_range<1> *&)): New. (gt_ggc_mx (int_range<1> *&)): New. * value-range.h (class irange): Add GTY support for the base class.
2021-04-30doc/options.texi: Fix the description of 'Negative'.Geng Qi1-2/+2
gcc/ChangeLog: * doc/options.texi (Negative): Change either or to both and.
2021-05-01Daily bump.GCC Administrator3-1/+308
2021-04-30testsuite: aarch64: Add fusion tests for FP vml[as] intrinsicsJonathan Wright2-0/+134
Add compilation tests to make sure that the output of vmla/vmls floating-point Neon intrinsics (fmul, fadd/fsub) is not fused into fmla/fmls instructions. gcc/testsuite/ChangeLog: 2021-02-16 Jonathan Wright <jonathan.wright@arm.com> * gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c: New test.
2021-04-30aarch64: Use RTL builtins for FP ml[as][q]_laneq intrinsicsJonathan Wright3-4/+62
Rewrite floating-point vml[as][q]_laneq Neon intrinsics to use RTL builtins rather than relying on the GCC vector extensions. Using RTL builtins allows control over the emission of fmla/fmls instructions (which we don't want here.) With this commit, the code generated by these intrinsics changes from a fused multiply-add/subtract instruction to an fmul followed by an fadd/fsub instruction. If the programmer really wants fmla/fmls instructions, they can use the vfm[as] intrinsics. gcc/ChangeLog: 2021-02-17 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add float_ml[as][q]_laneq builtin generator macros. * config/aarch64/aarch64-simd.md (mul_laneq<mode>3): Define. (aarch64_float_mla_laneq<mode>): Define. (aarch64_float_mls_laneq<mode>): Define. * config/aarch64/arm_neon.h (vmla_laneq_f32): Use RTL builtin instead of GCC vector extensions. (vmlaq_laneq_f32): Likewise. (vmls_laneq_f32): Likewise. (vmlsq_laneq_f32): Likewise.
2021-04-30aarch64: Use RTL builtins for FP ml[as][q]_lane intrinsicsJonathan Wright3-13/+55
Rewrite floating-point vml[as][q]_lane Neon intrinsics to use RTL builtins rather than relying on the GCC vector extensions. Using RTL builtins allows control over the emission of fmla/fmls instructions (which we don't want here.) With this commit, the code generated by these intrinsics changes from a fused multiply-add/subtract instruction to an fmul followed by an fadd/fsub instruction. If the programmer really wants fmla/fmls instructions, they can use the vfm[as] intrinsics. gcc/ChangeLog: 2021-02-16 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add float_ml[as]_lane builtin generator macros. * config/aarch64/aarch64-simd.md (*aarch64_mul3_elt<mode>): Rename to... (mul_lane<mode>3): This, and re-order arguments. (aarch64_float_mla_lane<mode>): Define. (aarch64_float_mls_lane<mode>): Define. * config/aarch64/arm_neon.h (vmla_lane_f32): Use RTL builtin instead of GCC vector extensions. (vmlaq_lane_f32): Likewise. (vmls_lane_f32): Likewise. (vmlsq_lane_f32): Likewise.
2021-04-30aarch64: Use RTL builtins for FP ml[as] intrinsicsJonathan Wright4-8/+43
Rewrite floating-point vml[as][q] Neon intrinsics to use RTL builtins rather than relying on the GCC vector extensions. Using RTL builtins allows control over the emission of fmla/fmls instructions (which we don't want here.) With this commit, the code generated by these intrinsics changes from a fused multiply-add/subtract instruction to an fmul followed by an fadd/fsub instruction. If the programmer really wants fmla/fmls instructions, they can use the vfm[as] intrinsics. gcc/ChangeLog: 2021-02-16 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add float_ml[as] builtin generator macros. * config/aarch64/aarch64-simd.md (aarch64_float_mla<mode>): Define. (aarch64_float_mls<mode>): Define. * config/aarch64/arm_neon.h (vmla_f32): Use RTL builtin instead of relying on GCC vector extensions. (vmla_f64): Likewise. (vmlaq_f32): Likewise. (vmlaq_f64): Likewise. (vmls_f32): Likewise. (vmls_f64): Likewise. (vmlsq_f32): Likewise. (vmlsq_f64): Likewise. * config/aarch64/iterators.md: Define VDQF_DF mode iterator.
2021-04-30aarch64: Use RTL builtins for FP ml[as]_n intrinsicsJonathan Wright3-34/+47
Rewrite floating-point vml[as][q]_n Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-01-18 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add float_ml[as]_n_builtin generator macros. * config/aarch64/aarch64-simd.md (*aarch64_mul3_elt_from_dup<mode>): Rename to... (mul_n<mode>3): This, and re-order arguments. (aarch64_float_mla_n<mode>): Define. (aarch64_float_mls_n<mode>): Define. * config/aarch64/arm_neon.h (vmla_n_f32): Use RTL builtin instead of inline asm. (vmlaq_n_f32): Likewise. (vmls_n_f32): Likewise. (vmlsq_n_f32): Likewise.
2021-04-30aarch64: Use RTL builtins for vmull[_high]_p8 intrinsicsJonathan Wright3-12/+44
Rewrite vmull[_high]_p8 Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-02-05 Jonathan Wright <joanthan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add pmull[2] builtin generator macros. * config/aarch64/aarch64-simd.md (aarch64_pmullv8qi): Define. (aarch64_pmull_hiv16qi_insn): Define. (aarch64_pmull_hiv16qi): Define. * config/aarch64/arm_neon.h (vmull_high_p8): Use RTL builtin instead of inline asm. (vmull_p8): Likewise.
2021-04-30AVR cc0 conversion - adjust peepholesSenthil Kumar Selvaraj1-216/+308
This patch adjusts peepholes to match and generate parallels with a clobber of REG_CC. It also sets mov<mode>_insn as the name of the pattern for the split insn (rather than the define_insn_and_split), so that avr_2word_insn_p, which looks for CODE_FOR_mov<mode>_insn, works correctly. This is required for the *cpse.eq peephole to fire, and also helps generate better code for avr_out_sbxx_branch. gcc/ChangeLog: * config/avr/avr.md: Adjust peepholes to match and generate parallels with clobber of REG_CC. (mov<mode>_insn): Rename to mov<mode>_insn_split. (*mov<mode>_insn): Rename to mov<mode>_insn.
2021-04-30middle-end: Disable section anchors for VAR_DECLs if -fdata-sectionsDavid Edelsohn1-0/+6
-fdata-sections places data symbols into their own, unique, named sections. -fsection-anchors create an anchor to access neighboring symbols within a section. When both are enabled, a separate section anchor is created for each symbol, which provides no benefit. This patch updates the common gating function use_blocks_for_decl_p() to return false if -fdata-sections is enabled. gcc/ChangeLog: * varasm.c (use_blocks_for_decl_p): Don't use section anchors for VAR_DECLs if -fdata-sections enabled.
2021-04-30Define target hook to emit KFmode constants for libgcc.Michael Meissner1-0/+29
This patch defines a target hook so that the KFmode constants (__LIBGCC_KF_MAX__, __LIBGCC_KF_MIN__, and __LIBGCC_KF_EPSILON__) needed to build _divkc3.c in libgcc are defined. The need for these constants were added in the April 28th changes to libgcc that added complex division optimizations. We only define the KFmode constants if IEEE 128-bit floating point is supported, but long double does not use the IEEE 128-bit format. If long double uses the IEEE 128-bit format, it will use TFmode and not KFmode. gcc/ 2021-04-30 Michael Meissner <meissner@linux.ibm.com> PR bootstrap/100327 * config/rs6000/rs6000.c (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define. (rs6000_libgcc_floating_mode_supported_p): New target hook.
2021-04-30Refactor backward threader registry and profitability code into classes.Aldy Hernandez1-154/+213
This refactors the registry and the profitability code from the backwards threader into two separate classes. It cleans up the code, and makes it easier for alternate implementations to share code. gcc/ChangeLog: * tree-ssa-threadbackward.c (class thread_jumps): Split out code from here... (class back_threader_registry): ...to here... (class back_threader_profitability): ...and here... (thread_jumps::thread_through_all_blocks): Remove argument. (back_threader_registry::back_threader_registry): New. (back_threader_registry::~back_threader_registry): New. (back_threader_registry::thread_through_all_blocks): New. (thread_jumps::profitable_jump_thread_path): Move from here... (back_threader_profitability::profitable_path_p): ...to here. (thread_jumps::find_taken_edge): New. (thread_jumps::convert_and_register_current_path): Move... (back_threader_registry::register_path): ...to here. (thread_jumps::register_jump_thread_path_if_profitable): Move... (thread_jumps::maybe_register_path): ...to here. (thread_jumps::handle_phi): Call find_taken_edge and maybe_register_path. (thread_jumps::handle_assignment): Same. (thread_jumps::fsm_find_control_statement_thread_paths): Remove tree argument to handle_phi and handle_assignment. (thread_jumps::find_jump_threads_backwards): Set m_name. Remove set of m_speed_p and m_max_threaded_paths. (pass_thread_jumps::execute): Remove second argument from find_jump_threads_backwards. (pass_early_thread_jumps::execute): Same.
2021-04-30Jump threader refactor.Aldy Hernandez7-610/+648
This is an overall refactor of the jump threader, both for the low level bits in tree-ssa-threadupdate.* and the high level bits in tree-ssa-threadedge.*. There should be no functional changes. Some of the benefits of the refactor are: a) Eliminates some icky global state (for example the x_vr_values hack). b) Provides some semblance of an API for the threader. c) Makes it clearer to see what parts are from the high level threader, and what parts belong in the low level path registry and BB threading mechanism. d) Avoids passing a ton of variables around. e) Provides for easier sharing with the backward threader. f) Merged simplify stmt code in VRP and DOM as they were nearly identical. This has been bootstrapped and regression tested on x86-64 Linux. Jeff had also been testing this path as part of his Fedora throughout the off-season. gcc/ChangeLog: * tree-ssa-dom.c (class dom_jump_threader_simplifier): New. (class dom_opt_dom_walker): Initialize some class variables. (pass_dominator::execute): Pass evrp_range_analyzer and dom_jump_threader_simplifier to dom_opt_dom_walker. Adjust for some functions moving into classes. (simplify_stmt_for_jump_threading): Adjust and move to... (jump_threader_simplifier::simplify): ...here. (dom_opt_dom_walker::before_dom_children): Adjust for m_evrp_range_analyzer. (dom_opt_dom_walker::after_dom_children): Remove x_vr_values hack. (test_for_singularity): Place in dom_opt_dom_walker class. (dom_opt_dom_walker::optimize_stmt): The argument evrp_range_analyzer is now a class field. * tree-ssa-threadbackward.c (class thread_jumps): Add m_registry. (thread_jumps::thread_through_all_blocks): New. (thread_jumps::convert_and_register_current_path): Use m_registry. (pass_thread_jumps::execute): Adjust for thread_through_all_blocks being in the threader class. (pass_early_thread_jumps::execute): Same. * tree-ssa-threadedge.c (threadedge_initialize_values): Move... (jump_threader::jump_threader): ...here. (threadedge_finalize_values): Move... (jump_threader::~jump_threader): ...here. (jump_threader::remove_jump_threads_including): New. (jump_threader::thread_through_all_blocks): New. (record_temporary_equivalences_from_phis): Move... (jump_threader::record_temporary_equivalences_from_phis): ...here. (record_temporary_equivalences_from_stmts_at_dest): Move... (jump_threader::record_temporary_equivalences_from_stmts_at_dest): Here... (simplify_control_stmt_condition_1): Move to jump_threader class. (simplify_control_stmt_condition): Move... (jump_threader::simplify_control_stmt_condition): ...here. (thread_around_empty_blocks): Move... (jump_threader::thread_around_empty_blocks): ...here. (thread_through_normal_block): Move... (jump_threader::thread_through_normal_block): ...here. (thread_across_edge): Move... (jump_threader::thread_across_edge): ...here. (thread_outgoing_edges): Move... (jump_threader::thread_outgoing_edges): ...here. * tree-ssa-threadedge.h: Move externally facing functings... (class jump_threader): ...here... (class jump_threader_simplifier): ...and here. * tree-ssa-threadupdate.c (struct redirection_data): Remove comment. (jump_thread_path_allocator::jump_thread_path_allocator): New. (jump_thread_path_allocator::~jump_thread_path_allocator): New. (jump_thread_path_allocator::allocate_thread_edge): New. (jump_thread_path_allocator::allocate_thread_path): New. (jump_thread_path_registry::jump_thread_path_registry): New. (jump_thread_path_registry::~jump_thread_path_registry): New. (jump_thread_path_registry::allocate_thread_edge): New. (jump_thread_path_registry::allocate_thread_path): New. (dump_jump_thread_path): Make extern. (debug (const vec<jump_thread_edge *> &path)): New. (struct removed_edges): Move to tree-ssa-threadupdate.h. (struct thread_stats_d): Remove. (remove_ctrl_stmt_and_useless_edges): Make static. (lookup_redirection_data): Move... (jump_thread_path_registry::lookup_redirection_data): ...here. (ssa_redirect_edges): Make static. (thread_block_1): Move... (jump_thread_path_registry::thread_block_1): ...here. (thread_block): Move... (jump_thread_path_registry::thread_block): ...here. (thread_through_loop_header): Move... (jump_thread_path_registry::thread_through_loop_header): ...here. (mark_threaded_blocks): Move... (jump_thread_path_registry::mark_threaded_blocks): ...here. (debug_path): Move... (jump_thread_path_registry::debug_path): ...here. (debug_all_paths): Move... (jump_thread_path_registry::dump): ..here. (rewire_first_differing_edge): Move... (jump_thread_path_registry::rewire_first_differing_edge): ...here. (adjust_paths_after_duplication): Move... (jump_thread_path_registry::adjust_paths_after_duplication): ...here. (duplicate_thread_path): Move... (jump_thread_path_registry::duplicate_thread_path): ..here. (remove_jump_threads_including): Move... (jump_thread_path_registry::remove_jump_threads_including): ...here. (thread_through_all_blocks): Move to... (jump_thread_path_registry::thread_through_all_blocks): ...here. (delete_jump_thread_path): Remove. (register_jump_thread): Move... (jump_thread_path_registry::register_jump_thread): ...here. * tree-ssa-threadupdate.h: Move externally facing functions... (class jump_thread_path_allocator): ...here... (class jump_thread_path_registry): ...and here. (thread_through_all_blocks): Remove. (struct removed_edges): New. (register_jump_thread): Remove. (remove_jump_threads_including): Remove. (delete_jump_thread_path): Remove. (remove_ctrl_stmt_and_useless_edges): Remove. (free_dom_edge_info): New prototype. * tree-vrp.c: Remove x_vr_values hack. (class vrp_jump_threader_simplifier): New. (vrp_jump_threader_simplifier::simplify): New. (vrp_jump_threader::vrp_jump_threader): Adjust method signature. Remove m_dummy_cond. Instantiate m_simplifier and m_threader. (vrp_jump_threader::thread_through_all_blocks): New. (vrp_jump_threader::simplify_stmt): Remove. (vrp_jump_threader::after_dom_children): Do not set m_dummy_cond. Remove x_vr_values hack. (execute_vrp): Adjust for thread_through_all_blocks being in a class.
2021-04-30gcc/genflags.c: Improve error messageChristophe Lyon1-2/+2
When an iterator cannot be expanded, it is helpful to see the expanded name which is causing problems. It would be better to also print the current iterator value (which couldn't match), but I couldn't find how. 2021-04-30 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * genflags.c (gen_insn): Print failed expansion string.
2021-04-30c++/98032 - add testcaseRichard Biener1-0/+20
This adds another testcase for PR95719. 2021-04-30 Richard Biener <rguenther@suse.de> PR c++/98032 * g++.dg/pr98032.C: New testcase.
2021-04-30Update alignment_for_piecewise_moveH.J. Lu1-1/+1
alignment_for_piecewise_move is called only with MOVE_MAX_PIECES or STORE_MAX_PIECES, which are the number of bytes at a time that we can move or store efficiently. We should call mode_for_size without limit to MAX_FIXED_MODE_SIZE, which is an integer expression for the size in bits of the largest integer machine mode that should actually be used, may be smaller than MOVE_MAX_PIECES or STORE_MAX_PIECES, which may use vector. * expr.c (alignment_for_piecewise_move): Call mode_for_size without limit to MAX_FIXED_MODE_SIZE.
2021-04-30Don't use nullptr return from simplify_gen_subregH.J. Lu1-1/+3
Check nullptr return from simplify_gen_subreg. Don't use it if it is nullptr. PR middle-end/90773 * builtins.c (builtin_memset_gen_str): Don't use return from simplify_gen_subreg.
2021-04-30tree-optimization/96513 - add testcase for fixed bugRichard Biener1-0/+26
This adds a testcase for a bug that was fixed with the hybrid SLP detection rewrite. 2021-04-30 Richard Biener <rguenther@suse.de> PR tree-optimization/96513 * gcc.dg/torture/pr96513.c: New testcase.
2021-04-30i386: Introduce reversed ADC and SBB patterns [PR98060]Uros Bizjak4-7/+131
The compiler is able to merge LTU comparisons with PLUS or MINUS pattern to form addition with carry (ADC) and subtraction with borrow (SBB) instructions: op = op + carry [ADC $0, op] op = op - carry [SBB $0, op] The patch introduces reversed ADC and SBB insn patterns: op = op + !carry [SBB $-1, op] op = op - !carry [ADC $-1, op] allowing the compiler to also merge GEU comparisons. 2021-04-30 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/98060 * config/i386/i386.md (*add<mode>3_carry_0r): New insn pattern. (*addsi3_carry_zext_0r): Ditto. (*sub<mode>3_carry_0): Ditto. (*subsi3_carry_zext_0r): Ditto. * config/i386/predicates.md (ix86_carry_flag_unset_operator): New predicate. * config/i386/i386.c (ix86_rtx_costs) <case PLUS, case MINUS>: Also consider ix86_carry_flag_unset_operator to calculate the cost of adc/sbb insn. gcc/testsuite/ PR target/98060 * gcc.target/i386/pr98060.c: New test.
2021-04-30modulo-sched: skip loops with strange register defs [PR100225]Roman Zhuykov2-21/+50
PR84878 fix adds an assertion which can fail, e.g. when stack pointer is adjusted inside the loop. We have to prevent it and search earlier for any 'strange' instruction. The solution is to skip the whole loop if using 'note_stores' we found that one of hard registers is in 'df->regular_block_artificial_uses' set. Also patch properly prohibit not single-set instruction in loop body. gcc/ChangeLog: PR rtl-optimization/100225 PR rtl-optimization/84878 * modulo-sched.c (sms_schedule): Use note_stores to skip loops where we have an instruction which touches (writes) any hard register from df->regular_block_artificial_uses set. Allow not-single-set instruction only right before basic block tail. gcc/testsuite/ChangeLog: PR rtl-optimization/100225 PR rtl-optimization/84878 * gcc.dg/pr100225.c: New test. libgomp/ChangeLog: * testsuite/libgomp.oacc-c-c++-common/atomic_capture-3.c: New test.
2021-04-29RISC-V: For '-march' and '-mabi' options, add 'Negative' property mentions ↵Geng Qi1-2/+2
itself. When use multi-lib riscv-tool-chain. A bug is triggered when there are two '-march' at command line. riscv64-unknown-elf-gcc -march=rv32gcp -mabi=ilp32f -march=rv32gcpzp64 HelloWorld.c /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o: ABI is incompatible with that of the selected emulation: target emulation `elf64-littleriscv' does not match `elf32-littleriscv' /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o: ABI is incompatible with that of the selected emulation: target emulation `elf64-littleriscv' does not match `elf32-littleriscv' /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o ...... This patch fix it. And the DRIVER would prune the extra '-march' and '-mabi' options and keep only the last one valid. gcc/ChangeLog: * config/riscv/riscv.opt (march=,mabi=): Negative itself.
2021-04-29RISC-V: Add patterns for builtin overflow.LevyHsu3-0/+257
gcc/ * config/riscv/riscv.c (riscv_min_arithmetic_precision): New. * config/riscv/riscv.h (TARGET_MIN_ARITHMETIC_PRECISION): New. * config/riscv/riscv.md (addv<mode>4, uaddv<mode>4): New. (subv<mode>4, usubv<mode>4, mulv<mode>4, umulv<mode>4): New.
2021-04-30Daily bump.GCC Administrator7-1/+631
2021-04-29merge ix86- and x86_64-*-* in config.gccAlexandre Oliva1-39/+1
Uros observed that i[34567]86-*-* and x86_64-*-* cpu_type-setting target cases were equivalent. I've verified that this was the case, and combined them. for gcc/ChangeLog * config.gcc: Merged x86 and x86_64 cpu_type-setting cases.
2021-04-29add ASM_OUTPUT_MAX_SKIP_ALIGN to i386.hAlexandre Oliva13-165/+11
Several i386 align tests expect p2align to be used, but not all configurations define ASM_OUTPUT_MAX_SKIP_ALIGN, even when HAVE_GAS_MAX_SKIP_P2ALIGN. i386.h had an equivalent ASM_OUTPUT_MAX_SKIP_PAD. I've renamed it and its uses to the documented _ALIGN spelling, and dropped all redundant defines elsewhere in gcc/config/i386/. for gcc/ChangeLog * config/i386/i386.h (ASM_OUTPUT_MAX_SKIP_PAD): Rename to... (ASM_OUTPUT_MAX_SKIP_ALIGN): ... this. Enclose in do/while(0). * config/i386/i386.c: Adjust. * config/i386/i386.md: Adjust. * config/i386/darwin.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Drop. * config/i386/dragonfly.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/freebsd.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/gas.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/gnu-user.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/iamcu.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/lynx.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/netbsd-elf.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/openbsdelf.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. * config/i386/x86-64.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise. (ASM_OUTPUT_MAX_SKIP_PAD): Likewise.
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