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2019-05-16tree-affine.c (expr_to_aff_combination): New function split out from...Richard Biener2-76/+148
2019-05-16 Richard Biener <rguenther@suse.de> * tree-affine.c (expr_to_aff_combination): New function split out from... (tree_to_aff_combination): ... here. (aff_combination_expand): Avoid building a GENERIC tree. From-SVN: r271294
2019-05-16gcc: move assemble_start_function / assemble_end_function to output_mi_thunkMax Filippov32-7/+137
Let backends call assemble_start_function after they have generated thunk function body so that a constant pool could be output if it is required. This may help backends to avoid implementing custom constant loading code specifically for the MI thunk and reuse existing functionality. gcc/ 2019-05-16 Max Filippov <jcmvbkbc@gmail.com> * cgraphunit.c (cgraph_node::expand_thunk): Remove assemble_start_function and assemble_end_function calls. * config/alpha/alpha.c (alpha_output_mi_thunk_osf): Call assemble_start_function and assemble_end_function. * config/arc/arc.c (arc_output_mi_thunk): Likewise. * config/arm/arm.c (arm_output_mi_thunk): Likewise. * config/bfin/bfin.c (bfin_output_mi_thunk): Likewise. * config/c6x/c6x.c (c6x_output_mi_thunk): Likewise. * config/cris/cris.c (cris_asm_output_mi_thunk): Likewise. * config/csky/csky.c (csky_output_mi_thunk): Likewise. * config/epiphany/epiphany.c (epiphany_output_mi_thunk): Likewise. * config/frv/frv.c (frv_asm_output_mi_thunk): Likewise. * config/i386/i386.c (x86_output_mi_thunk): Likewise. * config/ia64/ia64.c (ia64_output_mi_thunk): Likewise. * config/m68k/m68k.c (m68k_output_mi_thunk): Likewise. * config/microblaze/microblaze.c (microblaze_asm_output_mi_thunk): Likewise. * config/mips/mips.c (mips_output_mi_thunk): Likewise. * config/mmix/mmix.c (mmix_asm_output_mi_thunk): Likewise. * config/mn10300/mn10300.c (mn10300_asm_output_mi_thunk): Likewise. * config/nds32/nds32.c (nds32_asm_output_mi_thunk): Likewise. * config/nios2/nios2.c (nios2_asm_output_mi_thunk): Likewise. * config/or1k/or1k.c (or1k_output_mi_thunk): Likewise. * config/pa/pa.c (pa_asm_output_mi_thunk): Likewise. * config/riscv/riscv.c (riscv_output_mi_thunk): Likewise. * config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise. * config/s390/s390.c (s390_output_mi_thunk): Likewise. * config/sh/sh.c (sh_output_mi_thunk): Likewise. * config/sparc/sparc.c (sparc_output_mi_thunk): Likewise. * config/spu/spu.c (spu_output_mi_thunk): Likewise. * config/stormy16/stormy16.c (xstormy16_asm_output_mi_thunk): Likewise. * config/tilegx/tilegx.c (tilegx_output_mi_thunk): Likewise. * config/tilepro/tilepro.c (tilepro_asm_output_mi_thunk): Likewise. * config/vax/vax.c (vax_output_mi_thunk): Likewise. From-SVN: r271293
2019-05-16tree-ssa-alias.c (alias_stats): Add aliasing_component_refs_p_may_alias and ↵Jan Hubicka2-8/+52
aliasing_component_refs_p_no_alias. * tree-ssa-alias.c (alias_stats): Add aliasing_component_refs_p_may_alias and aliasing_component_refs_p_no_alias. (dump_alias_stats): Print aliasing_component_refs_p stats. (aliasing_component_refs_p): Update stats. From-SVN: r271292
2019-05-16Do not allow target_clones with alias attr (PR lto/90500).Martin Liska5-1/+31
2019-05-16 Martin Liska <mliska@suse.cz> PR lto/90500 * multiple_target.c (expand_target_clones): Do not allow target_clones being used with a symbol that is an alias. 2019-05-16 Martin Liska <mliska@suse.cz> PR lto/90500 * gcc.target/i386/pr90500-1.c: New test. * gcc.target/i386/pr90500-2.c: New test. From-SVN: r271289
2019-05-16tree-ssa-uninit: avoid ICE with BIT_AND_EXPR (PR 90394)Vladislav Ivanishin5-1/+94
2019-05-16 Vladislav Ivanishin <vlad@ispras.ru> PR tree-optimization/90394 * tree-ssa-uninit.c (is_pred_expr_subset_of): Potentially give false positives rather than ICE for cases where (code2 == NE_EXPR && code1 == BIT_AND_EXPR). testsuite/ * gcc.dg/uninit-pr90394-1-gimple.c: New test. * gcc.dg/uninit-pr90394.c: New test. From-SVN: r271287
2019-05-16re PR fortran/90329 (Incompatibility between gfortran and C lapack calls)Jakub Jelinek8-4/+62
PR fortran/90329 * tree-core.h (struct tree_decl_common): Document decl_nonshareable_flag for PARM_DECLs. * tree.h (DECL_HIDDEN_STRING_LENGTH): Define. * calls.c (expand_call): Don't try tail call if caller has any DECL_HIDDEN_STRING_LENGTH PARM_DECLs that are or might be passed on the stack and callee needs to pass any arguments on the stack. * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Use else if instead of series of mutually exclusive ifs. Handle DECL_HIDDEN_STRING_LENGTH for PARM_DECLs. * tree-streamer-out.c (pack_ts_decl_common_value_fields): Likewise. * trans-decl.c (create_function_arglist): Set DECL_HIDDEN_STRING_LENGTH on hidden string length PARM_DECLs if len is constant. From-SVN: r271285
2019-05-16* lto-streamer.h (LTO_major_version): Bump to 9.Jakub Jelinek2-1/+5
From-SVN: r271284
2019-05-16re PR testsuite/90502 (gcc.dg/tree-ssa/vector-6.c FAILs)Richard Biener2-2/+9
2019-05-16 Richard Biener <rguenther@suse.de> PR testsuite/90502 * gcc.dg/tree-ssa/vector-6.c: Adjust for half of the transforms happening earlier now. From-SVN: r271283
2019-05-16testsuite - improve check_effective_target_cet.Iain Sandoe2-1/+6
In some cases the test using setssbsy was not enough to detemine support for the CET insns. Adding -fcf-protection explicitly causes other insns to be emitted (e.g. endbr32/64) which are a more complete check. 2019-05-16 Iain Sandoe <iain@sandoe.co.uk> * lib/target-supports.exp (check_effective_target_cet): Add the -fcf-protection flag to the build conditions. From-SVN: r271282
2019-05-16re PR tree-optimization/90106 (builtin sqrt() ignoring libm's sqrt call result)Jun Ma5-42/+85
PR tree-optimization/90106 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): Add new parameter as new internal function call, also move it to new basic block. (use_internal_fn): Pass internal function call to shrink_wrap_one_built_in_call_with_conds. gcc/testsuite * gcc.dg/cdce1.c: Check tailcall code generation after cdce pass. * gcc.dg/cdce2.c: Likewise. From-SVN: r271281
2019-05-16[RTEMS] Change multilibs for ARMSebastian Huber2-5/+11
Account for Cortex-M3 Errata 602117. The -mfix-cortex-m3-ldrd option is enabled by default, if -mcpu=cortex-m3 is used. gcc/ * config/arm/t-rtems: Replace ARMv7-M multilibs with Cortex-M multilibs. From-SVN: r271280
2019-05-16re PR target/90424 (memcpy into vector builtin not optimized)Richard Biener6-13/+124
2019-05-16 Richard Biener <rguenther@suse.de> PR tree-optimization/90424 * tree-ssa.c (non_rewritable_lvalue_p): Handle inserts from aligned subvectors. (execute_update_addresses_taken): Likewise. * tree-cfg.c (verify_gimple_assign_ternary): Likewise. * g++.target/i386/pr90424-1.C: New testcase. * g++.target/i386/pr90424-2.C: Likewise. From-SVN: r271279
2019-05-16gimple-parser.c (c_parser_gimple_statement): Handle __BIT_INSERT.Richard Biener6-17/+79
2019-05-16 Richard Biener <rguenther@suse.de> c/ * gimple-parser.c (c_parser_gimple_statement): Handle __BIT_INSERT. (c_parser_gimple_unary_expression): Likewise. * gimple-pretty-print.c (dump_ternary_rhs): Dump BIT_INSERT_EXPR as __BIT_INSERT with -gimple. * gcc.dg/gimplefe-40.c: Amend again. From-SVN: r271278
2019-05-16compiler: improve escape analysis on interface conversionsCherry Zhang11-23/+369
If an interface does not escape, it doesn't need a heap allocation to hold the data (for non-direct interface type). This CL improves the escape analysis to track interface conversions, and reduces these allocations. Implicit interface conversions were mostly added late in the compilation pipeline, after the escape analysis. For the escape analysis to see them, we move the introduction of these conversions earlier, right before the escape analysis. Now that the compiler can generate interface conversions inlined, gcc/testsuite/go.test/test/nilptr2.go needs to be adjusted as in golang.org/cl/176579, so the use function does an actual use. Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/176459 * go.test/test/nilptr2.go: Change use function to actually do something. From-SVN: r271276
2019-05-16Daily bump.GCC Administrator1-1/+1
From-SVN: r271275
2019-05-16re PR middle-end/90478 (ICE in emit_case_dispatch_table at gcc/stmt.c:796)Jakub Jelinek2-2/+7
PR middle-end/90478 * gcc.dg/tree-ssa/pr90478.c: Add empty dg-options. Use long long type instead of long. From-SVN: r271271
2019-05-15omp-low.c (lower_rec_input_clauses): For if (0) or simdlen (1) set max_vf to 1.Jakub Jelinek5-0/+69
* omp-low.c (lower_rec_input_clauses): For if (0) or simdlen (1) set max_vf to 1. * omp-expand.c (expand_omp_simd): For if (0) or simdlen (1) clear safelen_int and set loop->dont_vectorize. * c-c++-common/gomp/simd8.c: New test. From-SVN: r271270
2019-05-15re PR debug/90197 (Cannot step through simple loop at -O -g)Jakub Jelinek2-3/+35
PR debug/90197 * cp-gimplify.c (genericize_cp_loop): Emit a DEBUG_BEGIN_STMT before the condition (or if missing or constant non-zero at the end of the loop. Emit a DEBUG_BEGIN_STMT before the increment expression if any. Don't call protected_set_expr_location on incr if it already has a location. From-SVN: r271269
2019-05-15CWG 2096 - constraints on literal unions.Marek Polacek4-10/+88
* class.c (check_field_decls): Initialize booleans directly. A union is literal if at least one of its non-static data members is of non-volatile literal type. * g++.dg/cpp0x/literal-type1.C: New test. From-SVN: r271267
2019-05-15Remove translation string markersJanne Blomqvist2-14/+17
C preprocessor definitions should not be translated. 2019-05-15 Janne Blomqvist <jb@gcc.gnu.org> * parse.c (gfc_parse_file): Remove translation string markers. From-SVN: r271261
2019-05-15Allow opening file on multiple unitsJanne Blomqvist3-1/+19
As of Fortran 2018 it's allowed to open the same file on multiple units. libgfortran/ChangeLog: 2019-05-15 Janne Blomqvist <jb@gcc.gnu.org> PR fortran/90461 * io/open.c (new_unit): Don't check if the file is already open for F2018. testsuite/ChangeLog: 2019-05-15 Janne Blomqvist <jb@gcc.gnu.org> PR fortran/90461 * gfortran.dg/open_errors_2.f90: Add -std=f2008, adjust line number. * gfortran.dg/open_errors_3.f90: New test. From-SVN: r271260
2019-05-15i386-expand.c (ix86_split_idivmod): Rename signed_p argument to unsigned_p.Uros Bizjak2-14/+15
* config/i386/i386-expand.c (ix86_split_idivmod): Rename signed_p argument to unsigned_p. Update all uses for changed polarity. * config/i386/i386.md (u_bool): Handle DIV and UDIV RTXes. (divmod splitters): Use u_bool macro in the call to ix86_split_idivmod. From-SVN: r271259
2019-05-15cp-tree.h (REFERENCE_VLA_OK): Remove.Paolo Carlini3-7/+5
2019-05-15 Paolo Carlini <paolo.carlini@oracle.com> * cp-tree.h (REFERENCE_VLA_OK): Remove. * lambda.c (build_capture_proxy): Remove use of the above. From-SVN: r271258
2019-05-15i386: Add tests for MMX intrinsic emulations with SSEH.J. Lu98-0/+5241
Test MMX intrinsics with -msse2 in 32-bit mode and -msse2 -mno-mmx in 64-bit mode. PR target/89021 * gcc.target/i386/mmx-vals.h: New file. * gcc.target/i386/sse2-mmx-2.c: Likewise. * gcc.target/i386/sse2-mmx-3.c: Likewise. * gcc.target/i386/sse2-mmx-4.c: Likewise. * gcc.target/i386/sse2-mmx-5.c: Likewise. * gcc.target/i386/sse2-mmx-6.c: Likewise. * gcc.target/i386/sse2-mmx-7.c: Likewise. * gcc.target/i386/sse2-mmx-8.c: Likewise. * gcc.target/i386/sse2-mmx-9.c: Likewise. * gcc.target/i386/sse2-mmx-10.c: Likewise. * gcc.target/i386/sse2-mmx-11.c: Likewise. * gcc.target/i386/sse2-mmx-12.c: Likewise. * gcc.target/i386/sse2-mmx-13.c: Likewise. * gcc.target/i386/sse2-mmx-14.c: Likewise. * gcc.target/i386/sse2-mmx-15.c: Likewise. * gcc.target/i386/sse2-mmx-16.c: Likewise. * gcc.target/i386/sse2-mmx-17.c: Likewise. * gcc.target/i386/sse2-mmx-18a.c: Likewise. * gcc.target/i386/sse2-mmx-18b.c: Likewise. * gcc.target/i386/sse2-mmx-18c.c: Likewise. * gcc.target/i386/sse2-mmx-19a.c: Likewise. * gcc.target/i386/sse2-mmx-18b.c: Likewise. * gcc.target/i386/sse2-mmx-19c.c: Likewise. * gcc.target/i386/sse2-mmx-19d.c: Likewise. * gcc.target/i386/sse2-mmx-19e.c: Likewise. * gcc.target/i386/sse2-mmx-20.c: Likewise. * gcc.target/i386/sse2-mmx-21.c: Likewise. * gcc.target/i386/sse2-mmx-22.c: Likewise. * gcc.target/i386/sse2-mmx-cvtpi2ps.c: Likewise. * gcc.target/i386/sse2-mmx-cvtps2pi.c: Likewise. * gcc.target/i386/sse2-mmx-cvttps2pi.c: Likewise. * gcc.target/i386/sse2-mmx-maskmovq.c: Likewise. * gcc.target/i386/sse2-mmx-packssdw.c: Likewise. * gcc.target/i386/sse2-mmx-packsswb.c: Likewise. * gcc.target/i386/sse2-mmx-packuswb.c: Likewise. * gcc.target/i386/sse2-mmx-paddb.c: Likewise. * gcc.target/i386/sse2-mmx-paddd.c: Likewise. * gcc.target/i386/sse2-mmx-paddq.c: Likewise. * gcc.target/i386/sse2-mmx-paddsb.c: Likewise. * gcc.target/i386/sse2-mmx-paddsw.c: Likewise. * gcc.target/i386/sse2-mmx-paddusb.c: Likewise. * gcc.target/i386/sse2-mmx-paddusw.c: Likewise. * gcc.target/i386/sse2-mmx-paddw.c: Likewise. * gcc.target/i386/sse2-mmx-pand.c: Likewise. * gcc.target/i386/sse2-mmx-pandn.c: Likewise. * gcc.target/i386/sse2-mmx-pavgb.c: Likewise. * gcc.target/i386/sse2-mmx-pavgw.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpeqb.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpeqd.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpeqw.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpgtb.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpgtd.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpgtw.c: Likewise. * gcc.target/i386/sse2-mmx-pextrw.c: Likewise. * gcc.target/i386/sse2-mmx-pinsrw.c: Likewise. * gcc.target/i386/sse2-mmx-pmaddwd.c: Likewise. * gcc.target/i386/sse2-mmx-pmaxsw.c: Likewise. * gcc.target/i386/sse2-mmx-pmaxub.c: Likewise. * gcc.target/i386/sse2-mmx-pminsw.c: Likewise. * gcc.target/i386/sse2-mmx-pminub.c: Likewise. * gcc.target/i386/sse2-mmx-pmovmskb.c: Likewise. * gcc.target/i386/sse2-mmx-pmulhuw.c: Likewise. * gcc.target/i386/sse2-mmx-pmulhw.c: Likewise. * gcc.target/i386/sse2-mmx-pmullw.c: Likewise. * gcc.target/i386/sse2-mmx-pmuludq.c: Likewise. * gcc.target/i386/sse2-mmx-por.c: Likewise. * gcc.target/i386/sse2-mmx-psadbw.c: Likewise. * gcc.target/i386/sse2-mmx-pshufw.c: Likewise. * gcc.target/i386/sse2-mmx-pslld.c: Likewise. * gcc.target/i386/sse2-mmx-pslldi.c: Likewise. * gcc.target/i386/sse2-mmx-psllq.c: Likewise. * gcc.target/i386/sse2-mmx-psllqi.c: Likewise. * gcc.target/i386/sse2-mmx-psllw.c: Likewise. * gcc.target/i386/sse2-mmx-psllwi.c: Likewise. * gcc.target/i386/sse2-mmx-psrad.c: Likewise. * gcc.target/i386/sse2-mmx-psradi.c: Likewise. * gcc.target/i386/sse2-mmx-psraw.c: Likewise. * gcc.target/i386/sse2-mmx-psrawi.c: Likewise. * gcc.target/i386/sse2-mmx-psrld.c: Likewise. * gcc.target/i386/sse2-mmx-psrldi.c: Likewise. * gcc.target/i386/sse2-mmx-psrlq.c: Likewise. * gcc.target/i386/sse2-mmx-psrlqi.c: Likewise. * gcc.target/i386/sse2-mmx-psrlw.c: Likewise. * gcc.target/i386/sse2-mmx-psrlwi.c: Likewise. * gcc.target/i386/sse2-mmx-psubb.c: Likewise. * gcc.target/i386/sse2-mmx-psubd.c: Likewise. * gcc.target/i386/sse2-mmx-psubq.c: Likewise. * gcc.target/i386/sse2-mmx-psubusb.c: Likewise. * gcc.target/i386/sse2-mmx-psubusw.c: Likewise. * gcc.target/i386/sse2-mmx-psubw.c: Likewise. * gcc.target/i386/sse2-mmx-punpckhbw.c: Likewise. * gcc.target/i386/sse2-mmx-punpckhdq.c: Likewise. * gcc.target/i386/sse2-mmx-punpckhwd.c: Likewise. * gcc.target/i386/sse2-mmx-punpcklbw.c: Likewise. * gcc.target/i386/sse2-mmx-punpckldq.c: Likewise. * gcc.target/i386/sse2-mmx-punpcklwd.c: Likewise. * gcc.target/i386/sse2-mmx-pxor.c: Likewise. From-SVN: r271254
2019-05-15i386: Enable TM MMX intrinsics with SSE2H.J. Lu2-8/+14
This patch enables TM MMX intrinsics with SSE2 when MMX is disabled. PR target/89021 * config/i386/i386-builtins.c (bdesc_tm): Enable MMX intrinsics with SSE2. From-SVN: r271253
2019-05-15i386: Allow MMX intrinsic emulation with SSEH.J. Lu8-70/+119
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA by default with TARGET_MMX_WITH_SSE. For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit mode since MMX intrinsics can be emulated wit SSE. gcc/ PR target/89021 * config/i386/i386-builtin.def: Enable MMX intrinsics with SSE/SSE2/SSSE3. * config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins): Likewise. * config/i386/i386-expand.c (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX intrinsics with TARGET_MMX_WITH_SSE. * config/i386/mmintrin.h: Only require SSE2 if __MMX_WITH_SSE__ is defined. gcc/testsuite/ PR target/89021 * gcc.target/i386/pr82483-1.c: Error only on ia32. * gcc.target/i386/pr82483-2.c: Likewise. From-SVN: r271252
2019-05-15i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSEH.J. Lu2-44/+101
PR target/89021 * config/i386/mmx.md (*vec_dupv2sf): Changed to define_insn_and_split to support SSE emulation. (*vec_extractv2sf_0): Likewise. (*vec_extractv2sf_1): Likewise. (*vec_extractv2si_0): Likewise. (*vec_extractv2si_1): Likewise. (*vec_extractv2si_zext_mem): Likewise. (vec_setv2sf): Also allow TARGET_MMX_WITH_SSE. (vec_extractv2sf_1 splitter): Likewise. (vec_extractv2sfsf): Likewise. (vec_setv2si): Likewise. (vec_extractv2si_1 splitter): Likewise. (vec_extractv2sisi): Likewise. (vec_setv4hi): Likewise. (vec_extractv4hihi): Likewise. (vec_setv8qi): Likewise. (vec_extractv8qiqi): Likewise. (vec_extractv2sfsf): Also allow TARGET_MMX_WITH_SSE. Pass TARGET_MMX_WITH_SSE ix86_expand_vector_extract. (vec_extractv2sisi): Likewise. (vec_extractv4hihi): Likewise. (vec_extractv8qiqi): Likewise. (vec_initv2sfsf): Also allow TARGET_MMX_WITH_SSE. Pass TARGET_MMX_WITH_SSE to ix86_expand_vector_init. (vec_initv2sisi): Likewise. (vec_initv4hihi): Likewise. (vec_initv8qiqi): Likewise. (vec_setv2si): Also allow TARGET_MMX_WITH_SSE. Pass TARGET_MMX_WITH_SSE to ix86_expand_vector_set. (vec_setv4hi): Likewise. (vec_setv8qi): Likewise. From-SVN: r271251
2019-05-15i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSEH.J. Lu2-3/+11
PR target/89021 * config/i386/mmx.md (MMXMODE:mov<mode>): Also allow TARGET_MMX_WITH_SSE. (MMXMODE:*mov<mode>_internal): Likewise. (MMXMODE:movmisalign<mode>): Likewise. From-SVN: r271250
2019-05-15Prevent allocation of MMX registers with TARGET_MMX_WITH_SSEUros Bizjak3-5/+38
2019-05-15 Uroš Bizjak <ubizjak@gmail.com> PR target/89021 * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute. * config/i386/sse.md (sse2_cvtpi2pd): Ditto. (sse2_cvtpd2pi): Ditto. (sse2_cvttpd2pi): Ditto. (*vec_concatv2sf_sse4_1): Ditto. (*vec_concatv2sf_sse): Ditto. (*vec_concatv2si_sse4_1): Ditto. (*vec_concatv2si): Ditto. (*vec_concatv4si_0): Ditto. (*vec_concatv2di_0): Ditto. From-SVN: r271249
2019-05-15i386: Emulate MMX abs<mode>2 with SSEH.J. Lu2-6/+14
Emulate MMX abs<mode>2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs<mode>2): Add SSE emulation. From-SVN: r271248
2019-05-15i386: Emulate MMX ssse3_palignrdi with SSEH.J. Lu2-10/+54
Emulate MMX version of palignrq with SSE version by concatenating 2 64-bit MMX operands into a single 128-bit SSE operand, followed by SSE psrldq. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_palignrdi): Changed to define_insn_and_split to support SSE emulation. From-SVN: r271247
2019-05-15i386: Emulate MMX ssse3_psign<mode>3 with SSEH.J. Lu2-7/+16
Emulate MMX ssse3_psign<mode>3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation. From-SVN: r271246
2019-05-15i386: Emulate MMX pshufb with SSE versionH.J. Lu2-9/+44
Emulate MMX version of pshufb with SSE version by masking out the bit 3 of the shuffle control byte. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. From-SVN: r271245
2019-05-15i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSEH.J. Lu2-10/+23
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX or TARGET_MMX_WITH_SSE. (*ssse3_pmulhrswv4hi3): Add SSE emulation. From-SVN: r271244
2019-05-15i386: Emulate MMX ssse3_pmaddubsw with SSEH.J. Lu2-7/+16
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation. From-SVN: r271243
2019-05-15i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSEH.J. Lu2-8/+32
Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3): Changed to define_insn_and_split to support SSE emulation. From-SVN: r271242
2019-05-15i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSEH.J. Lu2-8/+32
Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3): Changed to define_insn_and_split to support SSE emulation. From-SVN: r271241
2019-05-15i386: Make _mm_empty () as NOP without MMXH.J. Lu2-1/+36
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP without MMX. PR target/89021 * config/i386/mmx.md (mmx_<emms>): Renamed to ... (*mmx_<emms>): This. (mmx_<emms>): New expander. From-SVN: r271240
2019-05-15i386: Emulate MMX umulv1siv1di3 with SSE2H.J. Lu2-10/+23
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation support. (*sse2_umulv1siv1di3): Add SSE2 emulation. From-SVN: r271239
2019-05-15i386: Emulate MMX movntq with SSE2 movntidiH.J. Lu2-5/+14
Emulate MMX movntq with SSE2 movntidi. Only register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse_movntq): Add SSE2 emulation. From-SVN: r271238
2019-05-15i386: Emulate MMX mmx_psadbw with SSEH.J. Lu2-7/+17
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. From-SVN: r271237
2019-05-15i386: Emulate MMX mmx_uavgv4hi3 with SSEH.J. Lu2-10/+23
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. From-SVN: r271236
2019-05-15i386: Emulate MMX mmx_uavgv8qi3 with SSEH.J. Lu2-10/+22
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv8qi3): Add SSE emulation. From-SVN: r271235
2019-05-15i386: Emulate MMX maskmovq with SSE2 maskmovdquH.J. Lu2-0/+67
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by zero-extending source and mask operands to 128 bits. Handle unmapped bits 64:127 at memory address by adjusting source and mask operands together with memory address. PR target/89021 * config/i386/xmmintrin.h: Emulate MMX maskmovq with SSE2 maskmovdqu for __MMX_WITH_SSE__. From-SVN: r271234
2019-05-15i386: Emulate MMX mmx_umulv4hi3_highpart with SSEH.J. Lu2-10/+23
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_umulv4hi3_highpart): Add SSE emulation. From-SVN: r271233
2019-05-15i386: Emulate MMX mmx_pmovmskb with SSEH.J. Lu2-7/+29
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb from QImode to SImode. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. From-SVN: r271232
2019-05-15i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSEH.J. Lu2-20/+59
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_<code>v4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_<code>v8qi3): Likewise. (smaxmin:<code>v4hi3): New. (umaxmin:<code>v8qi3): Likewise. (smaxmin:*mmx_<code>v4hi3): Add SSE emulation. (umaxmin:*mmx_<code>v8qi3): Likewise. From-SVN: r271231
2019-05-15i386: Emulate MMX mmx_pinsrw with SSEH.J. Lu2-10/+30
Emulate MMX mmx_pinsrw with SSE. Only SSE register destination operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. From-SVN: r271230
2019-05-15i386: Emulate MMX mmx_pextrw with SSEH.J. Lu2-7/+16
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. From-SVN: r271229
2019-05-15i386: Emulate MMX sse_cvtpi2ps with SSEH.J. Lu2-8/+63
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of destination XMM register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (sse_cvtpi2ps): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. From-SVN: r271228
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