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2019-10-18re PR target/86753 (gcc.target/aarch64/sve/vcond_[45].c fail after recent ↵Prathamesh Kulkarni12-43/+281
combine patch) 2019-10-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> Richard Sandiford <richard.sandiford@arm.com> PR target/86753 * tree-vectorizer.h (scalar_cond_masked_key): New struct, and define hashmap traits for it. (loop_vec_info::scalar_cond_masked_set): New member. (vect_record_loop_mask): Adjust prototype. * tree-vectorizer.c (scalar_cond_masked_key::get_cond_ops_from_tree): Implement method. * tree-vect-loop.c (vectorizable_reduction): Pass NULL as last arg to vect_record_loop_mask. (vectorizable_live_operation): Likewise. (vect_record_loop_mask): New param scalar_mask. Add entry cond, loop_mask to scalar_cond_masked_set if scalar_mask is non NULL. * tree-vect-stmts.c (check_load_store_masking): New param scalar_mask. Pass it as last arg to vect_record_loop_mask. (vectorizable_call): Pass scalar_mask as last arg to vect_record_loop_mask. (vectorizable_store): Likewise. (vectorizable_load): Likewise. (vectorizable_condition): Check if another part of vectorized code applies loop_mask to condition or to it's inverse, and if yes, apply loop_mask to result of vector comparison. testsuite/ * gcc.target/aarch64/sve/cond_cnot_2.c: Remove XFAIL from { scan-assembler-not {\tsel\t}. * gcc.target/aarch64/sve/cond_convert_1.c: Adjust to make only one load conditional. * gcc.target/aarch64/sve/cond_convert_4.c: Likewise. * gcc.target/aarch64/sve/cond_unary_2.c: Likewise. * gcc.target/aarch64/sve/vcond_4.c: Remove XFAIL's. * gcc.target/aarch64/sve/vcond_5.c: Likewise. Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com> From-SVN: r277141
2019-10-18Daily bump.GCC Administrator1-1/+1
From-SVN: r277140
2019-10-17pa.c (pa_output_indirect_call): Fix typos in last change.John David Anglin2-7/+11
* config/pa/pa.c (pa_output_indirect_call): Fix typos in last change. From-SVN: r277135
2019-10-18re PR tree-optimization/92056 (ice in expr_object_size, at tree-object-si ↵Jakub Jelinek4-0/+49
ze.c:675 with -O3) PR tree-optimization/92056 * tree-ssa-strlen.c (determine_min_objsize): Call init_object_sizes before calling compute_builtin_object_size. * gcc.dg/tree-ssa/pr92056.c: New test. From-SVN: r277134
2019-10-17decl.c (grokfndecl): Remove redundant use of in_system_header_at.Paolo Carlini9-46/+58
/cp 2019-10-17 Paolo Carlini <paolo.carlini@oracle.com> * decl.c (grokfndecl): Remove redundant use of in_system_header_at. (compute_array_index_type_loc): Likewise. (grokdeclarator): Likewise. * error.c (cp_printer): Likewise. * lambda.c (add_default_capture): Likewise. * parser.c (cp_parser_primary_expression): Likewise. (cp_parser_selection_statement): Likewise. (cp_parser_toplevel_declaration): Likewise. (cp_parser_enumerator_list): Likewise. (cp_parser_using_declaration): Likewise. (cp_parser_member_declaration): Likewise. (cp_parser_exception_specification_opt): Likewise. (cp_parser_std_attribute_spec): Likewise. * pt.c (do_decl_instantiation): Likewise. (do_type_instantiation): Likewise. * typeck.c (cp_build_unary_op): Likewise. * decl.c (check_tag_decl): Pass to in_system_header_at the same location used for the permerror. (grokdeclarator): Likewise. * decl.c (check_tag_decl): Use locations[ds_typedef] in error_at. /testsuite 2019-10-17 Paolo Carlini <paolo.carlini@oracle.com> * g++.old-deja/g++.other/decl9.C: Check locations too. From-SVN: r277133
2019-10-17[Darwin, PPC] Fix PR 65342.Iain Sandoe4-35/+114
The current Darwin load/store lo_sum patterns have neither predicate nor constraint. This means that most parts of the backend, which rely on recog() to validate the rtx, can produce invalid combinations/selections. For 32bit cases this isn't a problem since we can load/store to unaligned addresses using D-mode insns. Conversely, for 64bit instructions that use DS mode, this can manifest as assemble errors (for an assembler that checks the LO14 relocations), or as crashes caused by wrong offsets (or worse, wrong content for the two LSBs). What we want to check for "Y" on Darwin is: - that the alignment of the Symbols' target is sufficient for DS mode - that the offset is suitable for DS mode. (while looking through the Mach-O PIC unspecs). So, the patch removes the Darwin-specific lo_sum patterns (we begin using the movdi_internal64 patterns). We also we need to extend the handling of the mem_operand_gpr constraint to allow looking through Mach-O PIC UNSPECs in the lo_sum cases. gcc/ChangeLog: 2019-10-17 Iain Sandoe <iain@sandoe.co.uk> PR target/65342 * config/rs6000/darwin.md (movdi_low, movsi_low_st): Delete. (movdi_low_st): Delete. * config/rs6000/rs6000.c (darwin_rs6000_legitimate_lo_sum_const_p): New. (mem_operand_gpr): Validate Mach-O LO_SUM cases separately. * config/rs6000/rs6000.md (movsi_low): Delete. From-SVN: r277130
2019-10-17cp-gimplify.c (cp_gimplify_expr): Use get_initialized_tmp_var.Jason Merrill6-10/+24
* cp-gimplify.c (cp_gimplify_expr): Use get_initialized_tmp_var. The comment for get_formal_tmp_var says that it shouldn't be used for expressions whose value might change between initialization and use, and in this case we're creating a temporary precisely because the value might change, so we should use get_initialized_tmp_var instead. I also noticed that many callers of get_initialized_tmp_var pass NULL for post_p, so it seems appropriate to make it a default argument. gcc/ * gimplify.h (get_initialized_tmp_var): Add default argument to post_p. * gimplify.c (gimplify_self_mod_expr, gimplify_omp_atomic): Remove NULL post_p argument. * targhooks (std_gimplify_va_arg_expr): Likewise. From-SVN: r277128
2019-10-17tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.Richard Biener4-109/+43
2019-10-17 Richard Biener <rguenther@suse.de> * tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove. (STMT_VINFO_VEC_COND_REDUC_CODE): Likewise. * tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not initialize STMT_VINFO_VEC_COND_REDUC_CODE. * tree-vect-loop.c (vect_is_simple_reduction): Set STMT_VINFO_REDUC_CODE. (vectorizable_reduction): Remove dead and redundant code, use STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE. From-SVN: r277126
2019-10-17Fix breakage introduced by r276985.Georg-Johann Lay3-9/+14
* config/avr/avr.c (avr_option_override): Remove set of PARAM_ALLOW_STORE_DATA_RACES. * common/config/avr/avr-common.c (avr_option_optimization_table) [OPT_LEVELS_ALL]: Turn on -fallow-store-data-races. From-SVN: r277115
2019-10-17i386: Add clear_ratio to processor_costsH.J. Lu3-1/+34
i386.h has #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) It is impossible to have CLEAR_RATIO > 6. This patch adds clear_ratio to processor_costs, sets it to the minimum of 6 and move_ratio in all cost models and defines CLEAR_RATIO with clear_ratio. * config/i386/i386.h (processor_costs): Add clear_ratio. (CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio. * config/i386/x86-tune-costs.h: Set clear_ratio to the minimum of 6 and move_ratio in all cost models. From-SVN: r277114
2019-10-17tree-vect-loop.c (check_reduction_path): Compute reduction operation here.Richard Biener2-101/+45
2019-10-17 Richard Biener <rguenther@suse.de> * tree-vect-loop.c (check_reduction_path): Compute reduction operation here. (vect_is_simple_reduction): Remove special-case of single-stmt reduction path detection. From-SVN: r277112
2019-10-17[arm] Add default FPU for Marvell-pj4Richard Earnshaw2-1/+5
According to GAS, the Marvell PJ4 CPU has a VFPv3-D16 floating point unit, but GCC's CPU configuration tables omits this meaning that -mfpu=auto will not correctly select the FPU. This patch fixes this by adding the +fp option to the architecture specification for this device. * config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture. From-SVN: r277111
2019-10-17[AArch64][SVE2] Support for EOR3 and variants of BSLYuliang Wang11-0/+351
2019-10-17 Yuliang Wang <yuliang.wang@arm.com> gcc/ * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>) (aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>) (aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>) (aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>): New combine patterns. * config/aarch64/iterators.md (BSL_DUP): New int iterator for the above. (bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above. gcc/testsuite/ * gcc.target/aarch64/sve2/eor3_1.c: New test. * gcc.target/aarch64/sve2/nlogic_1.c: As above. * gcc.target/aarch64/sve2/nlogic_2.c: As above. * gcc.target/aarch64/sve2/bitsel_1.c: As above. * gcc.target/aarch64/sve2/bitsel_2.c: As above. * gcc.target/aarch64/sve2/bitsel_3.c: As above. * gcc.target/aarch64/sve2/bitsel_4.c: As above. From-SVN: r277110
2019-10-17Remove incorrect PR from ChangeLog.Aldy Hernandez1-1/+0
From-SVN: r277108
2019-10-17re PR tree-optimization/92131 (incorrect assumption that (ao >= 0) is always ↵Aldy Hernandez4-3/+13
false) PR tree-optimization/92131 * tree-vrp.c (value_range_base::dump): Display +INF for both pointers and integers when appropriate. From-SVN: r277107
2019-10-17[vect] Be consistent in versioning threshold useAndre Vieira2-0/+14
gcc/ChangeLog: 2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com> * tree-vect-loop.c (vect_analyze_loop_2): Use same condition to decide when to use versioning threshold. From-SVN: r277105
2019-10-17[vect] Outline code into new function: determine_peel_for_niterAndre Vieira2-40/+58
gcc/ChangeLog: 2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com> * tree-vect-loop.c (determine_peel_for_niter): New function contained outlined code from ... (vect_analyze_loop_2): ... here. From-SVN: r277103
2019-10-17[C++ PATCH] builtin fn creationNathan Sidwell2-49/+36
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01283.html * decl.c (builtin_function_1): Merge into ... (cxx_builtin_function): ... here. Nadger the decl before maybe copying it. Set the context. (cxx_builtin_function_ext_scope): Push to top level, then call cxx_builtin_function. From-SVN: r277102
2019-10-17[vect] Refactor versioning thresholdAndre Vieira4-17/+15
gcc/ChangeLog: 2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com> * tree-vect-loop.c (vect_transform_loop): Move code from here... * tree-vect-loop-manip.c (vect_loop_versioning): ... to here. * tree-vectorizer.h (vect_loop_versioning): Remove unused parameters. From-SVN: r277101
2019-10-17tree-vect-loop.c (needs_fold_left_reduction_p): Export.Richard Biener4-81/+80
2019-10-17 Richard Biener <rguenther@suse.de> * tree-vect-loop.c (needs_fold_left_reduction_p): Export. (vect_is_simple_reduction): Move all validity checks ... (vectorizable_reduction): ... here. Compute whether we need a fold-left reduction here. * tree-vect-patterns.c (vect_reassociating_reduction_p): Merge both overloads, check needs_fold_left_reduction_p directly. * tree-vectorizer.h (needs_fold_left_reduction_p): Declare. From-SVN: r277100
2019-10-17[ARM,testsuite] Fix typo in arm_arch_v8a_ok effective target.Christophe Lyon17-16/+35
The arm_arch_v8a_ok effective-target lacks a closing bracket in these tests, resulting in it being ignored. 2019-10-17 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/arm/vseleqdf.c: Add missing closing bracket. * gcc.target/arm/vseleqsf.c: Likewise. * gcc.target/arm/vselgedf.c: Likewise. * gcc.target/arm/vselgesf.c: Likewise. * gcc.target/arm/vselgtdf.c: Likewise. * gcc.target/arm/vselgtsf.c: Likewise. * gcc.target/arm/vselledf.c: Likewise. * gcc.target/arm/vsellesf.c: Likewise. * gcc.target/arm/vselltdf.c: Likewise. * gcc.target/arm/vselltsf.c: Likewise. * gcc.target/arm/vselnedf.c: Likewise. * gcc.target/arm/vselnesf.c: Likewise. * gcc.target/arm/vselvcdf.c: Likewise. * gcc.target/arm/vselvcsf.c: Likewise. * gcc.target/arm/vselvsdf.c: Likewise. * gcc.target/arm/vselvssf.c: Likewise. From-SVN: r277099
2019-10-17tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix TARGET_MEM_REF creation.Richard Biener2-1/+6
2019-10-17 Richard Biener <rguenther@suse.de> * tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix TARGET_MEM_REF creation. From-SVN: r277098
2019-10-17Additional test cases for using automatic variables in equivalence statements.Mark Eggleston6-0/+100
From-SVN: r277097
2019-10-17progmem-error-1.cpp: Fix location of the expected diagnostic.Georg-Johann Lay2-4/+6
gcc/testsuite/ * gcc.target/avr/progmem-error-1.cpp: Fix location of the expected diagnostic. From-SVN: r277096
2019-10-17re PR testsuite/92125 (New test gcc.dg/ipa/pr91088.c introduced in r277054 ↵Feng Xue2-2/+7
fails) PR testsuite/92125 2019-10-17 Feng Xue <fxue@os.amperecomputing.com> PR testsuite/92125 * gcc.dg/ipa/pr91088.c: Change char conversion to bitand. From-SVN: r277095
2019-10-17re PR tree-optimization/92129 (ICE in vectorizable_reduction, at ↵Richard Biener2-0/+7
tree-vect-loop.c:5869) 2019-10-17 Richard Biener <rguenther@suse.de> PR tree-optimization/92129 * tree-vect-loop.c (vectorizable_reduction): Also fail on GIMPLE_SINGLE_RHS. From-SVN: r277094
2019-10-17re PR tree-optimization/92056 (ice in expr_object_size, at tree-object-si ↵Jakub Jelinek4-0/+28
ze.c:675 with -O3) PR tree-optimization/92056 * tree-object-size.c (cond_expr_object_size): Return early if then_ processing resulted in unknown size. * gcc.c-torture/compile/pr92056.c: New test. From-SVN: r277093
2019-10-17re PR tree-optimization/92115 (ICE in gimple_cond_get_ops_from_tree, at ↵Jakub Jelinek4-0/+25
gimple-expr.c:577) PR tree-optimization/92115 * tree-ssa-ifcombine.c (ifcombine_ifandif): Force condition into temporary if it could trap. * gcc.dg/pr92115.c: New test. From-SVN: r277092
2019-10-17re PR fortran/87752 (ICE in omp_add_variable, at gimplify.c:6776)Jakub Jelinek2-0/+17
PR fortran/87752 * gfortran.dg/gomp/pr87752.f90: New test. From-SVN: r277091
2019-10-17re PR debug/91887 (-fdebug-types-section ICE building chromium)Richard Biener4-12/+34
2019-10-17 Richard Biener <rguenther@suse.de> PR debug/91887 * dwarf2out.c (gen_formal_parameter_die): Also try to match context_die against a DW_TAG_GNU_formal_parameter_pack parent. * g++.dg/debug/dwarf2/pr91887.C: New testcase. From-SVN: r277090
2019-10-17Fix old file reference in gcc/cp/cp-gimplify.cLuis Machado2-1/+5
I've found this stale reference while looking at cp-gimplify.c. tree-gimple.c no longer exists and its contents were merged into gimple.c. Seems obvious enough. gcc/cp/ChangeLog: 2019-10-16 Luis Machado <luis.machado@linaro.org> * cp-gimplify.c: Fix reference to non-existing tree-gimple.c file. From-SVN: r277089
2019-10-17Daily bump.GCC Administrator1-1/+1
From-SVN: r277088
2019-10-17decl.c (cxx_maybe_build_cleanup): When clearing location of cleanup...Jakub Jelinek2-0/+7
* decl.c (cxx_maybe_build_cleanup): When clearing location of cleanup, if cleanup is a nop, clear location of its operand too. From-SVN: r277084
2019-10-17tree-ssa-strlen.c (maybe_invalidate): Use HOST_WIDE_INT_PRINT_UNSIGNED ↵Jakub Jelinek2-1/+7
instead of "%zu". * tree-ssa-strlen.c (maybe_invalidate): Use HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu". From-SVN: r277083
2019-10-16RISC-V: Include more registers in SIBCALL_REGS.Andrew Burgess3-4/+12
This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19. This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It also adds the missing riscv_regno_to_class change. Tested with cross riscv32-elf and riscv64-linux toolchain build and check. There were no regressions. I see about a 0.01% code size reduction for the C and libstdc++ libraries. gcc/ * config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing regs to SIBCALL_REGS. * config/riscv/riscv.c (riscv_regno_to_class): Change argument passing regs to SIBCALL_REGS. Co-Authored-By: Jim Wilson <jimw@sifive.com> From-SVN: r277082
2019-10-16PR tree-optimization/83821 - local aggregate initialization defeats strlen ↵Martin Sebor11-12/+694
optimization gcc/ChangeLog: PR tree-optimization/83821 * tree-ssa-strlen.c (maybe_invalidate): Add argument. Consider the length of a string when available. (handle_builtin_memset) Add argument. (handle_store, strlen_check_and_optimize_call): Same. (check_and_optimize_stmt): Same. Pass it to callees. gcc/testsuite/ChangeLog: PR tree-optimization/83821 * c-c++-common/Warray-bounds-4.c: Remove XFAIL. * gcc.dg/strlenopt-82.c: New test. * gcc.dg/strlenopt-83.c: Same. * gcc.dg/strlenopt-84.c: Same. * gcc.dg/strlenopt-85.c: Same. * gcc.dg/strlenopt-86.c: Same. * gcc.dg/tree-ssa/calloc-4.c: Same. * gcc.dg/tree-ssa/calloc-5.c: Same. From-SVN: r277080
2019-10-16PR tree-optimization/91996 - fold non-constant strlen relational expressionsMartin Sebor5-41/+422
gcc/testsuite/ChangeLog: PR tree-optimization/91996 * gcc.dg/strlenopt-80.c: New test. * gcc.dg/strlenopt-81.c: New test. gcc/ChangeLog: PR tree-optimization/91996 * tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location information. (compare_nonzero_chars): Add an overload. (count_nonzero_bytes): Add an argument. Call overload above. Handle non-constant lengths in some range. (handle_store): Add an argument. (check_and_optimize_stmt): Pass an argument to handle_store. From-SVN: r277076
2019-10-16[arm] fix bootstrap failure due to uninitialized warningRichard Earnshaw2-1/+5
The Arm port is failing bootstrap because GCC is now warning about an unitialized array. The code is complex enough that I certainly can't be sure the compiler is wrong, so perhaps the best fix here is just to memset the entire array before use. * config/arm/arm.c (neon_valid_immediate): Clear bytes before use. From-SVN: r277073
2019-10-16mips.c (mips_expand_builtin_insn): Force the operands which correspond to ↵Mihailo Stojanovic4-0/+58
the same input-output register to have... * config/mips/mips.c (mips_expand_builtin_insn): Force the operands which correspond to the same input-output register to have the same pseudo assigned to them. * gcc.target/mips/msa-dpadd-dpsub.c: New test. From-SVN: r277071
2019-10-16find_partition_fixes: remove unused bbs_in_cold_partition variableIlya Leoshkevich2-2/+4
gcc/ChangeLog: 2019-10-16 Ilya Leoshkevich <iii@linux.ibm.com> * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition. From-SVN: r277070
2019-10-16[AArch64] Fix symbol offset limitWilco Dijkstra5-22/+37
In aarch64_classify_symbol symbols are allowed large offsets on relocations. This means the offset can use all of the +/-4GB offset, leaving no offset available for the symbol itself. This results in relocation overflow and link-time errors for simple expressions like &global_array + 0xffffff00. To avoid this, unless the offset_within_block_p is true, limit the offset to +/-1MB so that the symbol needs to be within a 3.9GB offset from its references. For the tiny code model use a 64KB offset, allowing most of the 1MB range for code/data between the symbol and its references. gcc/ * config/aarch64/aarch64.c (aarch64_classify_symbol): Apply reasonable limit to symbol offsets. testsuite/ * gcc.target/aarch64/symbol-range.c: Improve testcase. * gcc.target/aarch64/symbol-range-tiny.c: Likewise. From-SVN: r277068
2019-10-16tree-vect-loop.c (vect_valid_reduction_input_p): Remove.Richard Biener6-96/+138
2019-10-16 Richard Biener <rguenther@suse.de> * tree-vect-loop.c (vect_valid_reduction_input_p): Remove. (vect_is_simple_reduction): Delay checking to vectorizable_reduction and relax the checking. (vectorizable_reduction): Check we have a simple use. Check for bogus condition reductions. * tree-vect-stmts.c (vect_transform_stmt): Make sure we are looking at the last stmt in a pattern sequence when filling in backedge PHI values. * gcc.dg/vect/vect-cond-reduc-3.c: New testcase. * gcc.dg/vect/vect-cond-reduc-4.c: Likewise. From-SVN: r277067
2019-10-16In PR70010, a function is marked with target(no-vsx) to disable VSX code ↵Peter Bergner8-12/+122
generation. In PR70010, a function is marked with target(no-vsx) to disable VSX code generation. To avoid VSX code generation, this function should not be inlined into VSX function. To fix the bug, in the current logic when checking whether the caller's ISA flags supports the callee's ISA flags, we just need to add a test that enforces that the caller's ISA flags match exactly the callee's flags, for those flags that were explicitly set in the callee. If caller without target attribute then using options from command line. gcc/ 2019-10-16 Peter Bergner <bergner@linux.ibm.com> Jiufu Guo <guojiufu@linux.ibm.com> PR target/70010 * config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if the callee explicitly disables some isa_flags the caller is using. gcc.testsuite/ 2019-10-16 Peter Bergner <bergner@linux.ibm.com> Jiufu Guo <guojiufu@linux.ibm.com> PR target/70010 * gcc.target/powerpc/pr70010.c: New test. * gcc.target/powerpc/pr70010-1.c: New test. * gcc.target/powerpc/pr70010-2.c: New test. * gcc.target/powerpc/pr70010-3.c: New test. * gcc.target/powerpc/pr70010-4.c: New test. Co-Authored-By: Jiufu Guo <guojiufu@linux.ibm.com> From-SVN: r277065
2019-10-16Assert for POINTER_TYPE_P in expr_callee_abiRichard Sandiford2-8/+6
2019-10-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * function-abi.cc (expr_callee_abi): Assert for POINTER_TYPE_P. From-SVN: r277063
2019-10-16[AArch64] Add partial SVE vector modesRichard Sandiford4-33/+144
This patch adds extra vector modes that represent a half, quarter or eighth of what an SVE vector can hold. This is useful for describing the memory vector involved in an extending load or truncating store. It might also be useful in future for representing "unpacked" SVE registers, i.e. registers that contain values in the low bits of a wider containing element. The new modes could have the same width as an Advanced SIMD mode for certain -msve-vector-bits=N options, so we need to ensure that they come later in the mode list and that Advanced SIMD modes always "win". 2019-10-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * genmodes.c (mode_data::order): New field. (blank_mode): Update accordingly. (VECTOR_MODES_WITH_PREFIX): Add an order parameter. (make_vector_modes): Likewise. (VECTOR_MODES): Update use accordingly. (cmp_modes): Sort by the new order field ahead of sorting by size. * config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI) (VNx4QI, VNx4HI, VNx8QI): New partial vector modes. * config/aarch64/aarch64.c (VEC_PARTIAL): New flag value. (aarch64_classify_vector_mode): Handle the new partial modes. (aarch64_vl_bytes): New function. (aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR when counting the number of registers in an SVE mode. (aarch64_class_max_nregs): Likewise. (aarch64_hard_regno_mode_ok): Don't allow partial vectors in registers yet. (aarch64_classify_address): Treat partial vectors analogously to full vectors. (aarch64_print_address_internal): Consolidate the printing of MUL VL addresses, using aarch64_vl_bytes as the number of bytes represented by "VL". (aarch64_vector_mode_supported_p): Reject partial vector modes. From-SVN: r277062
2019-10-16[AArch64] Improve poly_int handling in aarch64_layout_frameRichard Sandiford2-4/+11
I'd used known_lt when converting these conditions to poly_int, but on reflection that was a bad choice. The code isn't just doing a range check; it specifically needs constants that will fit in a certain encoding. 2019-10-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_layout_frame): Use is_constant rather than known_lt when choosing frame layouts. From-SVN: r277061
2019-10-16[AArch64] Add an assert to aarch64_layout_frameRichard Sandiford2-2/+14
This patch adds an assert that all the individual *_adjust allocations add up to the full frame size. With that safety net, it seemed slightly clearer to use crtl->outgoing_args_size as the final adjustment where appropriate, to match what's used in the comments. This is a bit overkill on its own, but I need to add more cases for SVE. 2019-10-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_layout_frame): Assert that all the adjustments add up to the full frame size. Use crtl->outgoing_args_size directly as the final adjustment where appropriate. From-SVN: r277060
2019-10-16[AArch64] Use frame reference in aarch64_layout_frameRichard Sandiford2-60/+58
Using the full path "cfun->machine->frame" in aarch64_layout_frame led to awkward formatting in some follow-on patches, so it seemed worth using a local reference instead. 2019-10-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_layout_frame): Use a local "frame" reference instead of always referring directly to "cfun->machine->frame". From-SVN: r277059
2019-10-16re PR tree-optimization/92119 (ICE: SIGSEGV in contains_struct_check ↵Richard Biener2-1/+8
(tree.h:3380) with -Os -fno-tree-dce -fno-tree-dse -ftree-slp-vectorize) 2019-10-16 Richard Biener <rguenther@suse.de> PR tree-optimization/92119 * tree-vect-patterns.c (vect_recog_rotate_pattern): Guard against missing bswap lhs. From-SVN: r277057
2019-10-16Deal with incoming POLY_INT_CST ranges (PR92033)Richard Sandiford4-0/+62
This patch makes value_range_base::set convert POLY_INT_CST bounds into the worst-case INTEGER_CST bounds. The main case in which this gives useful ranges is a lower bound of A + B * X becoming A when B >= 0. E.g.: [32 + 16X, 100] -> [32, 100] [32 + 16X, 32 + 16X] -> [32, MAX] But the same thing can be useful for the upper bound with negative X coefficients. 2019-10-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ PR middle-end/92033 * poly-int.h (constant_lower_bound_with_limit): New function. (constant_upper_bound_with_limit): Likewise. * doc/poly-int.texi: Document them. * tree-vrp.c (value_range_base::set): Convert POLY_INT_CST bounds into the worst-case INTEGER_CST bounds. From-SVN: r277056
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