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gcc/fortran/ChangeLog:
* dump-parse-tree.c (show_omp_namelist): Handle depobj + mutexinoutset
in the depend clause.
(show_omp_clauses, show_omp_node, show_code_node): Handle depobj.
* gfortran.h (enum gfc_statement): Add ST_OMP_DEPOBJ.
(enum gfc_omp_depend_op): Add OMP_DEPEND_UNSET,
OMP_DEPEND_MUTEXINOUTSET and OMP_DEPEND_DEPOBJ.
(gfc_omp_clauses): Add destroy, depobj_update and depobj.
(enum gfc_exec_op): Add EXEC_OMP_DEPOBJ
* match.h (gfc_match_omp_depobj): Match 'omp depobj'.
* openmp.c (gfc_match_omp_clauses): Add depobj + mutexinoutset
to depend clause.
(gfc_match_omp_depobj, resolve_omp_clauses, gfc_resolve_omp_directive):
Handle 'omp depobj'.
* parse.c (decode_omp_directive, next_statement, gfc_ascii_statement):
Likewise.
* resolve.c (gfc_resolve_code): Likewise.
* st.c (gfc_free_statement): Likewise.
* trans-openmp.c (gfc_trans_omp_clauses): Handle depobj + mutexinoutset
in the depend clause.
(gfc_trans_omp_depobj, gfc_trans_omp_directive): Handle EXEC_OMP_DEPOBJ.
* trans.c (trans_code): Likewise.
libgomp/ChangeLog:
* testsuite/libgomp.fortran/depobj-1.f90: New test.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/depobj-1.f90: New test.
* gfortran.dg/gomp/depobj-2.f90: New test.
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The test fails for targets with V4QImode support which is the case for
IBM Z.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr71264.c: Xfail on IBM Z due to V4QImode support.
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This removes pedantic_non_lvalue_loc which doesn't do what it says
since quite some time in favor of what it actually does and where
that's not a duplicate (protected_set_expr_location_unshare).
2021-04-19 Richard Biener <rguenther@suse.de>
* fold-const.c (pedantic_non_lvalue_loc): Remove.
(fold_binary_loc): Adjust.
(fold_ternary_loc): Likewise.
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switch_to_section warns if we try to output a retain decl in a
section without a retain flag, or if we try to output a non-retain
decl in a section with a retain flag. However, the warning only
applied if we were trying to “switch” to the current section.
This works if all decls that use a section are generated consecutively,
but not if there is an unrelated decl in between.
This patch makes the check unconditional, but suppresses the warning
if we're writing the section's named.decl (i.e. the decl from which
the section name and original flags were derived).
Also, the warning didn't fire for -fsection-anchors, for two reasons:
we allowed retain and non-retain decls to be put into the same block,
and we didn't pass a decl to switch_to_section.
Although these are arguably separate bugs, it isn't easy to fix them
independently without temporarily regressing -fsection-anchor targets.
gcc/
PR middle-end/100130
* varasm.c (get_block_for_decl): Make sure that any use of the
retain attribute matches the section's retain flag.
(switch_to_section): Check for retain mismatches even when
changing sections, but do not warn if the given decl is the
section's named.decl.
(output_object_block): Pass the first decl in the block (if any)
to switch_to_section.
gcc/testsuite/
PR middle-end/100130
* c-c++-common/attr-retain-10.c: New test.
* c-c++-common/attr-retain-11.c: Likewise.
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On IBM Z the aliasing stores are realized through one element vector
instructions, if no cost model for vectorization is used which is the
default according to vect.exp. Fixed by changing the number of times
the pattern must be found in the dump.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-39.c: Change number of times the pattern
must match for target IBM Z only.
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* gcc.pot: Regenerate.
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Use crc32 target option for CRC32 intrinsics to support CRC32 intrinsics
without enabling SSE vector instructions.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__CRC32__ for -mcrc32.
* config/i386/i386-options.c (ix86_option_override_internal):
Enable crc32 instruction for -msse4.2.
* config/i386/i386.md (sse4_2_crc32<mode>): Remove TARGET_SSE4_2
check.
(sse4_2_crc32di): Likewise.
* config/i386/ia32intrin.h: Use crc32 target option for CRC32
intrinsics.
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There are various non-IBM CPUs with isel as well, so it is easiest if we
just don't consider that flag here (it is not needed).
2021-04-20 Segher Boessenkool <segher@kernel.crashing.org>
PR target/100108
* config/rs6000/rs6000.c (rs6000_machine_from_flags): Do not consider
OPTION_MASK_ISEL.
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Another construct we need to look inside.
gcc/cp/ChangeLog:
PR c++/100109
* pt.c (find_parameter_packs_r): Look into enum initializers.
gcc/testsuite/ChangeLog:
PR c++/100109
* g++.dg/cpp0x/lambda/lambda-variadic14.C: New test.
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gcc/ChangeLog:
* doc/invoke.texi: Fix typo.
* params.opt: Likewise.
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gcc/ada/ChangeLog:
* gnatvsn.ads: Bump Library_Version to 12.
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gcc/ChangeLog:
* doc/invoke.texi: Document new param.
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2021-04-20 Jakub Jelinek <jakub@redhat.com>
* BASE-VER: Set to 11.0.0.
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Depending on whether GCC is configured using --with-mode=zarch or not,
for the 31bit target instructions are generated either for ESA or
z/Architecture. For the sake of simplicity and robustness test only for
the latter by adding manually option -mzarch.
gcc/testsuite/ChangeLog:
* gcc.target/s390/zero-scratch-regs-1.c: Force test to run for
z/Architecture only.
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2021-04-20 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/100110
* trans-decl.c (gfc_get_symbol_decl): Replace test for host
association with a check that the current and symbol namespaces
are the same.
gcc/testsuite/
PR fortran/100110
* gfortran.dg/pdt_31.f03: New test.
* gfortran.dg/pdt_26.f03: Reduce 'builtin_malloc' count from 9
to 8.
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This is an ICE-on-invalid, but I keep seeing it when reducing code so
I'd like to fix it. We crash on
template <typename> void forward() {
concept C = true;
}
which breaks two requirements:
[temp.concept]/1: A concept is a template ...
[temp.concept]/3: A concept-definition shall inhabit a namespace scope.
This patch adds a test that exercises broken code and fixes the ICE
by checking that a concept-definition is defined at namespace scope.
gcc/cp/ChangeLog:
PR c++/97536
* decl.c (grokvardecl): Given an error when a concept is not defined
at namespace scope.
gcc/testsuite/ChangeLog:
PR c++/97536
* g++.dg/concepts/diagnostic16.C: New test.
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Limit how many logical expressions GORI will look back through when
evaluating outgoing edge range.
PR tree-optimization/100081
* gimple-range-cache.h (ranger_cache): Inherit from gori_compute
rather than gori_compute_cache.
* gimple-range-gori.cc (is_gimple_logical_p): Move to top of file.
(range_def_chain::m_logical_depth): New member.
(range_def_chain::range_def_chain): Initialize m_logical_depth.
(range_def_chain::get_def_chain): Don't build defchains through more
than LOGICAL_LIMIT logical expressions.
* params.opt (param_ranger_logical_depth): New.
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The percentage character was being confused for a format specifier in
pp_format(), whilst the backtick character was confused for the
beginning of a quoted string in expand_d_format().
Both are now properly escaped to avoid the ICE.
gcc/d/ChangeLog:
PR d/98457
* d-diagnostic.cc (expand_d_format): Handle escaped backticks.
(escape_d_format): New funtion.
(verror): Call escape_d_format on prefixing strings.
(vdeprecation): Likewise.
gcc/testsuite/ChangeLog:
PR d/98457
* gdc.dg/pr98457.d: New test.
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This is a partial revert of r11-8168. The overall purpose of the
commit is retained (to fix a bogus warning when -mfpu=<not-auto> is
used in combination with eg -mcpu=neoverse-v1), but it removes the
hunk that changed the subsequent feature bits for features of a
simd/fp unit that cannot be described by -mfpu. While I still think
that is the correct direction of travel, it's somewhat disruptive and
not appropriate for late stage4. I'll revisit for gcc-12.
gcc:
PR target/100067
* config/arm/arm.c (arm_configure_build_target): Do not strip
extended FPU/SIMD feature bits from the target ISA when -mfpu
is specified (partial revert of r11-8168).
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The testcase is endianness dependent and works only on little-endian.
2021-04-19 Christophe Lyon <christophe.lyon@linaro.org>
PR target/100075
gcc/testsuite/
* gcc.target/aarch64/pr100075.c: Add aarch64_little_endian
effective target.
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This reverts a s/column_offset/column/ change in the fix for PR99446.
2021-04-19 Richard Biener <rguenther@suse.de>
PR preprocessor/100142
libcpp/
* line-map.c (linemap_position_for_loc_and_offset): Revert
unintended s/column_offset/column/ change.
gcc/testsuite/
* gcc.dg/pr100142.c: New testcase.
* g++.dg/diagnostic/pr72803.C: Revert last change.
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This configuration knob is temporary, and isn't really meant to be exposed to
users.
gcc/
* params.opt (-param=openacc-kernels=): Add.
* omp-oacc-kernels-decompose.cc
(pass_omp_oacc_kernels_decompose::gate): Use it.
* doc/invoke.texi (-fopenacc-kernels=@var{mode}): Move...
(--param): ... here, 'openacc-kernels'.
gcc/c-family/
* c.opt (fopenacc-kernels=): Remove.
gcc/fortran/
* lang.opt (fopenacc-kernels=): Remove.
gcc/testsuite/
* c-c++-common/goacc/if-clause-2.c: '-fopenacc-kernels=[...]' ->
'--param=openacc-kernels=[...]'.
* c-c++-common/goacc/kernels-decompose-1.c: Likewise.
* c-c++-common/goacc/kernels-decompose-2.c: Likewise.
* c-c++-common/goacc/kernels-decompose-ice-1.c: Likewise.
* c-c++-common/goacc/kernels-decompose-ice-2.c: Likewise.
* gfortran.dg/goacc/kernels-decompose-1.f95: Likewise.
* gfortran.dg/goacc/kernels-decompose-2.f95: Likewise.
* gfortran.dg/goacc/kernels-tree.f95: Likewise.
libgomp/
* testsuite/libgomp.oacc-c-c++-common/declare-vla-kernels-decompose-ice-1.c:
'-fopenacc-kernels=[...]' -> '--param=openacc-kernels=[...]'.
* testsuite/libgomp.oacc-c-c++-common/declare-vla-kernels-decompose.c:
Likewise.
* testsuite/libgomp.oacc-c-c++-common/kernels-decompose-1.c:
Likewise.
* testsuite/libgomp.oacc-fortran/pr94358-1.f90: Likewise.
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gcc/ChangeLog:
PR c/100143
* gengtype.c (finish_root_table): Align function arguments
in between declaration and definition.
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Since GCC 8, the -freorder-blocks-and-partition pass can split a function
into hot and cold parts, thus generating 2 FDEs for a single function in
DWARF for exception purposes and doing an equivalent trick for Windows SEH.
Now the Windows system unwinder does not support arbitrarily large frames
and there is even a hard limit on the encoding of the CFI, which changes
the stack allocation strategy when it is topped and which must be reflected
everywhere.
gcc/
* config/i386/winnt.c (i386_pe_seh_cold_init): Properly deal with
frames larger than the SEH maximum frame size.
gcc/testsuite/
* gnat.dg/opt92.adb: New test.
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If the register named in an existing REG_UNUSED note dies somewhere
between where the note used to be and I3, we should just drop it.
2021-04-21 Segher Boessenkool <segher@kernel.crashing.org>
PR rtl-optimization/99927
* combine.c (distribute_notes) [REG_UNUSED]: If the register already
is dead, just drop it.
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On s390* the only missing part for the mentioned testcases was a load of
a double floating-point zero via a move (in particular for quite old
machines) which was added in commit 46c47420a5fefd4d9d02b0db347235dd74e20fb2.
Common code implementation is sufficient in order to clear volatile
GPRs, FPRs, and VRs. Access registers a0 and a1 are nonvolatile and not
cleared. Therefore, target hook TARGET_ZERO_CALL_USED_REGS is not
implemented for s390*.
Added a target specific test in order to ensure that all call clobbered
GPRs, FPRs, and VRs are zeroed and all call saved registers are kept.
gcc/testsuite/ChangeLog:
* c-c++-common/zero-scratch-regs-8.c: Enable on s390*.
* c-c++-common/zero-scratch-regs-9.c: Likewise.
* c-c++-common/zero-scratch-regs-10.c: Likewise.
* c-c++-common/zero-scratch-regs-11.c: Likewise.
* gcc.target/s390/zero-scratch-regs-1.c: New test.
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Following up on the fix for PR99914, when testing on MinGW, it was found
not to support weak in the same way as on ELF or Mach-O targets.
So the linkage has been reverted back to COMDAT for that target, however
in order to properly support overriding functions and variables, all
declarations with external linkage must be put on COMDAT. For this a
new target hook has been added to control the behavior.
gcc/ChangeLog:
PR d/99914
* config/i386/winnt-d.c (TARGET_D_TEMPLATES_ALWAYS_COMDAT): Define.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in (D language and ABI): Add @hook for
TARGET_D_TEMPLATES_ALWAYS_COMDAT.
gcc/d/ChangeLog:
PR d/99914
* d-target.def (d_templates_always_comdat): New hook.
* d-tree.h (mark_needed): Remove prototype.
* decl.cc: Include d-target.h.
(mark_needed): Rename to...
(d_mark_needed): ...this. Make static.
(set_linkage_for_decl): Put variables in comdat if
d_templates_always_comdat.
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Following on from adding TARGET_D_REGISTER_OS_TARGET_INFO, this adds the
required handlers to implement `__traits(getTargetInfo, "objectFormat")'
for all platforms that have D support files.
Some back-ends (i386, rs6000, and pa) have some awarenes of the what
object format they are compiling for, so new getTargetInfo handlers have
been have added both to those back-ends as well as platform-specific
target files to override the default in the D front-end.
gcc/ChangeLog:
* config/darwin-d.c (darwin_d_handle_target_object_format): New
function.
(darwin_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
* config/dragonfly-d.c (dragonfly_d_handle_target_object_format): New
function.
(dragonfly_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
* config/freebsd-d.c (freebsd_d_handle_target_object_format): New
function.
(freebsd_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
* config/glibc-d.c (glibc_d_handle_target_object_format): New
function.
(glibc_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
* config/i386/i386-d.c (ix86_d_handle_target_object_format): New
function.
(ix86_d_register_target_info): Add ix86_d_handle_target_object_format
as handler for objectFormat key.
* config/i386/winnt-d.c (winnt_d_handle_target_object_format): New
function.
(winnt_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
* config/netbsd-d.c (netbsd_d_handle_target_object_format): New
function.
(netbsd_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
* config/openbsd-d.c (openbsd_d_handle_target_object_format): New
function.
(openbsd_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
* config/pa/pa-d.c (pa_d_handle_target_object_format): New function.
(pa_d_register_target_info): Add pa_d_handle_target_object_format as
handler for objectFormat key.
* config/rs6000/rs6000-d.c (rs6000_d_handle_target_object_format): New
function.
(rs6000_d_register_target_info): Add
rs6000_d_handle_target_object_format as handler for objectFormat key.
* config/sol2-d.c (solaris_d_handle_target_object_format): New
function.
(solaris_d_register_target_info): New function.
(TARGET_D_REGISTER_OS_TARGET_INFO): Define.
gcc/d/ChangeLog:
* d-target.cc (d_handle_target_object_format): New function.
(d_language_target_info): Add d_handle_target_object_format as handler
for objectFormat key.
(Target::getTargetInfo): Continue if handler returned NULL_TREE.
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gcc/fortran/ChangeLog:
PR fortran/100094
* trans-array.c (gfc_trans_deferred_array): Add code to initialize
pointers and allocatables with correct TKR parameters.
gcc/testsuite/ChangeLog:
PR fortran/100094
* gfortran.dg/PR100094.f90: New test.
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The previous change to this testcase missed the fact that the data may
be accessed via an anchor, depending on the optimization level,
leading to false failures.
This patch restricts matching to upper16:lower16 followed by
non-spaces, followed by +4 (in f4) or +320 (in f5).
Using '.*' instead of '[^ \]' would match accross the whole assembly
file, which is not what we want, hence the limitation with spaces.
2021-04-16 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
PR target/96770
* gcc.target/arm/pure-code/pr96770.c: Fix scan-assembler-times
with movt/movw.
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As the following testcase shows, we emit a -Wpsabi note about argument
passing change since GCC 9, but in reality the ABI didn't change.
The alignment is 8 bits in GCC < 9 and 32 bits in GCC >= 9 and
the aarch64_function_arg_alignment returns in that case:
return MIN (MAX (alignment, PARM_BOUNDARY), STACK_BOUNDARY);
so when both the old and new alignment are smaller or equal to PARM_BOUNDARY
(or both are larger than STACK_BOUNDARY, just in theory), even when the new
one is bigger, it doesn't change the argument passing.
So, the following patch changes aarch64_function_arg_alignment to tell the
callers the exact old alignmentm so that they can test it if needed.
The other aarch64_function_arg_alignment callers either check the
alignment for equality against 16-byte alignment (when old alignment was
smaller than that and the new one is 16-byte, we want to emit -Wpsabi
in all the cases) or the va_arg case which I think is ok now too.
2021-04-16 Jakub Jelinek <jakub@redhat.com>
PR target/91710
* config/aarch64/aarch64.c (aarch64_function_arg_alignment): Change
abi_break argument from bool * to unsigned *, store there the pre-GCC 9
alignment.
(aarch64_layout_arg, aarch64_gimplify_va_arg_expr): Adjust callers.
(aarch64_function_arg_regno_p): Likewise. Only emit -Wpsabi note if
the old and new alignment after applying MIN/MAX to it is different.
* gcc.target/aarch64/pr91710.c: New test.
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gcc/fortran/ChangeLog:
PR fortran/100018
* resolve.c: Add association check before de-referencing pointer.
gcc/testsuite/ChangeLog:
PR fortran/100018
* gfortran.dg/PR10018.f90: New test.
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The attached testcase generates the following paradoxical subregs when creating
the predicates.
(insn 22 21 23 2 (set (reg:VNx8BI 100)
(subreg:VNx8BI (reg:VNx2BI 103) 0))
(expr_list:REG_EQUAL (const_vector:VNx8BI [
(const_int 1 [0x1])
(const_int 0 [0])
(const_int 1 [0x1])
(const_int 0 [0]) repeated x5
])
(nil)))
and
(insn 15 14 16 2 (set (reg:VNx8BI 96)
(subreg:VNx8BI (reg:VNx2BI 99) 0))
(expr_list:REG_EQUAL (const_vector:VNx8BI [
(const_int 1 [0x1])
(const_int 0 [0]) repeated x7
])
(nil)))
This causes CSE to incorrectly think that the two predicates are equal because
some of the significant bits get ignored due to the subreg.
The attached patch instead makes it so it always looks at all 16-bits of the
predicate, but in turn means we need to generate a TRN that matches the expected
result mode. In effect in RTL we keep the mode as VNx16BI but during codegen
re-interpret them as the mode the predicate instruction wanted:
(insn 10 9 11 2 (set (reg:VNx8BI 96)
(subreg:VNx8BI (reg:VNx16BI 99) 0))
(expr_list:REG_EQUAL (const_vector:VNx8BI [
(const_int 1 [0x1])
(const_int 0 [0]) repeated x7
])
(nil)))
Which needed correction to the TRN pattern. A new TRN1_CONV unspec is
introduced which allows one to keep the arguments as VNx16BI but encode the
instruction as a type of the last operand.
(insn 9 8 10 2 (set (reg:VNx16BI 99)
(unspec:VNx16BI [
(reg:VNx16BI 97)
(reg:VNx16BI 98)
(reg:VNx2BI 100)
] UNSPEC_TRN1_CONV))
(nil))
This allows us remove all the paradoxical subregs and end up with
(insn 16 15 17 2 (set (reg:VNx8BI 101)
(subreg:VNx8BI (reg:VNx16BI 104) 0))
(expr_list:REG_EQUAL (const_vector:VNx8BI [
(const_int 1 [0x1])
(const_int 0 [0])
(const_int 1 [0x1])
(const_int 0 [0]) repeated x5
])
(nil)))
gcc/ChangeLog:
PR target/100048
* config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>): New.
* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_trn): Use new
TRN optab.
* config/aarch64/iterators.md (UNSPEC_TRN1_CONV): New.
gcc/testsuite/ChangeLog:
PR target/100048
* gcc.target/aarch64/sve/pr100048.c: New test.
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In r11-6895 handling of empty bases has been fixed such that non-lval
stores of empty classes are not added when the type of *valp doesn't
match the type of the initializer, but as this testcase shows it is
done only when *valp is non-NULL. If it is NULL, we still shouldn't
add empty class constructors if the type of the constructor elt *valp
points to doesn't match.
2021-04-16 Jakub Jelinek <jakub@redhat.com>
PR c++/100111
* constexpr.c (cxx_eval_store_expression): Don't add CONSTRUCTORs
for empty classes into *valp when types don't match even when *valp
is NULL.
* g++.dg/cpp0x/constexpr-100111.C: New test.
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The standard for many Power vector interfaces is now the recently
published Power Vector Intrinsic Programming Reference. Reference
that document for the relevant interfaces, and remove redundant
information from the GCC user's manual.
2021-04-16 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Revise
this section and its subsections.
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Here we ICE when compiling this code in C++20, because we're trying to
slam a 'typename' after the ->. The cp_parser_template_id call just
before the spot I'm changing parsed A::template A<int> as a BASELINK
that contains a constructor, but make_typename_type crashes on that.
This patch makes make_typename_type more robust instead of checking
for is_overloaded_fn prior calling it.
gcc/cp/ChangeLog:
PR c++/99803
* decl.c (make_typename_type): Give an error and return when
name is is_overloaded_fn.
* parser.c (cp_parser_class_name): Don't check is_overloaded_fn
before calling make_typename_type.
gcc/testsuite/ChangeLog:
PR c++/99803
* g++.dg/cpp2a/typename14.C: Don't expect particular error
messages.
* g++.dg/cpp2a/typename19.C: New test.
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The gimplefe-40.c and gimplefe-41.c test cases require vect_* effective
targets even though they reside in gcc.dg. By default e.g.
DEFAULT_VECTCFLAGS which is used to add target-specific machine or build
flags is only applied in the ./vect subdirectory. Move these tests
there.
gcc/testsuite/ChangeLog:
* gcc.dg/gimplefe-40.c: Moved to...
* gcc.dg/vect/gimplefe-40.c: ...here.
* gcc.dg/gimplefe-41.c: Moved to...
* gcc.dg/vect/gimplefe-41.c: ...here.
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The interface of an intrinsic procedure is automatically explicit.
Do not write it to the module file to prevent wrong ambiguities on USE.
gcc/fortran/ChangeLog:
PR fortran/63797
* module.c (write_symtree): Do not write interface of intrinsic
procedure to module file for F2003 and newer.
gcc/testsuite/ChangeLog:
PR fortran/63797
* gfortran.dg/pr63797.f90: New test.
Co-authored-by: Paul Thomas <pault@gcc.gnu.org>
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For z10 and newer inner loops are completely unrolled which means store
motion is not applied. Reverting max-completely-peeled-insns to the
default value fixes these testcases.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr83403-1.c: Revert
max-completely-peeled-insns to the default value on IBM Z.
* gcc.dg/tree-ssa/pr83403-2.c: Likewise.
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Here, reduced_constant_expression_p is incorrectly returning true for a
partially initialized array CONSTRUCTOR (in C++20 mode) because when the
CONSTRUCTOR_NO_CLEARING flag is set, the predicate doesn't check that
the CONSTRUCTOR spans the entire array like it does for class CONSTRUCTORS.
This patch adds a dedicated loop for the array case that simultaneously
verifies the CONSTRUCTOR spans the entire array and is made up of valid
constant expressions.
gcc/cp/ChangeLog:
PR c++/99700
* constexpr.c (reduced_constant_expression_p): For array
CONSTRUCTORs, use a dedicated loop that additionally verifies
the CONSTRUCTOR spans the entire array.
gcc/testsuite/ChangeLog:
PR c++/99700
* g++.dg/cpp2a/constexpr-init21.C: New test.
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The testcase used to be compiled at -O2 by GCC8 and earlier to:
f1:
neg w1, w0, asr 16
and w1, w1, 65535
orr w0, w1, w0, lsl 16
ret
f2:
neg w1, w0
extr w0, w1, w0, 16
ret
but since GCC9 (r9-3594 for f1 and r9-6926 for f2) we compile it into:
f1:
mov w1, w0
sbfx x0, x1, 16, 16
neg w0, w0
bfi w0, w1, 16, 16
ret
f2:
neg w1, w0
sbfx x0, x0, 16, 16
bfi w0, w1, 16, 16
ret
instead, i.e. one insn longer each. With this patch we get:
f1:
mov w1, w0
neg w0, w1, asr 16
bfi w0, w1, 16, 16
ret
f2:
neg w1, w0
extr w0, w1, w0, 16
ret
i.e. identical f2 and same number of insns as in GCC8 in f1.
The combiner unfortunately doesn't try splitters when doing 2 -> 1
combination, so it can't be implemented as combine splitters, but
it could be implemented as define_insn_and_split if desirable.
2021-04-16 Jakub Jelinek <jakub@redhat.com>
PR target/100075
* config/aarch64/aarch64.md (*neg_asr_si2_extr, *extrsi5_insn_di): New
define_insn patterns.
* gcc.target/aarch64/pr100075.c: New test.
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This patch fixes a regression introduced by the rtl-ssa patches.
It was seen on HPPA but it might be latent elsewhere.
The problem is that the traditional way of expanding an untyped_call
is to emit sequences like:
(call (mem (symbol_ref "foo")))
(set (reg pseudo1) (reg result1))
...
(set (reg pseudon) (reg resultn))
The ABI specifies that result1..resultn are clobbered by the call but
nothing in the RTL indicates that result1..resultn are the results
of the call. Normally, using a clobbered value gives undefined results,
but in this case the results are well-defined and matter for correctness.
This seems like a niche case, so I think it would be better to mark
it explicitly rather than try to detect it heuristically.
Note that in expand_builtin_apply we already have an rtx_insn *,
so it doesn't matter whether we call emit_call_insn or emit_insn.
Calling emit_insn seems more natural now that the gen_* call
has been split out. It also matches later code in the function.
gcc/
PR rtl-optimization/98689
* reg-notes.def (UNTYPED_CALL): New note.
* combine.c (distribute_notes): Handle it.
* emit-rtl.c (try_split): Likewise.
* rtlanal.c (rtx_properties::try_to_add_insn): Likewise. Assume
that calls with the note implicitly set all return value registers.
* builtins.c (expand_builtin_apply): Add a REG_UNTYPED_CALL
to untyped_calls.
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This patch is a GCC 11 regression caused by the rtl-ssa code.
Normally we treat calls as containing a potential set of a global
register, but DF makes a sensible exception for the stack pointer:
if (i == STACK_POINTER_REGNUM)
/* The stack ptr is used (honorarily) by a CALL insn. */
df_ref_record (DF_REF_BASE, collection_rec, regno_reg_rtx[i],
NULL, bb, insn_info, DF_REF_REG_USE,
DF_REF_CALL_STACK_USAGE | flags);
else if (global_regs[i])
{
/* Calls to const functions cannot access any global registers and
calls to pure functions cannot set them. All other calls may
reference any of the global registers, so they are recorded as
used. */
The only DF definition of SP was therefore the one in the entry block.
However, the rtlanal.c rtx_properties code (wrongly) assumed that calls
also clobbered the global SP. This led to multiple definitions of SP
when we only expected one.
This patch tightens the rtlanal.c handling of global registers
to match the DF approach.
gcc/
PR rtl-optimization/99596
* rtlanal.c (rtx_properties::try_to_add_insn): Don't add global
register accesses for const calls. Assume that pure functions
can only read from global registers. Ignore cases in which
the stack pointer has been marked global.
gcc/testsuite/
PR rtl-optimization/99596
* gcc.target/arm/pr99596.c: New test.
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Commit r11-8168 changed the word ordering of a warning in order to
make the text more consistent. Unfortunately, it neglected to update
some filters in the testsuite that are intended to strip such warnings
when we try to partially override the user-supplied command-line
options.
This patch rectifies this and also fixes some patterns that were
incorrectly specified in the first place.
gcc/testsuite:
PR target/100067
* g++.target/arm/arm.exp (dg_runtest_extra_prunes): Update prune
template.
* gcc.target/arm/arm.exp (dg_runtest_extra_prunes): Likewise.
* g++.target/arm/mve.exp (dg_runtest_extra_prunes): Likewise. Fix
missing quotes around switch names.
* gcc.target/arm/mve/mve.exp: (dg_runtest_extra_prunes): Likewise.
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The following testcase ICEs because disabling of DCE means there are dead
stmts in the loop (though, in theory they could become dead only shortly
before if-conv through some optimization), ifcvt which goes through all
stmts in the loop if-converts them into .COND_DIV etc. internal fn calls
in the copy of the loop meant for vectorization only, the loop is
successfully vectorized but the particular .COND_* call is not because
it isn't a live statement and the scalar .COND_* remains in the IL until
expansion where it ICEs because these ifns only support vectors and not
scalars.
These ifns are similar to .MASK_{LOAD,STORE} in this behavior.
One possible fix could be to expand scalar versions of them during
expansion, basically undoing what if-conv did to create them, i.e.
expand them as the lhs = else; if (mask) { lhs = statement; } or so.
For .MASK_LOAD we have code to replace them in vect_transform_loop already
though (not needed for .MASK_STORE, as stores should be always live
and thus always vectorized), so this patch instead replaces .COND_*
similarly to .MASK_LOAD in that loop, with the small difference
that lhs = .MASK_LOAD (...); is replaced by lhs = 0; while
lhs = .COND_* (..., else_arg); is replaced by lhs = else_arg.
The statement must be dead, otherwise it would be vectorized, so I think
it is not a big deal we don't turn it back into multiple basic blocks etc.
(and it might be not possible to do that at that point).
2021-04-16 Jakub Jelinek <jakub@redhat.com>
PR target/99767
* tree-vect-loop.c (vect_transform_loop): Don't remove just
dead scalar .MASK_LOAD calls, but also dead .COND_* calls - replace
them by their last argument.
* gcc.target/aarch64/pr99767.c: New test.
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