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2019-11-14Support UTF-8 character constants for C2x.Joseph Myers11-1/+80
C2x adds u8'' character constants to C. This patch adds the corresponding GCC support. Most of the support was already present for C++ and just needed enabling for C2x. However, in C2x these constants have type unsigned char, which required corresponding adjustments in the compiler and the preprocessor to give them that type for C. For C, it seems clear to me that having type unsigned char means the constants are unsigned in the preprocessor (and thus treated as having type uintmax_t in #if conditionals), so this patch implements that. I included a conditional in the libcpp change to avoid affecting signedness for C++, but I'm not sure if in fact these constants should also be unsigned in the preprocessor for C++ in which case that !CPP_OPTION (pfile, cplusplus) conditional would not be needed. Bootstrapped with no regressions on x86_64-pc-linux-gnu. gcc/c: * c-parser.c (c_parser_postfix_expression) (c_parser_check_literal_zero): Handle CPP_UTF8CHAR. * gimple-parser.c (c_parser_gimple_postfix_expression): Likewise. gcc/c-family: * c-lex.c (lex_charconst): Make CPP_UTF8CHAR constants unsigned char for C. gcc/testsuite: * gcc.dg/c11-utf8char-1.c, gcc.dg/c2x-utf8char-1.c, gcc.dg/c2x-utf8char-2.c, gcc.dg/c2x-utf8char-3.c, gcc.dg/gnu2x-utf8char-1.c: New tests. libcpp: * charset.c (narrow_str_to_charconst): Make CPP_UTF8CHAR constants unsigned for C. * init.c (lang_defaults): Set utf8_char_literals for GNUC2X and STDC2X. From-SVN: r278265
2019-11-14Tweak gcc.dg/vect/bb-slp-4[01].c (PR92366)Richard Sandiford4-9/+64
gcc.dg/vect/bb-slp-40.c was failing on some targets because the explicit dg-options overrode things like -maltivec. This patch uses dg-additional-options instead. Also, it seems safer not to require exactly 1 instance of each message, since that depends on the target vector length. gcc.dg/vect/bb-slp-41.c contained invariant constructors that are vectorised on AArch64 (foo) and constructors that aren't (bar). This meant that the number of times we print "Found vectorizable constructor" depended on how many vector sizes we try, since we'd print it for each failed attempt. In foo, we create invariant { b[0], ... } and { b[1], ... }, and the test is making sure that the two separate invariant vectors can be fed from the same vector load at b. This is a different case from bb-slp-40.c, where the constructors are naturally separate. (The expected count is 4 rather than 2 because we can vectorise the epilogue too.) However, due to limitations in the loop vectoriser, we still do the addition of { b[0], ... } and { b[1], ... } in the loop. Hopefully that'll be fixed at some point, so this patch adds an alternative test that directly needs 4 separate invariant constructors. E.g. with Joel's SLP optimisation, the new test generates: ldr q4, [x1] dup v7.4s, v4.s[0] dup v6.4s, v4.s[1] dup v5.4s, v4.s[2] dup v4.4s, v4.s[3] instead of the somewhat bizarre: ldp s6, s5, [x1, 4] ldr s4, [x1, 12] ld1r {v7.4s}, [x1] dup v6.4s, v6.s[0] dup v5.4s, v5.s[0] dup v4.4s, v4.s[0] The patch then disables vectorisation of the original foo in bb-vect-slp-41.c, so that we get the same correctness testing for bar but don't need to test for specific counts. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/testsuite/ PR testsuite/92366 * gcc.dg/vect/bb-slp-40.c: Use dg-additional-options instead of dg-options. Remove expected counts. * gcc.dg/vect/bb-slp-41.c: Remove dg-options and explicit dg-do run. Suppress vectorization of foo. * gcc.dg/vect/bb-slp-42.c: New test. From-SVN: r278262
2019-11-14re PR tree-optimization/92506 (Wrong code with -fwrapv since r277979)Andrew MacLeod2-1/+9
2019-11-14 Andrew MacLeod <amacleod@redhat.com> PR tree-optimization/92506 * range-op.cc (range_operator::fold_range): Start with range undefined. (operator_abs::wi_fold): Fix wrong line copy... With wrapv, abs with overflow is varying. From-SVN: r278259
2019-11-14Remove range_intersect, range_invert, and range_union.Aldy Hernandez4-72/+34
From-SVN: r278258
2019-11-14Make flag_thread_jumps a gate of pass_jump_after_combineIlya Leoshkevich2-1/+9
This is a follow-up to https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00919.html (r278095). Dominance info is deleted even if we don't perform jump threading. Since the whole point of this pass is to perform jump threading (other cleanups are not valuable at this point), skip it completely when flag_thread_jumps is not set. gcc/ChangeLog: 2019-11-14 Ilya Leoshkevich <iii@linux.ibm.com> PR rtl-optimization/92430 * cfgcleanup.c (pass_jump_after_combine::gate): New function. (pass_jump_after_combine::execute): Perform jump threading unconditionally. From-SVN: r278254
2019-11-14Update the arm-*-vxworks* supportJerome Lambourg4-35/+38
2019-11-13 Jerome Lambourg <lambourg@adacore.com> Doug Rupp <rupp@adacore.com> Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc: Collapse the arm-vxworks entries into a single arm-wrs-vxworks7* one, bpabi based. Update the default cpu from arm8 to armv7-a * config/arm/vxworks.h (CC1_SPEC): Simplify, knowing that we always use ARM_UNWIND_INFO. (DWARF2_UNWIND_INFO): Remove redefinition. (ARM_TARGET2_DWARF_FORMAT): Likewise. (VXWORKS_PERSONALITY): Define, to "llvm". (VXWORKS_EXTRA_LIBS_RTP): Define, to "-lllvm". libgcc/ * config.host: Collapse the arm-vxworks entries into a single arm-wrs-vxworks7* one. * config/arm/unwind-arm-vxworks.c: Update comments. Provide __gnu_Unwind_Find_exidx and a weak dummy __cxa_type_match for kernel modules, to be overriden by libstdc++ when we link with it. Rely on externally provided __exidx_start/end. Co-Authored-By: Doug Rupp <rupp@adacore.com> Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r278253
2019-11-14Housekeeping on TARGET_OS_CPP_BUILTINS for arm-vxworksJerome Lambourg2-35/+42
2019-11-14 Jerome Lambourg <lambourg@adacore.com> * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Use _VX_CPU instead of CPU and handle arm_arch8. From-SVN: r278252
2019-11-14Base support for vxworks 7 on aarch64Doug Rupp4-0/+106
2019-11-14 Doug Rupp <rupp@adacore.com> Olivier Hainque <hainque@adacore.com> Jerome Lambourg <lambourg@adacore.com> gcc/ * config.gcc: Handle aarch64*-wrs-vxworks7*. * config/aarch64/aarch64-vxworks.h: New file. * config/aarch64/t-aarch64-vxworks: New file. libgcc/ * config.host: Handle aarch64*-wrs-vxworks7*. Co-Authored-By: Jerome Lambourg <lambourg@adacore.com> Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r278251
2019-11-14Introduce vxworks specific crtstuff supportJerome Lambourg3-10/+42
2019-11-06 Jerome Lambourg <lambourg@adacore.com> Olivier Hainque <hainque@adacore.com> libgcc/ * config/vxcrtstuff.c: New file. * config/t-vxcrtstuff: New Makefile fragment. * config.host: Append t-vxcrtstuff to the tmake_file list on all VxWorks ports using dwarf for table based EH. gcc/ * config/vx-common.h (USE_TM_CLONE_REGISTRY): Remove definition, pointless with a VxWorks specific version of crtstuff. (DWARF2_UNWIND_INFO): Conditionalize on !ARM_UNWIND_INFO. * config/vxworks.h (VX_CRTBEGIN_SPEC, VX_CRTEND_SPEC): New local macros, controlling the addition of vxworks specific crtstuff objects depending on the EH mechanism and kind of module being linked. (VXWORKS_STARTFILE_SPEC, VXWORKS_ENDFILE_SPEC): Use them. Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r278248
2019-11-14Common ground work for vxworks7 ports updatesPat Bernardi4-6/+66
2019-11-06 Pat Bernardi <bernardi@adacore.com> Jerome Lambourg <lambourg@adacore.com> Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc: Add comment to introduce the TARGET_VXWORKS commong macro definitions, conveying VXWORKS7 or 64bit general variations. Add a block to set gcc_cv_initfini_array unconditionally to "yes" for VxWorks7. config/vx-common.h (VXWORKS_CC1_SPEC): New macro, empty string by default. Update some comments. config/vxworks.h (VXWORKS_EXTRA_LIBS_RTP): New macro, empty by default, to be added the end of VXWORKS_LIBS_RTP. (VXWORKS_LIBS_RTP): Replace hardcoded part by VXWORKS_BASE_LIBS_RTP and append VXWORKS_EXTRA_LIBS_RTP, both of which specific ports may redefine. (VXWORKS_NET_LIBS_RTP): Account for VxWorks7 specificities. (VXWORKS_CC1_SPEC): Common base definition, with VxWorks7 variation to account for the now available TLS abilities. (TARGET_LIBC_HAS_FUNCTION): Account for VxWorks7 abilities. (VXWORKS_HAVE_TLS): Likewise. Co-Authored-By: Jerome Lambourg <lambourg@adacore.com> Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r278247
2019-11-14Consider building nodes from scalars in vect_slp_analyze_node_operationsRichard Sandiford4-0/+83
If the statements in an SLP node aren't similar enough to be vectorised, or aren't something the vectoriser has code to handle, the BB vectoriser tries building the vector from scalars instead. This patch does the same thing if we're able to build a viable-looking tree but fail later during the analysis phase, e.g. because the target doesn't support a particular vector operation. This is needed to avoid regressions with a later patch. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-slp.c (vect_contains_pattern_stmt_p): New function. (vect_slp_convert_to_external): Likewise. (vect_slp_analyze_node_operations): If analysis fails, try building the node from scalars instead. gcc/testsuite/ * gcc.dg/vect/bb-slp-div-2.c: New test. From-SVN: r278246
2019-11-14Vectorise conversions between differently-sized integer vectorsRichard Sandiford21-6/+280
This patch adds AArch64 patterns for converting between 64-bit and 128-bit integer vectors, and makes the vectoriser and expand pass use them. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-cfg.c (verify_gimple_assign_unary): Handle conversions between vector types. * tree-vect-stmts.c (vectorizable_conversion): Extend the non-widening and non-narrowing path to handle standard conversion codes, if the target supports them. * expr.c (convert_move): Try using the extend and truncate optabs for vectors. * optabs-tree.c (supportable_convert_operation): Likewise. * config/aarch64/iterators.md (Vnarroqw): New iterator. * config/aarch64/aarch64-simd.md (<optab><Vnarrowq><mode>2) (trunc<mode><Vnarrowq>2): New patterns. gcc/testsuite/ * gcc.dg/vect/bb-slp-pr69907.c: Do not expect BB vectorization to fail for aarch64 targets. * gcc.dg/vect/no-scevccp-outer-12.c: Expect the test to pass on aarch64 targets. * gcc.dg/vect/vect-double-reduc-5.c: Likewise. * gcc.dg/vect/vect-outer-4e.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_5.c: New test. * gcc.target/aarch64/vect_mixed_sizes_6.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_7.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_8.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_9.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_10.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_11.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_12.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_13.c: Likewise. From-SVN: r278245
2019-11-14Allow mixed vector sizes within a single vectorised stmtRichard Sandiford2-27/+37
Although a previous patch allowed mixed vector sizes within a vector region, we generally still required equal vector sizes within a vector stmt. Specifically, vect_get_vector_types_for_stmt computes two vector types: the vector type corresponding to STMT_VINFO_VECTYPE and the vector type that determines the minimum vectorisation factor for the stmt ("nunits_vectype"). It then required these two types to be the same size. There doesn't seem to be any need for that restriction though. AFAICT, all vectorizable_* functions either do their own compatibility checks or don't need to do them (because gimple guarantees that the scalar types are compatible). It should always be the case that nunits_vectype has at least as many elements as the other vectype, but that's something we can assert for. I couldn't resist a couple of other tweaks while there: - there's no need to compute nunits_vectype if its element type is the same as STMT_VINFO_VECTYPE's. - it's useful to distinguish the nunits_vectype from the main vectype in dump messages - when reusing the existing STMT_VINFO_VECTYPE, it's useful to say so in the dump, and say what the type is 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-stmts.c (vect_get_vector_types_for_stmt): Don't require vectype and nunits_vectype to have the same size; instead assert that nunits_vectype has at least as many elements as vectype. Don't compute a separate nunits_vectype if the scalar type is obviously the same as vectype's. Tweak dump messages. From-SVN: r278244
2019-11-14[AArch64] Support vectorising with multiple vector sizesRichard Sandiford12-6/+147
This patch makes the vectoriser try mixtures of 64-bit and 128-bit vector modes on AArch64. It fixes some existing XFAILs and allows kernel 24 from the Livermore Loops test to be vectorised (by using a mixture of V2DF and V2SI). 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_vectorize_related_mode): New function. (aarch64_autovectorize_vector_modes): Also add V4HImode and V2SImode. (TARGET_VECTORIZE_RELATED_MODE): Define. gcc/testsuite/ * gcc.dg/vect/vect-outer-4f.c: Expect the test to pass on aarch64 targets. * gcc.dg/vect/vect-outer-4g.c: Likewise. * gcc.dg/vect/vect-outer-4k.c: Likewise. * gcc.dg/vect/vect-outer-4l.c: Likewise. * gfortran.dg/vect/vect-8.f90: Expect kernel 24 to be vectorized for aarch64. * gcc.target/aarch64/vect_mixed_sizes_1.c: New test. * gcc.target/aarch64/vect_mixed_sizes_2.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_3.c: Likewise. * gcc.target/aarch64/vect_mixed_sizes_4.c: Likewise. From-SVN: r278243
2019-11-14Avoid retrying with the same vector modesRichard Sandiford5-0/+60
A later patch makes the AArch64 port add four entries to autovectorize_vector_modes. Each entry describes a different vector mode assignment for vector code that mixes 8-bit, 16-bit, 32-bit and 64-bit elements. But if (as usual) the vector code has fewer element sizes than that, we could end up trying the same combination of vector modes multiple times. This patch adds a check to prevent that. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vectorizer.h (vec_info::mode_set): New typedef. (vec_info::used_vector_mode): New member variable. (vect_chooses_same_modes_p): Declare. * tree-vect-stmts.c (get_vectype_for_scalar_type): Record each chosen vector mode in vec_info::used_vector_mode. (vect_chooses_same_modes_p): New function. * tree-vect-loop.c (vect_analyze_loop): Use it to avoid trying the same vector statements multiple times. * tree-vect-slp.c (vect_slp_bb_region): Likewise. From-SVN: r278242
2019-11-14Support vectorisation with mixed vector sizesRichard Sandiford7-38/+147
After previous patches, it's now possible to make the vectoriser support multiple vector sizes in the same vector region, using related_vector_mode to pick the right vector mode for a given element mode. No port yet takes advantage of this, but I have a follow-on patch for AArch64. This patch also seemed like a good opportunity to add some more dump messages: one to make it clear which vector size/mode was being used when analysis passed or failed, and another to say when we've decided to skip a redundant vector size/mode. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * machmode.h (opt_machine_mode::operator==): New function. (opt_machine_mode::operator!=): Likewise. * tree-vectorizer.h (vec_info::vector_mode): Update comment. (get_related_vectype_for_scalar_type): Delete. (get_vectype_for_scalar_type_and_size): Declare. * tree-vect-slp.c (vect_slp_bb_region): Print dump messages to say whether analysis passed or failed, and with what vector modes. Use related_vector_mode to check whether trying a particular vector mode would be redundant with the autodetected mode, and print a dump message if we decide to skip it. * tree-vect-loop.c (vect_analyze_loop): Likewise. (vect_create_epilog_for_reduction): Use get_related_vectype_for_scalar_type instead of get_vectype_for_scalar_type_and_size. * tree-vect-stmts.c (get_vectype_for_scalar_type_and_size): Replace with... (get_related_vectype_for_scalar_type): ...this new function. Take a starting/"prevailing" vector mode rather than a vector size. Take an optional nunits argument, with the same meaning as for related_vector_mode. Use related_vector_mode when not auto-detecting a mode, falling back to mode_for_vector if no target mode exists. (get_vectype_for_scalar_type): Update accordingly. (get_same_sized_vectype): Likewise. * tree-vectorizer.c (get_vec_alignment_for_array_type): Likewise. From-SVN: r278240
2019-11-14Require equal type sizes for vectorised callsRichard Sandiford2-0/+18
As explained in the comment, vectorizable_call needs more work to support mixtures of sizes. This avoids testsuite fallout for later SVE patches. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-stmts.c (vectorizable_call): Require the types to have the same size. From-SVN: r278239
2019-11-14Make less use of get_same_sized_vectypeRichard Sandiford2-13/+21
Some callers of get_same_sized_vectype were dealing with operands that are constant or defined externally, and so have no STMT_VINFO_VECTYPE available. Under the current model, using get_same_sized_vectype for that case is equivalent to using get_vectype_for_scalar_type, since get_vectype_for_scalar_type always returns vectors of the same size, once a size is fixed. Using get_vectype_for_scalar_type is arguably more obvious though: if we're using the same scalar type as we would for internal definitions, we should use the same vector type too. (Constant and external definitions sometimes let us change the original scalar type to a "nicer" scalar type, but that isn't what's happening here.) This is a prerequisite to supporting multiple vector sizes in the same vec_info. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-stmts.c (vectorizable_call): If an operand is constant or external, use get_vectype_for_scalar_type rather than get_same_sized_vectype to get its vector type. (vectorizable_conversion, vectorizable_shift): Likewise. (vectorizable_operation): Likewise. From-SVN: r278238
2019-11-14Replace vec_info::vector_size with vec_info::vector_modeRichard Sandiford9-41/+55
This patch replaces vec_info::vector_size with vec_info::vector_mode, but for now continues to use it as a way of specifying a single vector size. This makes it easier for later patches to use related_vector_mode instead. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vectorizer.h (vec_info::vector_size): Replace with... (vec_info::vector_mode): ...this new field. * tree-vect-loop.c (vect_update_vf_for_slp): Update accordingly. (vect_analyze_loop, vect_transform_loop): Likewise. * tree-vect-loop-manip.c (vect_do_peeling): Likewise. * tree-vect-slp.c (can_duplicate_and_interleave_p): Likewise. (vect_make_slp_decision, vect_slp_bb_region): Likewise. * tree-vect-stmts.c (get_vectype_for_scalar_type): Likewise. * tree-vectorizer.c (try_vectorize_loop_1): Likewise. gcc/testsuite/ * gcc.dg/vect/vect-tail-nomask-1.c: Update expected epilogue vectorization message. From-SVN: r278237
2019-11-14Replace autovectorize_vector_sizes with autovectorize_vector_modesRichard Sandiford17-122/+177
This is another patch in the series to remove the assumption that all modes involved in vectorisation have to be the same size. Rather than have the target provide a list of vector sizes, it makes the target provide a list of vector "approaches", with each approach represented by a mode. A later patch will pass this mode to targetm.vectorize.related_mode to get the vector mode for a given element mode. Until then, the modes simply act as an alternative way of specifying the vector size. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * target.h (vector_sizes, auto_vector_sizes): Delete. (vector_modes, auto_vector_modes): New typedefs. * target.def (autovectorize_vector_sizes): Replace with... (autovectorize_vector_modes): ...this new hook. * doc/tm.texi.in (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Replace with... (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): ...this new hook. * doc/tm.texi: Regenerate. * targhooks.h (default_autovectorize_vector_sizes): Delete. (default_autovectorize_vector_modes): New function. * targhooks.c (default_autovectorize_vector_sizes): Delete. (default_autovectorize_vector_modes): New function. * omp-general.c (omp_max_vf): Use autovectorize_vector_modes instead of autovectorize_vector_sizes. Use the number of units in the mode to calculate the maximum VF. * omp-low.c (omp_clause_aligned_alignment): Use autovectorize_vector_modes instead of autovectorize_vector_sizes. Use a loop based on related_mode to iterate through all supported vector modes for a given scalar mode. * optabs-query.c (can_vec_mask_load_store_p): Use autovectorize_vector_modes instead of autovectorize_vector_sizes. * tree-vect-loop.c (vect_analyze_loop, vect_transform_loop): Likewise. * tree-vect-slp.c (vect_slp_bb_region): Likewise. * config/aarch64/aarch64.c (aarch64_autovectorize_vector_sizes): Replace with... (aarch64_autovectorize_vector_modes): ...this new function. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Delete. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define. * config/arc/arc.c (arc_autovectorize_vector_sizes): Replace with... (arc_autovectorize_vector_modes): ...this new function. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Delete. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define. * config/arm/arm.c (arm_autovectorize_vector_sizes): Replace with... (arm_autovectorize_vector_modes): ...this new function. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Delete. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define. * config/i386/i386.c (ix86_autovectorize_vector_sizes): Replace with... (ix86_autovectorize_vector_modes): ...this new function. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Delete. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define. * config/mips/mips.c (mips_autovectorize_vector_sizes): Replace with... (mips_autovectorize_vector_modes): ...this new function. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Delete. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define. From-SVN: r278236
2019-11-14Use consistent compatibility checks in vectorizable_shiftRichard Sandiford2-5/+15
The validation phase of vectorizable_shift used TYPE_MODE to check whether the shift amount vector was compatible with the shifted vector: if ((op1_vectype == NULL_TREE || TYPE_MODE (op1_vectype) != TYPE_MODE (vectype)) && (!slp_node || SLP_TREE_DEF_TYPE (SLP_TREE_CHILDREN (slp_node)[1]) != vect_constant_def)) But the generation phase was stricter and required the element types to be equivalent: && !useless_type_conversion_p (TREE_TYPE (vectype), TREE_TYPE (op1))) This difference led to an ICE with a later patch. The first condition seems a bit too lax given that the function supports vect_worthwhile_without_simd_p, where two different vector types could have the same integer mode. But it seems too strict to reject signed shifts by unsigned amounts or unsigned shifts by signed amounts; verify_gimple_assign_binary is happy with those. This patch therefore goes for a middle ground of checking both TYPE_MODE and TYPE_VECTOR_SUBPARTS, using the same condition in both places. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-stmts.c (vectorizable_shift): Check the number of vector elements as well as the type mode when deciding whether an op1_vectype is compatible. Reuse the result of this check when generating vector statements. From-SVN: r278235
2019-11-14Use build_vector_type_for_mode in get_vectype_for_scalar_type_and_sizeRichard Sandiford2-5/+28
Except for one case, get_vectype_for_scalar_type_and_size calculates what the vector mode should be and then calls build_vector_type, which recomputes the mode from scratch. This patch makes it use build_vector_type_for_mode instead. The exception mentioned above is when preferred_simd_mode returns an integer mode, which it does if no appropriate vector mode exists. The integer mode in question is usually word_mode, although epiphany can return a doubleword mode in some cases. There's no guarantee that this integer mode is appropriate, since for example the scalar type could be a float. The traditional behaviour is therefore to use the integer mode to determine a size only, and leave mode_for_vector to pick the TYPE_MODE. (Note that it can actually end up picking a vector mode if the target defines a disabled vector mode. We therefore still need to check TYPE_MODE after building the type.) 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-stmts.c (get_vectype_for_scalar_type_and_size): If targetm.vectorize.preferred_simd_mode returns an integer mode, use mode_for_vector to decide what the vector type's mode should actually be. Use build_vector_type_for_mode instead of build_vector_type. From-SVN: r278234
2019-11-14Pass the data vector mode to get_mask_modeRichard Sandiford11-60/+62
This patch passes the data vector mode to get_mask_mode, rather than its size and nunits. This is a bit simpler and allows targets to distinguish between modes that happen to have the same size and number of elements. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * target.def (get_mask_mode): Take a vector mode itself as argument, instead of properties about the vector mode. * doc/tm.texi: Regenerate. * targhooks.h (default_get_mask_mode): Update to reflect new get_mode_mask interface. * targhooks.c (default_get_mask_mode): Likewise. Use related_int_vector_mode. * optabs-query.c (can_vec_mask_load_store_p): Update call to get_mask_mode. * tree-vect-stmts.c (check_load_store_masking): Likewise, checking first that the original mode really is a vector. * tree.c (build_truth_vector_type_for): Likewise. * config/aarch64/aarch64.c (aarch64_get_mask_mode): Update for new get_mode_mask interface. (aarch64_expand_sve_vcond): Update call accordingly. * config/gcn/gcn.c (gcn_vectorize_get_mask_mode): Update for new get_mode_mask interface. * config/i386/i386.c (ix86_get_mask_mode): Likewise. From-SVN: r278233
2019-11-14Remove build_{same_sized_,}truth_vector_typeRichard Sandiford17-54/+77
build_same_sized_truth_vector_type was confusingly named, since for SVE and AVX512 the returned vector isn't the same byte size (although it does have the same number of elements). What it really returns is the "truth" vector type for a given data vector type. The more general truth_type_for provides the same thing when passed a vector and IMO has a more descriptive name, so this patch replaces all uses of build_same_sized_truth_vector_type with that. It does the same for a call to build_truth_vector_type, leaving truth_type_for itself as the only remaining caller. It's then more natural to pass build_truth_vector_type the original vector type rather than its size and nunits, especially since the given size isn't the size of the returned vector. This in turn allows a future patch to simplify the interface of get_mask_mode. Doing this also fixes a bug in which truth_type_for would pass a size of zero for BLKmode vector types. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree.h (build_truth_vector_type): Delete. (build_same_sized_truth_vector_type): Likewise. * tree.c (build_truth_vector_type): Rename to... (build_truth_vector_type_for): ...this. Make static and take a vector type as argument. (truth_type_for): Update accordingly. (build_same_sized_truth_vector_type): Delete. * tree-vect-generic.c (expand_vector_divmod): Use truth_type_for instead of build_same_sized_truth_vector_type. * tree-vect-loop.c (vect_create_epilog_for_reduction): Likewise. (vect_record_loop_mask, vect_get_loop_mask): Likewise. * tree-vect-patterns.c (build_mask_conversion): Likeise. * tree-vect-slp.c (vect_get_constant_vectors): Likewise. * tree-vect-stmts.c (vect_get_vec_def_for_operand): Likewise. (vect_build_gather_load_calls, vectorizable_call): Likewise. (scan_store_can_perm_p, vectorizable_scan_store): Likewise. (vectorizable_store, vectorizable_condition): Likewise. (get_mask_type_for_scalar_type, get_same_sized_vectype): Likewise. (vect_get_mask_type_for_stmt): Use truth_type_for instead of build_truth_vector_type. * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred): Use truth_type_for instead of build_same_sized_truth_vector_type. * config/rs6000/rs6000-call.c (fold_build_vec_cmp): Likewise. gcc/c/ * c-typeck.c (build_conditional_expr): Use truth_type_for instead of build_same_sized_truth_vector_type. (build_vec_cmp): Likewise. gcc/cp/ * call.c (build_conditional_expr_1): Use truth_type_for instead of build_same_sized_truth_vector_type. * typeck.c (build_vec_cmp): Likewise. gcc/d/ * d-codegen.cc (build_boolop): Use truth_type_for instead of build_same_sized_truth_vector_type. From-SVN: r278232
2019-11-14Add build_truth_vector_type_for_modeRichard Sandiford8-54/+95
Callers of vect_halve_mask_nunits and vect_double_mask_nunits already know what mode the resulting vector type should have, so we might as well create the vector type directly with that mode, just like build_vector_type_for_mode lets us build normal vectors with a known mode. This avoids the current awkwardness of having to recompute the mode starting from vec_info::vector_size, which hard-codes the assumption that all vectors have to be the same size. A later patch gets rid of build_truth_vector_type and build_same_sized_truth_vector_type, so the net effect of the series is to reduce the number of type functions by one. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree.h (build_truth_vector_type_for_mode): Declare. * tree.c (build_truth_vector_type_for_mode): New function, split out from... (build_truth_vector_type): ...here. (build_opaque_vector_type): Fix head comment. * tree-vectorizer.h (supportable_narrowing_operation): Remove vec_info parameter. (vect_halve_mask_nunits): Replace vec_info parameter with the mode of the new vector. (vect_double_mask_nunits): Likewise. * tree-vect-loop.c (vect_halve_mask_nunits): Likewise. (vect_double_mask_nunits): Likewise. * tree-vect-loop-manip.c: Include insn-config.h, rtl.h and recog.h. (vect_maybe_permute_loop_masks): Remove vinfo parameter. Update call to vect_halve_mask_nunits, getting the required mode from the unpack patterns. (vect_set_loop_condition_masked): Update call accordingly. * tree-vect-stmts.c (supportable_narrowing_operation): Remove vec_info parameter and update call to vect_double_mask_nunits. (vectorizable_conversion): Update call accordingly. (simple_integer_narrowing): Likewise. Remove vec_info parameter. (vectorizable_call): Update call accordingly. (supportable_widening_operation): Update call to vect_halve_mask_nunits. * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use build_truth_vector_type_mode instead of build_truth_vector_type. From-SVN: r278231
2019-11-14Replace mode_for_int_vector with related_int_vector_modeRichard Sandiford6-37/+42
mode_for_int_vector, like mode_for_vector, can sometimes return an integer mode or an unsupported vector mode. But no callers are interested in that case, and only want supported vector modes. This patch therefore replaces mode_for_int_vector with related_int_vector_mode, which gives the target a chance to pick its preferred vector mode for the given element mode and size. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * machmode.h (mode_for_int_vector): Delete. (related_int_vector_mode): Declare. * stor-layout.c (mode_for_int_vector): Delete. (related_int_vector_mode): New function. * optabs.c (expand_vec_perm_1): Use related_int_vector_mode instead of mode_for_int_vector. (expand_vec_perm_const): Likewise. * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Likewise. (aarch64_evpc_sve_tbl): Likewise. * config/s390/s390.c (s390_expand_vec_compare_cc): Likewise. (s390_expand_vcond): Likewise. From-SVN: r278230
2019-11-14Add a targetm.vectorize.related_mode hookRichard Sandiford11-25/+126
This patch is the first of a series that tries to remove two assumptions: (1) that all vectors involved in vectorisation must be the same size (2) that there is only one vector mode for a given element mode and number of elements Relaxing (1) helps with targets that support multiple vector sizes or that require the number of elements to stay the same. E.g. if we're vectorising code that operates on narrow and wide elements, and the narrow elements use 64-bit vectors, then on AArch64 it would normally be better to use 128-bit vectors rather than pairs of 64-bit vectors for the wide elements. Relaxing (2) makes it possible for -msve-vector-bits=128 to produce fixed-length code for SVE. It also allows unpacked/half-size SVE vectors to work with -msve-vector-bits=256. The patch adds a new hook that targets can use to control how we move from one vector mode to another. The hook takes a starting vector mode, a new element mode, and (optionally) a new number of elements. The flexibility needed for (1) comes in when the number of elements isn't specified. All callers in this patch specify the number of elements, but a later vectoriser patch doesn't. 2019-11-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * target.def (related_mode): New hook. * doc/tm.texi.in (TARGET_VECTORIZE_RELATED_MODE): New hook. * doc/tm.texi: Regenerate. * targhooks.h (default_vectorize_related_mode): Declare. * targhooks.c (default_vectorize_related_mode): New function. * machmode.h (related_vector_mode): Declare. * stor-layout.c (related_vector_mode): New function. * expmed.c (extract_bit_field_1): Use it instead of mode_for_vector. * optabs-query.c (qimode_for_vec_perm): Likewise. * tree-vect-stmts.c (get_group_load_store_type): Likewise. (vectorizable_store, vectorizable_load): Likewise From-SVN: r278229
2019-11-14aarch64: Add testsuite checks for asm-flagRichard Henderson5-0/+170
Inspired by the tests in gcc.target/i386. Testing code generation, diagnostics, and execution. * gcc.target/aarch64/asm-flag-1.c: New test. * gcc.target/aarch64/asm-flag-3.c: New test. * gcc.target/aarch64/asm-flag-5.c: New test. * gcc.target/aarch64/asm-flag-6.c: New test. From-SVN: r278228
2019-11-14arm: Add testsuite checks for asm-flagRichard Henderson5-0/+173
Inspired by the tests in gcc.target/i386. Testing code generation, diagnostics, and execution. * gcc.target/arm/asm-flag-1.c: New test. * gcc.target/arm/asm-flag-3.c: New test. * gcc.target/arm/asm-flag-5.c: New test. * gcc.target/arm/asm-flag-6.c: New test. From-SVN: r278227
2019-11-14arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__Richard Henderson8-0/+201
Since all but a couple of lines is shared between the two targets, enable them both at once. * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Declare. * config/arm/aarch-common.c (arm_md_asm_adjust): New. * config/arm/arm-c.c (arm_cpu_builtins): Define __GCC_ASM_FLAG_OUTPUTS__. * config/arm/arm.c (TARGET_MD_ASM_ADJUST): New. * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): Define __GCC_ASM_FLAG_OUTPUTS__. * config/aarch64/aarch64.c (TARGET_MD_ASM_ADJUST): New. * doc/extend.texi (FlagOutputOperands): Add documentation for ARM and AArch64. From-SVN: r278226
2019-11-14arm: Rename CC_NOOVmode to CC_NZmodeRichard Henderson7-123/+164
CC_NZmode is a more accurate description of what we require from the mode, and matches up with the definition in aarch64. Rename noov_comparison_operator to nz_comparison_operator in order to match. * config/arm/arm-modes.def (CC_NZ): Rename from CC_NOOV. * config/arm/predicates.md (nz_comparison_operator): Rename from noov_comparison_operator. * config/arm/arm.c (arm_select_cc_mode): Use CC_NZmode name. (arm_gen_dicompare_reg): Likewise. (maybe_get_arm_condition_code): Likewise. (thumb1_final_prescan_insn): Likewise. (arm_emit_coreregs_64bit_shift): Likewise. * config/arm/arm.md (addsi3_compare0): Likewise. (*addsi3_compare0_scratch, subsi3_compare0): Likewise. (*mulsi3_compare0, *mulsi3_compare0_v6): Likewise. (*mulsi3_compare0_scratch, *mulsi3_compare0_scratch_v6): Likewise. (*mulsi3addsi_compare0, *mulsi3addsi_compare0_v6): Likewise. (*mulsi3addsi_compare0_scratch): Likewise. (*mulsi3addsi_compare0_scratch_v6): Likewise. (*andsi3_compare0, *andsi3_compare0_scratch): Likewise. (*zeroextractsi_compare0_scratch): Likewise. (*ne_zeroextractsi, *ne_zeroextractsi_shifted): Likewise. (*ite_ne_zeroextractsi, *ite_ne_zeroextractsi_shifted): Likewise. (andsi_not_shiftsi_si_scc_no_reuse): Likewise. (andsi_not_shiftsi_si_scc): Likewise. (*andsi_notsi_si_compare0, *andsi_notsi_si_compare0_scratch): Likewise. (*iorsi3_compare0, *iorsi3_compare0_scratch): Likewise. (*xorsi3_compare0, *xorsi3_compare0_scratch): Likewise. (*shiftsi3_compare0, *shiftsi3_compare0_scratch): Likewise. (*not_shiftsi_compare0, *not_shiftsi_compare0_scratch): Likewise. (*notsi_compare0, *notsi_compare0_scratch): Likewise. (return_addr_mask, *check_arch2): Likewise. (*arith_shiftsi_compare0, *arith_shiftsi_compare0_scratch): Likewise. (*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch): Likewise. (compare_scc splitters): Likewise. (movcond_addsi): Likewise. * config/arm/thumb2.md (thumb2_addsi3_compare0): Likewise. (*thumb2_addsi3_compare0_scratch): Likewise. (*thumb2_mulsi_short_compare0): Likewise. (*thumb2_mulsi_short_compare0_scratch): Likewise. (compare peephole2s): Likewise. * config/arm/thumb1.md (thumb1_cbz): Use CC_NZmode and nz_comparison_operator names. (cbranchsi4_insn): Likewise. From-SVN: r278225
2019-11-14arm: Fix the "c" constraintRichard Henderson2-2/+5
The existing definition using register class CC_REG does not work because CC_REGNUM does not support normal modes, and so fails to match register_operand. Use a non-register constraint and the cc_register predicate instead. * config/arm/constraints.md (c): Use cc_register predicate. From-SVN: r278224
2019-11-14aarch64: Add "c" constraintRichard Henderson2-0/+8
Mirror arm in letting "c" match the condition code register. * config/aarch64/constraints.md (c): New constraint. From-SVN: r278223
2019-11-14ipa-fnsummary.c (ipa_call_context::estimate_size_and_time, [...]): Micro ↵Jan Hubicka2-2/+11
optimize. * ipa-fnsummary.c (ipa_call_context::estimate_size_and_time, ipa_merge_fn_summary_after_inlining): Micro optimize. From-SVN: r278222
2019-11-14* params.opt (max-inline-insns-single-O2): Set to 70 (instead of 30).Jan Hubicka2-1/+5
From-SVN: r278221
2019-11-14Support for value ranges in IPA predicatesJan Hubicka7-54/+242
* ipa-cp.c (ipa_vr_operation_and_type_effects): Move up in file. (ipa_value_range_from_jfunc): New function. * ipa-fnsummary.c (evaluate_conditions_for_known_args): Add known_value_ranges parameter; use it to evalulate conditions. (evaluate_properties_for_edge): Compute known value ranges. (ipa_fn_summary_t::duplicate): Update use of evaluate_conditions_for_known_args. (estimate_ipcp_clone_size_and_time): Likewise. (ipa_merge_fn_summary_after_inlining): Likewise. * ipa-prop.h (ipa_value_range_from_jfunc): Declare. * gcc.dg/ipa/inline-9.c: New testcase. From-SVN: r278220
2019-11-14Remove usage of CIF_MAX_INLINE_INSNS_SINGLE_O2_LIMIT.Martin Liska2-10/+10
2019-11-14 Martin Liska <mliska@suse.cz> * ipa-inline.c (want_inline_small_function_p): Use CIF_MAX_INLINE_INSNS_AUTO_LIMIT instead of CIF_MAX_INLINE_INSNS_SINGLE_O2_LIMIT. From-SVN: r278219
2019-11-14Add Optimization keyword for param_max_inline_insns_auto param.Martin Liska9-35/+38
2019-11-14 Martin Liska <mliska@suse.cz> * ipa-cp.c (devirtualization_time_bonus): Use opt_for_fn of a callee to get value of the param. * ipa-inline.c (inline_insns_auto): Use proper opt_for_fn. * opts.c (maybe_default_option): Do not overwrite param value if optimization level does not match. Note that params usually have default value set via Init() keyword. * params.opt: Remove -param=max-inline-insns-auto-O2. * cif-code.def (MAX_INLINE_INSNS_AUTO_O2_LIMIT): Remove. * doc/invoke.texi: Remove documentation of max-inline-insns-auto-O2. 2019-11-14 Martin Liska <mliska@suse.cz> * c-c++-common/asan/memcmp-1.c: Update expected backtrace. From-SVN: r278218
2019-11-14Remove dead code in switch conv pass.Martin Liska3-11/+9
2019-11-14 Martin Liska <mliska@suse.cz> * tree-switch-conversion.c (switch_conversion::switch_conversion): Do not initialize m_other_count. (switch_conversion::collect): Do not count m_default_count and m_other_count as we use frequencies for edges. * tree-switch-conversion.h: Remove m_default_count and m_other_count. From-SVN: r278217
2019-11-14Remove wrong lto-dump: lto1 makefile dependency.Martin Liska2-1/+6
2019-11-14 Martin Liska <mliska@suse.cz> * Make-lang.in: Remove wrong dependency of LTO_DUMP_EXE on LTO_EXE. From-SVN: r278212
2019-11-14Document -fallocation-dce.Martin Liska2-1/+10
2019-11-14 Martin Liska <mliska@suse.cz> PR other/92329 * doc/invoke.texi: Document -fallocation-dce. From-SVN: r278211
2019-11-14Enable VPOPCNTDQ for icelake-{client,server} and tigerlake.Martin Liska2-1/+8
2019-11-14 Martin Liska <mliska@suse.cz> PR target/92389 * config/i386/i386.h: Add PTA_AVX512VPOPCNTDQ to PTA_ICELAKE_CLIENT which is later interited by PTA_ICELAKE_SERVER and PTA_TIGERLAKE. From-SVN: r278210
2019-11-14Update statistics about needed symbols in IPA ICF.Martin Liska3-10/+30
2019-11-14 Martin Liska <mliska@suse.cz> * ipa-icf.c (sem_item_optimizer::execute): Save loaded_symbols. (sem_item_optimizer::parse_nonsingleton_classes): Return number of loaded symbols. (sem_item_optimizer::merge_classes): Print statistics about totally needed symbols. * ipa-icf.h (parse_nonsingleton_classes): Change return type. (merge_classes): Add one argument. From-SVN: r278209
2019-11-14Handle FIELD_DECL in IPA ICF.Martin Liska2-1/+9
2019-11-14 Martin Liska <mliska@suse.cz> * ipa-icf-gimple.c (func_checker::hash_operand): Improve func_checker::hash_operand by handling of FIELD_DECLs. From-SVN: r278208
2019-11-14Use func_checker::hash_operand for hashing of GIMPLE operands.Martin Liska4-210/+81
2019-11-14 Martin Liska <mliska@suse.cz> * ipa-icf-gimple.h (func_checker::func_checker): Add default constructor. * ipa-icf.c (sem_function::init): Make operand_equal_p and hash_operand public. (sem_item::add_expr): Remove. (sem_item::add_type): Remove. (sem_function::hash_stmt): Use m_checker for hashing of GIMPLE statements. (sem_function::parse): Init with checker. (sem_variable::parse): Pass NULL as checker. (sem_item_optimizer::parse_funcs_and_vars): Pass checker to ::parse function. (sem_item_optimizer::parse_nonsingleton_classes): Likewise. (sem_variable::parse): New function. (sem_variable::get_hash): Only return computed hash value. (sem_variable::init): Initialize hash of a variable. * ipa-icf.h: Remove add_expr, add_type and add func_checker to couple of functions as a new argument. From-SVN: r278207
2019-11-14Update dump message in IPA ICF.Martin Liska2-2/+9
2019-11-14 Martin Liska <mliska@suse.cz> * ipa-icf-gimple.c (func_checker::compare_gimple_call): Update bail out reason. (func_checker::compare_gimple_assign): Likewise. From-SVN: r278206
2019-11-14i386-options.c (ix86_omp_device_kind_arch_isa): Don't change sse4.2 to ↵Jakub Jelinek5-10/+11
sse4_2 and sse4.1 to sse4.1. * config/i386/i386-options.c (ix86_omp_device_kind_arch_isa): Don't change sse4.2 to sse4_2 and sse4.1 to sse4.1. * config/i386/t-omp-device (omp-device-properties-i386): Likewise. * c-c++-common/gomp/declare-variant-11.c: Add "sse4.2" and "sse4.1" test. From-SVN: r278205
2019-11-14c-parser.c (c_parser_omp_context_selector): Don't require score argument to ↵Jakub Jelinek9-5/+56
fit into shwi, just to be INTEGER_CST. * c-parser.c (c_parser_omp_context_selector): Don't require score argument to fit into shwi, just to be INTEGER_CST. Diagnose negative score. * parser.c (cp_parser_omp_context_selector): Don't require score argument to fit into shwi, just to be INTEGER_CST. Diagnose negative score. * pt.c (tsubst_attribute): Likewise. * c-c++-common/gomp/declare-variant-2.c: Add test for non-integral score and for negative score. * c-c++-common/gomp/declare-variant-3.c: Add test for zero score. * g++.dg/gomp/declare-variant-8.C: Add test for negative and zero scores. From-SVN: r278204
2019-11-14c-omp.c (c_omp_check_context_selector): Add nvidia to the list of valid vendors.Jakub Jelinek4-1/+8
* c-omp.c (c_omp_check_context_selector): Add nvidia to the list of valid vendors. * c-c++-common/gomp/declare-variant-3.c: Add testcase for vendor nvidia. From-SVN: r278203
2019-11-14omp-general.c (omp_context_name_list_prop): New function.Jakub Jelinek18-85/+243
* omp-general.c (omp_context_name_list_prop): New function. (omp_context_selector_matches): Use it. Return 0 if it returns NULL. (omp_context_selector_props_compare): Allow equivalency of an identifier and a string literal containing no embedded zeros. c-family/ * c-omp.c (c_omp_check_context_selector): Handle name lists containing string literals. Don't diagnose atomic_default_mem_order with multiple props. c/ * c-parser.c (c_parser_omp_context_selector): Rename CTX_PROPERTY_IDLIST to CTX_PROPERTY_NAME_LIST, add CTX_PROPERTY_ID. Use CTX_PROPERTY_ID for atomic_default_mem_order, only allow a single identifier in that. For CTX_PROPERTY_NAME_LIST, allow identifiers and string literals. cp/ * parser.c (cp_parser_omp_context_selector): Rename CTX_PROPERTY_IDLIST to CTX_PROPERTY_NAME_LIST, add CTX_PROPERTY_ID. Use CTX_PROPERTY_ID for atomic_default_mem_order, only allow a single identifier in that. For CTX_PROPERTY_NAME_LIST, allow identifiers and string literals. * pt.c (tsubst_attribute): Fix up STRING_CST handling if allow_string. testsuite/ * c-c++-common/gomp/declare-variant-2.c: Adjust expected diagnostics, add a test for atomic_default_mem_order with a string literal. * c-c++-common/gomp/declare-variant-3.c: Use string literal props in a few random places, add a few string literal prop related tests. * c-c++-common/gomp/declare-variant-8.c: Likewise. * c-c++-common/gomp/declare-variant-9.c: Use string literal props in a few random places. * c-c++-common/gomp/declare-variant-10.c: Likewise. * c-c++-common/gomp/declare-variant-11.c: Likewise. * c-c++-common/gomp/declare-variant-12.c: Likewise. * g++.dg/gomp/declare-variant-7.C: Likewise. From-SVN: r278202
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