aboutsummaryrefslogtreecommitdiff
path: root/gcc
AgeCommit message (Collapse)AuthorFilesLines
2016-07-01altivec.md (*altivec_vpermr_<mode>_internal): Exchange the order of the ↵Kelvin Nilsen2-1/+7
second and third operands in the vpermr instruction... gcc/ChangeLog: 2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/altivec.md (*altivec_vpermr_<mode>_internal): Exchange the order of the second and third operands in the vpermr instruction tmeplate. From-SVN: r237912
2016-07-01re PR target/71698 (ICE related to decimal float when compiling with ↵Peter Bergner4-2/+27
-mcpu=power9) gcc/ PR target/71698 * config/rs6000/rs6000.c (rs6000_secondary_reload_simple_move): Disallow TDmode values. gcc/testsuite/ PR target/71698 * gcc.target/powerpc/pr71698.c: New test. From-SVN: r237911
2016-07-01re PR target/71151 ([avr] -fmerge-constants and ↵Georg-Johann Lay9-21/+58
-fdata-sections/-ffunction-sections results in string constants in .progmem.gcc_sw section) gcc/testsuite/ PR target/71151 * gcc.target/avr/pr71151-common.h (foo): Use macro SECTION_NAME instead of ".foo" for its section name. * gcc.target/avr/pr71151-2.c (SECTION_NAME): Define appropriately depending on MCU's flash size. * gcc.target/avr/pr71151-3.c (SECTION_NAME): Dito. * gcc.target/avr/pr71151-4.c (SECTION_NAME): Dito. * gcc.target/avr/pr71151-5.c (SECTION_NAME): Dito. * gcc.target/avr/pr71151-6.c (SECTION_NAME): Dito. * gcc.target/avr/pr71151-7.c (SECTION_NAME): Dito. * gcc.target/avr/pr71151-8.c (SECTION_NAME): Dito. From-SVN: r237910
2016-07-01strcpy arg optimised outAlan Modra2-1/+7
For functions that return an argument unchanged, like strcat, find_call_crossed_cheap_reg attempts to find an assignment between a pseudo reg and the arg reg before the call, so that uses of the pseudo after the call can instead use the return value. The exit condition on the loop looking at previous insns was wrong. Uses of the arg reg don't matter. What matters is the insn setting the arg reg as any assignment involving the arg reg prior to that insn is likely a completely unrelated use of the hard reg. PR rtl-optimization/71709 * ira-lives.c (find_call_crossed_cheap_reg): Exit loop on arg reg being set, not referenced. From-SVN: r237909
2016-07-01ix86: fix PR/65105 testcase 2Jan Beulich2-1/+5
I cannot see how without allowing the compiler to use SSE2 instructions (as is done by all other tests for this PR scanning for particular instructions) this test could ever have succeeded anywhere. gcc/testsuite/ 2016-07-01 Jan Beulich <jbeulich@suse.com> * gcc.target/i386/pr65105-2.c: Add -msse2. From-SVN: r237908
2016-07-01re PR tree-optimization/70729 (Loop marked with omp simd pragma is not ↵Yuri Rumyantsev2-0/+10
vectorized) PR tree-optimization/70729 gcc/ * tree-vectorizer.c (adjust_simduid_builtins): Nullify safelen field of loop since it can be not valid after transformation. From-SVN: r237907
2016-07-01[ARM] Delete thumb_reload_in_hKyrylo Tkachov3-8/+5
* config/arm/arm.c (thumb_reload_in_hi): Delete. * config/arm/arm-protos.h (thumb_reload_in_hi): Delete prototype. From-SVN: r237906
2016-07-01arm.c (arm_function_ok_for_sibcall): Add another check for NULL decl.Eric Botcazou2-1/+6
* config/arm/arm.c (arm_function_ok_for_sibcall): Add another check for NULL decl. From-SVN: r237903
2016-07-01Daily bump.GCC Administrator1-1/+1
From-SVN: r237902
2016-06-30re PR target/71677 (PowerPC ISA 3.0 DImode load/store needs a fix)Michael Meissner4-8/+38
2016-06-30 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/71677 * config/rs6000/constraints.md (wY constraint): New constraint to match the requirements for the LXSD and STXSD instructions. * config/rs6000/predicates.md (offsettable_mem_14bit_operand): New predicate to match the requirements for the LXSD and STXSD instructions. * config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case): Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y' to make sure that the bottom 2 bits of offset are 0, the address form is offsettable, and no updating is done in the address mode. (mov<mode>_hardfloat64, FMOVE64 case): Likewise. (movdi_internal32): Likewise (movdi_internal64): Likewise. From-SVN: r237898
2016-06-30re PR tree-optimization/71707 (ICE in get_stridx_plus_constant)Jakub Jelinek4-2/+44
PR tree-optimization/71707 * tree-ssa-strlen.c (get_stridx_plus_constant): Handle already present strinfo even for ADDR_EXPR ptr. * gcc.dg/strlenopt-29.c: New test. From-SVN: r237889
2016-06-30re PR fortran/71704 (ICE with -fopenmp and some omp constructs)Jakub Jelinek4-33/+150
PR fortran/71704 * parse.c (matchs, matcho): Move right before decode_omp_directive. If spec_only, only gfc_match the keyword and if successful, goto do_spec_only. (matchds, matchdo): Define. (decode_omp_directive): Add spec_only local var and set it. Use matchds or matchdo macros instead of matchs or matcho for declare target, declare simd, declare reduction and threadprivate directives. Return ST_GET_FCN_CHARACTERISTICS if a non-declarative directive could be matched. (next_statement): For ST_GET_FCN_CHARACTERISTICS restore gfc_current_locus from old_locus even if there is no label. * gfortran.dg/gomp/pr71704.f90: New test. From-SVN: r237888
2016-06-30re PR fortran/71705 (ICE in lower_omp_target, at omp-low.c:16136)Jakub Jelinek4-0/+20
PR fortran/71705 * trans-openmp.c (gfc_trans_omp_clauses): Set TREE_ADDRESSABLE on decls in to/from clauses. * gfortran.dg/gomp/pr71705.f90: New test. From-SVN: r237887
2016-06-30altivec.md (darn_32): Change the condition to TARGET_P9_MISC instead of ↵Kelvin Nilsen92-13/+1782
TARGET_MODULO. gcc/ChangeLog: 2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/altivec.md (darn_32): Change the condition to TARGET_P9_MISC instead of TARGET_MODULO. (darn_raw): Replace TARGET_MODULO with TARGET_P9_MISC in the condition expression. (darn): Replace TARGET_MODULO with TARGET_P9_MISC in the condition expression. * config/rs6000/dfp.md (UNSPEC_DTSTSFI): New unspec constant. (DFP_TEST): New code iterator. (dfptstsfi_<code>_mode>): New define_expand. (*dfp_sgnfcnc_<mode>): New define_insn. * config/rs6000/rs6000-builtin.def (BU_P9_MISC_0): Move this macro definition next to BU_P9_MISC_1 definition and change the MASK value to RS6000_BTM_P9_MISC. (BU_P9_MISC_1): Change the MASK value to RS6000_BTM_P9_MISC. (BU_P9_64BIT_MISC_0): Likewise. (BU_P9_DFP_MISC_0): New macro definition. (BU_P9_DFP_MISC_1): New macro definition. (BU_P9_DFP_MISC_2): New macro definition. (BU_P9_DFP_OVERLOAD_1): New macro definition. (BU_P9_DFP_OVERLOAD_2): New macro definition. (BU_P9_DFP_OVERLOAD_3): New macro definition. (TSTSFI_LT_DD): New BU_P9_DFP_MISC_2. (TSTSFI_LT_TD): Likewise. (TSTSFI_EQ_DD): Likewise. (TSTSFI_EQ_TD): Likewise. (TSTSFI_GT_DD): Likewise. (TSTSFI_GT_TD): Likewise. (TSTSFI_OV_DD): Likewise. (TSTSFI_OV_TD): Likewise. (TSTSFI_LT): New BU_P9_DFP_OVERLOAD_2. (TSTSFI_LT_DD): Likewise. (TSTSFI_LT_TD): Likewise. (TSTSFI_EQ): Likewise. (TSTSFI_EQ_DD): Likewise. (TSTSFI_EQ_TD): Likewise. (TSTSFI_GT): Likewise. (TSTSFI_GT_DD): Likewise. (TSTSFI_GT_TD): Likewise. (TSTSFI_OV): Likewise. (TSTSFI_OV_DD): Likewise. (TSTSFI_OV_TD): Likewise. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add overloaded test significance functions. * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add OPTION_MASK_P9_MISC into the representation of this mask. (POWERPC_MASKS): Add OPTION_MASK_P9_MISC into the representation of this mask. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Set the RS6000_BTM_P9_MISC flag in the return value if TARGET_P9_MISC is non-zero. (rs6000_expand_binop_builtin): Enforce that argument 0 of the exp argument is a 6-bit unsigned literal value if the icode argument represents a DFP test significance built-in call. (rs6000_invalid_builtin): Add support for the RS6000_BTM_P9_MISC flag used independently and in combination with the RS6000_BTM_64BIT flag. (rs6000_opt_masks): Add entry for power9-misc command-line option. (rs6000_builtin_mask_names): Add entry for power9-misc command-line option. * config/rs6000/rs6000.h: Redefine TARGET_P9_MISC as 0 if HAVE_AS_POWER9 is not a defined macro. Define MASK_P9_MISC and RS6000_BTM_P9_MISC macros. * config/rs6000/rs6000.opt: Add support for the -mpower9-misc option and change the description of the -mpower9-vector option to enable only vector instructions, removing its erroneously claimed support for scalar instructions. * doc/extend.texi (PowerPC AltiVec Built-in Functions): Document the ISA 3.0 digital floating point test significance built-in functions. gcc/testsuite/ChangeLog: 2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/dfp/dfp.exp: New dejagnu test script. * gcc.target/powerpc/dfp/dtstsfi-0.c: New test. * gcc.target/powerpc/dfp/dtstsfi-1.c: New test. * gcc.target/powerpc/dfp/dtstsfi-10.c: New test. * gcc.target/powerpc/dfp/dtstsfi-11.c: New test. * gcc.target/powerpc/dfp/dtstsfi-12.c: New test. * gcc.target/powerpc/dfp/dtstsfi-13.c: New test. * gcc.target/powerpc/dfp/dtstsfi-14.c: New test. * gcc.target/powerpc/dfp/dtstsfi-15.c: New test. * gcc.target/powerpc/dfp/dtstsfi-16.c: New test. * gcc.target/powerpc/dfp/dtstsfi-17.c: New test. * gcc.target/powerpc/dfp/dtstsfi-18.c: New test. * gcc.target/powerpc/dfp/dtstsfi-19.c: New test. * gcc.target/powerpc/dfp/dtstsfi-2.c: New test. * gcc.target/powerpc/dfp/dtstsfi-20.c: New test. * gcc.target/powerpc/dfp/dtstsfi-21.c: New test. * gcc.target/powerpc/dfp/dtstsfi-22.c: New test. * gcc.target/powerpc/dfp/dtstsfi-23.c: New test. * gcc.target/powerpc/dfp/dtstsfi-24.c: New test. * gcc.target/powerpc/dfp/dtstsfi-25.c: New test. * gcc.target/powerpc/dfp/dtstsfi-26.c: New test. * gcc.target/powerpc/dfp/dtstsfi-27.c: New test. * gcc.target/powerpc/dfp/dtstsfi-28.c: New test. * gcc.target/powerpc/dfp/dtstsfi-29.c: New test. * gcc.target/powerpc/dfp/dtstsfi-3.c: New test. * gcc.target/powerpc/dfp/dtstsfi-30.c: New test. * gcc.target/powerpc/dfp/dtstsfi-31.c: New test. * gcc.target/powerpc/dfp/dtstsfi-32.c: New test. * gcc.target/powerpc/dfp/dtstsfi-33.c: New test. * gcc.target/powerpc/dfp/dtstsfi-34.c: New test. * gcc.target/powerpc/dfp/dtstsfi-35.c: New test. * gcc.target/powerpc/dfp/dtstsfi-36.c: New test. * gcc.target/powerpc/dfp/dtstsfi-37.c: New test. * gcc.target/powerpc/dfp/dtstsfi-38.c: New test. * gcc.target/powerpc/dfp/dtstsfi-39.c: New test. * gcc.target/powerpc/dfp/dtstsfi-4.c: New test. * gcc.target/powerpc/dfp/dtstsfi-40.c: New test. * gcc.target/powerpc/dfp/dtstsfi-41.c: New test. * gcc.target/powerpc/dfp/dtstsfi-42.c: New test. * gcc.target/powerpc/dfp/dtstsfi-43.c: New test. * gcc.target/powerpc/dfp/dtstsfi-44.c: New test. * gcc.target/powerpc/dfp/dtstsfi-45.c: New test. * gcc.target/powerpc/dfp/dtstsfi-46.c: New test. * gcc.target/powerpc/dfp/dtstsfi-47.c: New test. * gcc.target/powerpc/dfp/dtstsfi-48.c: New test. * gcc.target/powerpc/dfp/dtstsfi-49.c: New test. * gcc.target/powerpc/dfp/dtstsfi-5.c: New test. * gcc.target/powerpc/dfp/dtstsfi-50.c: New test. * gcc.target/powerpc/dfp/dtstsfi-51.c: New test. * gcc.target/powerpc/dfp/dtstsfi-52.c: New test. * gcc.target/powerpc/dfp/dtstsfi-53.c: New test. * gcc.target/powerpc/dfp/dtstsfi-54.c: New test. * gcc.target/powerpc/dfp/dtstsfi-55.c: New test. * gcc.target/powerpc/dfp/dtstsfi-56.c: New test. * gcc.target/powerpc/dfp/dtstsfi-57.c: New test. * gcc.target/powerpc/dfp/dtstsfi-58.c: New test. * gcc.target/powerpc/dfp/dtstsfi-59.c: New test. * gcc.target/powerpc/dfp/dtstsfi-6.c: New test. * gcc.target/powerpc/dfp/dtstsfi-60.c: New test. * gcc.target/powerpc/dfp/dtstsfi-61.c: New test. * gcc.target/powerpc/dfp/dtstsfi-62.c: New test. * gcc.target/powerpc/dfp/dtstsfi-63.c: New test. * gcc.target/powerpc/dfp/dtstsfi-64.c: New test. * gcc.target/powerpc/dfp/dtstsfi-65.c: New test. * gcc.target/powerpc/dfp/dtstsfi-66.c: New test. * gcc.target/powerpc/dfp/dtstsfi-67.c: New test. * gcc.target/powerpc/dfp/dtstsfi-68.c: New test. * gcc.target/powerpc/dfp/dtstsfi-69.c: New test. * gcc.target/powerpc/dfp/dtstsfi-7.c: New test. * gcc.target/powerpc/dfp/dtstsfi-70.c: New test. * gcc.target/powerpc/dfp/dtstsfi-71.c: New test. * gcc.target/powerpc/dfp/dtstsfi-72.c: New test. * gcc.target/powerpc/dfp/dtstsfi-73.c: New test. * gcc.target/powerpc/dfp/dtstsfi-74.c: New test. * gcc.target/powerpc/dfp/dtstsfi-75.c: New test. * gcc.target/powerpc/dfp/dtstsfi-76.c: New test. * gcc.target/powerpc/dfp/dtstsfi-77.c: New test. * gcc.target/powerpc/dfp/dtstsfi-78.c: New test. * gcc.target/powerpc/dfp/dtstsfi-79.c: New test. * gcc.target/powerpc/dfp/dtstsfi-8.c: New test. * gcc.target/powerpc/dfp/dtstsfi-9.c: New test. From-SVN: r237885
2016-06-30This patch sets the branch cost to the same most optimal setting for all ↵Wilco Dijkstra2-6/+15
Cortex cores... This patch sets the branch cost to the same most optimal setting for all Cortex cores, reducing codesize and improving performance due to using more CSEL instructions. Set the autoprefetcher model in Cortex-A72 to weak like the others. Enable AES fusion in Cortex-A35. As a result generated code is now more similar as well as more optimal across Cortex cores. gcc/ * config/aarch64/aarch64.c (cortexa35_tunings): Enable AES fusion. Use cortexa57_branch_cost. (cortexa53_tunings): Use cortexa57_branch_cost. (cortexa72_tunings): Use cortexa57_branch_cost. Use AUTOPREFETCHER_WEAK. (cortexa73_tunings): Use cortexa57_branch_cost. From-SVN: r237884
2016-06-30[AArch64][2/2] (Re)Implement vcopy<q>_lane<q> intrinsicsKyrylo Tkachov4-156/+501
2016-06-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> James Greenhalgh <james.greenhalgh@arm.com> * config/aarch64/arm_neon.h (vcopyq_lane_f32, vcopyq_lane_f64, vcopyq_lane_p8, vcopyq_lane_p16, vcopyq_lane_s8, vcopyq_lane_s16, vcopyq_lane_s32, vcopyq_lane_s64, vcopyq_lane_u8, vcopyq_lane_u16, vcopyq_lane_u32, vcopyq_lane_u64): Reimplement in C. (vcopy_lane_f32, vcopy_lane_f64, vcopy_lane_p8, vcopy_lane_p16, vcopy_lane_s8, vcopy_lane_s16, vcopy_lane_s32, vcopy_lane_s64, vcopy_lane_u8, vcopy_lane_u16, vcopy_lane_u32, vcopy_lane_u64, vcopy_laneq_f32, vcopy_laneq_f64, vcopy_laneq_p8, vcopy_laneq_p16, vcopy_laneq_s8, vcopy_laneq_s16, vcopy_laneq_s32, vcopy_laneq_s64, vcopy_laneq_u8, vcopy_laneq_u16, vcopy_laneq_u32, vcopy_laneq_u64, vcopyq_laneq_f32, vcopyq_laneq_f64, vcopyq_laneq_p8, vcopyq_laneq_p16, vcopyq_laneq_s8, vcopyq_laneq_s16, vcopyq_laneq_s32, vcopyq_laneq_s64, vcopyq_laneq_u8, vcopyq_laneq_u16, vcopyq_laneq_u32, vcopyq_laneq_u64): New intrinsics. * gcc.target/aarch64/vect_copy_lane_1.c: New test. Co-Authored-By: James Greenhalgh <james.greenhalgh@arm.com> From-SVN: r237883
2016-06-30[AArch64][1/2] Add support INS (element) instruction to copy lanes between ↵James Greenhalgh4-0/+127
vectors 2016-06-30 James Greenhalgh <james.greenhalgh@arm.com> Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>): New define_insn. (*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise. * gcc.target/aarch64/vget_set_lane_1.c: New test. Co-Authored-By: Kyrylo Tkachov <kyrylo.tkachov@arm.com> From-SVN: r237882
2016-06-30Fix bogus option suggestions for RejectNegative options (PR driver/71651)David Malcolm6-5/+37
gcc/ChangeLog: PR driver/71651 * gcc.c (driver::build_option_suggestions): Pass "option" to add_misspelling_candidates. * opts-common.c (add_misspelling_candidates): Add "option" param; use it to avoid adding negated forms for options marked with RejectNegative. * opts.h (add_misspelling_candidates): Add "option" param. gcc/testsuite/ChangeLog: PR driver/71651 * gcc.dg/spellcheck-options-12.c: New test case. From-SVN: r237880
2016-06-30re PR middle-end/71693 (ICE: verify_gimple failed (type mismatch in shift ↵Jakub Jelinek4-6/+33
expression, -O0, -O1, -O2, -O3)) PR middle-end/71693 * fold-const.c (fold_binary_loc) <case RROTATE_EXPR>: Cast TREE_OPERAND (arg0, 0) and TREE_OPERAND (arg0, 1) to type first when permuting bitwise operation with rotate. Cast TREE_OPERAND (arg0, 0) to type when cancelling two rotations. * gcc.c-torture/compile/pr71693.c: New test. From-SVN: r237875
2016-06-30Daily bump.GCC Administrator1-1/+1
From-SVN: r237869
2016-06-30Offer suggestions for misspelled --param names.David Malcolm9-19/+66
gcc/ChangeLog: * opts.c (handle_param): Use find_param_fuzzy to offer suggestions for misspelled param names. * params.c: Include spellcheck.h. (find_param_fuzzy): New function. * params.h (find_param_fuzzy): New prototype. * spellcheck.c (struct edit_distance_traits<const char *>): Move to... * spellcheck.h (struct edit_distance_traits<const char *>): ...here. gcc/testsuite/ChangeLog: * gcc.dg/spellcheck-params.c: New testcase. * gcc.dg/spellcheck-params-2.c: New testcase. From-SVN: r237865
2016-06-29predicates.md (const_0_to_7_operand): New predicate, recognize 0..7.Michael Meissner9-3/+204
[gcc] 2016-06-29 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/predicates.md (const_0_to_7_operand): New predicate, recognize 0..7. * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add support for doing extracts from V16QImode, V8HImode, V4SImode under ISA 3.0. * config/rs6000/vsx.md (VSX_EXTRACT_I): Mode iterator for ISA 3.0 vector extract support. (VSX_EXTRACT_PREDICATE): Mode attribute to validate element number for ISA 3.0 vector extract. (VSX_EX): Constraints to use for ISA 3.0 vector extract. (vsx_extract_<mode>, VSX_EXTRACT_I): Add support for doing extracts of a constant element number from small integer vectors on 64-bit ISA 3.0 systems. (vsx_extract_<mode>_di): Likewise. * config/rs6000/rs6000.h (TARGET_VEXTRACTUB): New target macro to say when we can do ISA 3.0 vector extracts. * config/rs6000/rs6000.md (stfiwx): Allow DImode in Altivec registers, using the stxsiwx instruction. [gcc/testsuite] 2016-06-29 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-extract-1.c: New file to test ISA 3.0 vector extract instructions. * gcc.target/powerpc/p9-extract-2.c: Likewise. From-SVN: r237864
2016-06-29re PR fortran/71686 (ICE on broken character continuation)Jerry DeLisle3-0/+19
2016-06-29 Jerry DeLisle <jvdelisle@gcc.gnu.org> PR fortran/71686 * gfortran.dg/unexpected_eof_2.f90: New test. * gfortran.dg/unexpected_eof_3.f90: New test. From-SVN: r237861
2016-06-29re PR fortran/71686 (ICE on broken character continuation)Jerry DeLisle2-2/+12
2016-06-29 Jerry DeLisle <jvdelisle@gcc.gnu.org> PR fortran/71686 * scanner.c (gfc_next_char_literal): Only decrement nextc if it is not NULL. From-SVN: r237860
2016-06-29Add qdf24xx base tuning support.Jim Wilson8-2/+193
gcc/ * config/aarch64/aarch64-cores.def (qdf24xx): Use qdf24xx tuning. * config/aarch64/aarch64.c (qdf24xx_addrcost_table, qdf24xx_regmove_cost, qdf24xx_tunings): New. * config/arm/aarch64-cost-tables.h (qdf24xx_extra_costs): New. * config/arm/arm-cores.def (qdf24xx): Use qdf24xx tuning. * config/arm/arm.c (arm_qdf24xx_tune): New. gcc/testsuite/ * gcc.dg/asr_div1.c: Add aarch64 specific dg-options. From-SVN: r237857
2016-06-29openmp.c (match_oacc_clause_gang): Rename to ...Cesar Philippidis6-62/+146
gcc/fortran/ * openmp.c (match_oacc_clause_gang): Rename to ... (match_oacc_clause_gwv): this. Add support for OpenACC worker and vector clauses. (gfc_match_omp_clauses): Use match_oacc_clause_gwv for OMP_CLAUSE_{GANG,WORKER,VECTOR}. Propagate any MATCH_ERRORs for invalid OMP_CLAUSE_{ASYNC,WAIT,GANG,WORKER,VECTOR} clauses. (gfc_match_oacc_wait): Propagate MATCH_ERROR for invalid oacc_expr_lists. Adjust the first and needs_space arguments to gfc_match_omp_clauses. gcc/testsuite/ * gfortran.dg/goacc/asyncwait-2.f95: Updated expected diagnostics. * gfortran.dg/goacc/asyncwait-3.f95: Likewise. * gfortran.dg/goacc/asyncwait-4.f95: Add test coverage. From-SVN: r237854
2016-06-29re PR tree-optimization/15256 ([tree-ssa] Optimize manual bitfield ↵Richard Biener2-0/+20
manipilation.) 2016-06-29 Richard Biener <rguenther@suse.de> PR middle-end/15256 * gcc.dg/tree-ssa/forwprop-34.c: New testcase. From-SVN: r237852
2016-06-29Increase loop alignment on Cortex cores to 8 and set function alignment to 16.Wilco Dijkstra2-7/+16
This makes things consistent across big.LITTLE cores, improves performance of benchmarks with tight loops and reduces performance variations due to small changes in code layout. gcc/ * config/aarch64/aarch64.c (cortexa53_tunings): Increase loop alignment to 8. Set function alignment to 16. (cortexa35_tunings): Likewise. (cortexa57_tunings): Increase loop alignment to 8. (cortexa72_tunings): Likewise. (cortexa73_tunings): Likewise. From-SVN: r237851
2016-06-29re PR ada/48835 (porting GNAT to m68k-linux)Eric Botcazou6-57/+103
PR ada/48835 PR ada/61954 * gcc-interface/gigi.h (enum standard_datatypes): Add ADT_realloc_decl (realloc_decl): New macro. * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Use local variable for the entity type and translate it as void pointer if the entity has convention C. (gnat_to_gnu_entity) <E_Function>: If this is not a definition and the external name matches that of malloc_decl or realloc_decl, return the correspoding node directly. (gnat_to_gnu_subprog_type): Likewise for parameter and return types. * gcc-interface/trans.c (gigi): Initialize void_list_node here, not... Initialize realloc_decl. * gcc-interface/utils.c (install_builtin_elementary_types): ...here. (build_void_list_node): Delete. * gcc-interface/utils2.c (known_alignment) <CALL_EXPR>: Return the alignment of the system allocator for malloc_decl and realloc_decl. Do not take alignment from void pointer types either. From-SVN: r237850
2016-06-29[ARM] Fix, add tests for FP16 aapcs.Matthew Wahab9-27/+71
testsuite/ * gcc.target/arm/aapcs/neon-vect10.c: Require -mfloat-ab=hard. Replace arm_neon_fp16_ok with arm_neon_fp16_hw. * gcc.target/arm/aapcs/neon-vect9.c: Likewise. * gcc.target/arm/aapcs/vfp18.c: Likewise. * gcc.target/arm/aapcs/vfp19.c: Likewise. * gcc.target/arm/aapcs/vfp20.c: Likewise. * gcc.target/arm/aapcs/vfp21.c: Likewise. * gcc.target/arm/fp16-aapcs-1.c: Require -mfloat-ab=hard. Also simplify the test. * gcc.target/arm/fp16-aapcs-2.c: New. From-SVN: r237849
2016-06-29misc.c (LANG_HOOKS_WARN_UNUSED_GLOBAL_DECL): Reorder.Eric Botcazou2-6/+10
* gcc-interface/misc.c (LANG_HOOKS_WARN_UNUSED_GLOBAL_DECL): Reorder. (LANG_HOOKS_INIT_TS): Likewise. From-SVN: r237848
2016-06-29[Testsuite] Selectors and options directives for ARM VFP FP16 support.Matthew Wahab4-5/+102
gcc/ * doc/sourcebuild.texi (Effective-Target keywords): Add entries for arm_fp16_ok and arm_fp16_hw. (Add Options): Add entries for arm_fp16, arm_fp16_ieee and arm_fp16_alternative. testsuite/ * lib/target-supports.exp (add_options_for arm_fp16): Reword comment. (add_options_for_arm_fp16_ieee): New. (add_options_for_arm_fp16_alternative): New. (effective_target_arm_fp16_ok_nocache): Add to comment. Fix a long-line. (effective_target_arm_fp16_hw): New. From-SVN: r237847
2016-06-29re PR tree-optimization/71655 (GCC trunk ICE on westmere target)Ilya Enkovich4-0/+41
gcc/ PR tree-optimization/71655 * tree-vect-stmts.c (vectorizable_comparison): Swap definition types when swapping operands. gcc/testsuite/ PR tree-optimization/71655 * g++.dg/pr71655.C: New test. From-SVN: r237846
2016-06-29Mark -fstack-protect as optimization flag.Martin Liska7-6/+89
PR middle-end/71585 * common.opt (flag_stack_protect): Mark the flag as optimization flag. * ipa-inline-transform.c (inline_call): Remove unnecessary call of build_optimization_node. * gcc.dg/pr71585.c: New test. * gcc.dg/pr71585-2.c: New test. * gcc.dg/pr71585-3.c: New test. From-SVN: r237845
2016-06-29re PR tree-optimization/70729 (Loop marked with omp simd pragma is not ↵Yuri Rumyantsev5-0/+105
vectorized) gcc/ 2016-06-29 Yuri Rumyantsev <ysrumyan@gmail.com> PR tree-optimization/70729 * tree-ssa-loop-im.c (ref_indep_loop_p_1): Consider memory reference as independent in loops having positive safelen value. * tree-vect-loop.c (vect_transform_loop): Clear-up safelen value since it may be not valid after vectorization. gcc/testsuite/ 2016-06-29 Yuri Rumyantsev <ysrumyan@gmail.com> PR tree-optimization/70729 * g++.dg/vect/pr70729.cc: New test. From-SVN: r237844
2016-06-29Improve diagnostic messages of "#pragma omp cancel", "#pragma omp ↵Thomas Schwinge8-30/+72
cancellation point" parsing gcc/c/ * c-parser.c (c_parser_pragma) <PRAGMA_OMP_CANCELLATION_POINT>: Move pragma context checking into... (c_parser_omp_cancellation_point): ... here, and improve diagnostic messages. * c-typeck.c (c_finish_omp_cancel) (c_finish_omp_cancellation_point): Improve diagnostic messages. gcc/cp/ * parser.c (cp_parser_pragma) <PRAGMA_OMP_CANCELLATION_POINT>: Move pragma context checking into... (cp_parser_omp_cancellation_point): ... here, and improve diagnostic messages. * semantics.c (finish_omp_cancel, finish_omp_cancellation_point): Improve diagnostic messages. gcc/testsuite/ * c-c++-common/gomp/cancel-1.c: Extend. From-SVN: r237843
2016-06-29Rename PRAGMA_OMP_DECLARE_REDUCTION to PRAGMA_OMP_DECLAREThomas Schwinge5-6/+12
gcc/c-family/ * c-pragma.h (enum pragma_kind): Rename PRAGMA_OMP_DECLARE_REDUCTION to PRAGMA_OMP_DECLARE. Adjust all users. From-SVN: r237842
2016-06-29re PR tree-optimization/71625 (missing strlen optimization on different ↵Jakub Jelinek4-10/+116
array initialization style) PR tree-optimization/71625 * tree-ssa-strlen.c (get_addr_stridx): Add PTR argument. Assume list is sorted by ascending list->offset. If PTR is non-NULL and there is previous strinfo, call get_stridx_plus_constant. (get_stridx): Pass exp as second argument to get_addr_stridx. (addr_stridxptr): Add missing list = list->next, so that there can be more than one entries in the list. Bump limit from 16 to 32. Ensure the list is sorted by ascending list->offset. (get_stridx_plus_constant): Adjust so that it can be also called with ADDR_EXPR instead of SSA_NAME as PTR. (handle_char_store): Pass NULL_TREE as second argument to get_addr_stridx. * gcc.dg/strlenopt-28.c: New test. From-SVN: r237841
2016-06-29re PR tree-optimization/68961 (Test case gcc.target/powerpc/pr60203.c fails ↵Richard Biener2-5/+14
since r231674) 2016-06-29 Richard Biener <rguenther@suse.de> PR rtl-optimization/68961 * simplify-rtx.c (simplify_subreg): Handle VEC_CONCAT like CONCAT. From-SVN: r237840
2016-06-29re PR middle-end/71002 (-fstrict-aliasing breaks Boost's short string ↵Richard Biener9-59/+34
optimization implementation) 2016-06-29 Richard Biener <rguenther@suse.de> PR middle-end/71002 * alias.c (component_uses_parent_alias_set_from): Handle type punning through union accesses by using the union alias set. * gimple.c (gimple_get_alias_set): Remove union type punning case. c-family/ * c-common.c (c_common_get_alias_set): Remove union type punning case. fortran/ * f95-lang.c (LANG_HOOKS_GET_ALIAS_SET): Remove (un-)define. (gfc_get_alias_set): Remove. * g++.dg/torture/pr71002.C: Adjust testcase. From-SVN: r237839
2016-06-29match.pd ((T)(T2)x -> (T)x): Remove restriction on final precision not ↵Richard Biener2-8/+8
matching mode precision. 2016-07-29 Richard Biener <rguenther@suse.de> * match.pd ((T)(T2)x -> (T)x): Remove restriction on final precision not matching mode precision. From-SVN: r237838
2016-06-29pa.md (call_symref_64bit_post_reload): Don't call pa_output_arg_descriptor.John David Anglin2-5/+9
* config/pa/pa.md (call_symref_64bit_post_reload): Don't call pa_output_arg_descriptor. (call_val_symref_64bit_post_reload): Likewise. (call_val_powf_64bit_post_reload): Likewise. (sibcall_internal_symref_64bit): Likewise. (sibcall_value_internal_symref_64bit): Likewise. From-SVN: r237837
2016-06-29Daily bump.GCC Administrator1-1/+1
From-SVN: r237836
2016-06-29re PR c/71685 (Segmentation fault in gcc when compiling the attached file.)Jakub Jelinek4-3/+21
PR c/71685 * c-typeck.c (c_build_qualified_type): Don't clear C_TYPE_INCOMPLETE_VARS for the main variant. * gcc.dg/pr71685.c: New test. From-SVN: r237830
2016-06-28PR c/71552 - Confusing error for incorrect struct initializationMartin Sebor4-11/+41
gcc/c/ChangeLog: PR c/71552 * c-typeck.c (output_init_element): Diagnose incompatible types before non-constant initializers. gcc/testsuite/ChangeLog: PR c/71552 * gcc.dg/init-bad-9.c: New test. From-SVN: r237829
2016-06-28abs128-1.c: Require VSX.Bill Schmidt5-8/+15
2016-06-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/abs128-1.c: Require VSX. * gcc.target/powerpc/copysign128-1.c: Likewise. * gcc.target/powerpc/inf128-1.c: Likewise. * gcc.target/powerpc/nan128-1.c: Likewise. From-SVN: r237828
2016-06-28re PR middle-end/71626 (ICE at -O1 and above on x86_64-linux-gnu (in ↵Jakub Jelinek5-10/+58
output_constant_pool_2, at varasm.c:3837)) PR middle-end/71626 * config/i386/i386.c (ix86_expand_vector_move): For SUBREG of a constant, force its SUBREG_REG into memory or register instead of whole op1. * gcc.c-torture/execute/pr71626-1.c: New test. * gcc.c-torture/execute/pr71626-2.c: New test. From-SVN: r237826
2016-06-28re PR target/58655 ([avr] -mfract-convert-truncate not documented)Pitchumani Sivanupandi3-3/+13
PR target/58655 * config/avr/avr.opt (-mfract-convert-truncate): Update description. * doc/invoke.texi (AVR Options): Document it. From-SVN: r237825
2016-06-28linux.h: Do not include arch/icache.hWalter Lee3-9/+46
gcc/ChangeLog * config/tilegx/linux.h: Do not include arch/icache.h (CLEAR_INSN_CACHE): Provide inlined definition directly. * config/tilepro/linux.h: Do not include arch/icache.h (CLEAR_INSN_CACHE): Provide inlined definition directly. libgcc/ChangeLog * config/tilepro/atomic.h: Do not include arch/spr_def.h and asm/unistd.h. (SPR_CMPEXCH_VALUE): Define for tilegx. (__NR_FAST_cmpxchg): Define for tilepro. (__NR_FAST_atomic_update): Define for tilepro. (__NR_FAST_cmpxchg64): Define for tilepro. From-SVN: r237824
2016-06-28re PR target/71656 (ICE in reload when generating code for -mcpu=power9 ↵Peter Bergner2-2/+7
-mpower9-dform-vector) PR target/71656 * gcc.target/powerpc/pr71656-2.c: Fix syntax errors. From-SVN: r237823
generated by cgit v1.1 at 2025-08-07 09:47:15 +0000