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2018-08-26frame-header-opt.c: Include "backend.h" rather than "cfg.h"Jeff Law2-1/+6
* config/mips/frame-header-opt.c: Include "backend.h" rather than "cfg.h" From-SVN: r263869
2018-08-27Daily bump.GCC Administrator1-1/+1
From-SVN: r263867
2018-08-26PR c++/87029, Implement -Wredundant-move.Marek Polacek11-9/+391
* c.opt (Wredundant-move): New option. * typeck.c (treat_lvalue_as_rvalue_p): New function. (maybe_warn_pessimizing_move): Call convert_from_reference. Warn about redundant moves. * doc/invoke.texi: Document -Wredundant-move. * g++.dg/cpp0x/Wredundant-move1.C: New test. * g++.dg/cpp0x/Wredundant-move2.C: New test. * g++.dg/cpp0x/Wredundant-move3.C: New test. * g++.dg/cpp0x/Wredundant-move4.C: New test. From-SVN: r263863
2018-08-26re PR c++/87080 (ice in cp_get_fndecl_from_callee, at cp/cvt.c:965)Marek Polacek4-0/+29
PR c++/87080 * typeck.c (maybe_warn_pessimizing_move): Do nothing in a template. * g++.dg/cpp0x/Wpessimizing-move5.C: New test. From-SVN: r263862
2018-08-26Daily bump.GCC Administrator1-1/+1
From-SVN: r263860
2018-08-25re PR fortran/86704 (Segmentation fault when using matmul in combination ↵Thomas Koenig2-0/+30
with transpose) 2018-08-25 Thomas Koenig <tkoenig@gcc.gnu.org> PR libfortran/86704 * m4/matmul_internal.m4: Correct calculation of needed buffer size for arrays of shape (1,n). * generated/matmul_c10.c: Regenerated * generated/matmul_c16.c: Regenerated * generated/matmul_c4.c: Regenerated * generated/matmul_c8.c: Regenerated * generated/matmul_i1.c: Regenerated * generated/matmul_i16.c: Regenerated * generated/matmul_i2.c: Regenerated * generated/matmul_i4.c: Regenerated * generated/matmul_i8.c: Regenerated * generated/matmul_r10.c: Regenerated * generated/matmul_r16.c: Regenerated * generated/matmul_r4.c: Regenerated * generated/matmul_r8.c: Regenerated * generated/matmulavx128_c10.c: Regenerated * generated/matmulavx128_c16.c: Regenerated * generated/matmulavx128_c4.c: Regenerated * generated/matmulavx128_c8.c: Regenerated * generated/matmulavx128_i1.c: Regenerated * generated/matmulavx128_i16.c: Regenerated * generated/matmulavx128_i2.c: Regenerated * generated/matmulavx128_i4.c: Regenerated * generated/matmulavx128_i8.c: Regenerated * generated/matmulavx128_r10.c: Regenerated * generated/matmulavx128_r16.c: Regenerated * generated/matmulavx128_r4.c: Regenerated * generated/matmulavx128_r8.c: Regenerated 2018-08-25 Thomas Koenig <tkoenig@gcc.gnu.org> PR libfortran/86704 * gfortran.dg/matmul_19.f90: New test. From-SVN: r263856
2018-08-25re PR tree-optimization/87059 (internal compiler error: in set_value_range, ↵Martin Sebor3-1/+19
at tree-vrp.c:289) PR tree-optimization/87059 * builtins.c (expand_builtin_strncmp): Convert MIN_EXPR operand to the same type as the other. * fold-const.c (fold_binary_loc): Assert expectation. From-SVN: r263855
2018-08-25re PR fortran/86545 (ICE in transfer_expr on invalid WRITE statement)Janus Weil4-2/+45
fix PR 86545 2018-08-25 Janus Weil <janus@gcc.gnu.org> PR fortran/86545 * resolve.c (resolve_transfer): Correctly determine typespec for generic function calls, in order to throw a proper error. 2018-08-25 Janus Weil <janus@gcc.gnu.org> PR fortran/86545 * gfortran.dg/generic_35.f90: New test case. From-SVN: r263854
2018-08-25Code clean-up on darwin.cIain Sandoe2-8/+6
* config/darwin.c (machopic_legitimize_pic_address): Clean up extraneous parentheses, dead code section and formatting. From-SVN: r263851
2018-08-25Daily bump.GCC Administrator1-1/+1
From-SVN: r263849
2018-08-24diagnostics: tweaks to line-spans vs line numbering (PR 87091)David Malcolm4-35/+137
This patch tweaks how line numbers are printed for a diagnostic containing multiple line spans. With this patch, rather than printing span headers: ../x86_64-pc-linux-gnu/libstdc++-v3/include/vector:87:22: note: message ../x86_64-pc-linux-gnu/libstdc++-v3/include/vector:74:1: ++ |+#include <vector> 74 | #endif ../x86_64-pc-linux-gnu/libstdc++-v3/include/vector:87:22: 87 | using vector = std::vector<_Tp, polymorphic_allocator<_Tp>>; | ^~~ we now print: ../x86_64-pc-linux-gnu/libstdc++-v3/include/vector:87:22: note: message +++ |+#include <vector> 74 | #endif .... 87 | using vector = std::vector<_Tp, polymorphic_allocator<_Tp>>; | ^~~ and for sufficiently close lines, rather than print a gap: + |+#include <stdio.h> 1 | test (int ch) .. 3 | putchar (ch); | ^~~~~~~ we print the line itself: + |+#include <stdio.h> 1 | test (int ch) 2 | { 3 | putchar (ch); | ^~~~~~~ gcc/ChangeLog: PR 87091 * diagnostic-show-locus.c (layout::layout): Ensure the margin is wide enough for jumps in the line-numbering to be visible. (layout::print_gap_in_line_numbering): New member function. (layout::calculate_line_spans): When using line numbering, merge line spans that are only 1 line apart. (diagnostic_show_locus): When printing line numbers, show gaps in line numbering directly, rather than printing headers. (selftest::test_diagnostic_show_locus_fixit_lines): Add test of line-numbering with multiple line spans. (selftest::test_fixit_insert_containing_newline_2): Add test of line-numbering, in which the spans are close enough to be merged. gcc/testsuite/ChangeLog: PR 87091 * gcc.dg/missing-header-fixit-3.c: Update for changes to how line spans are printed with -fdiagnostics-show-line-numbers. From-SVN: r263843
2018-08-24gimple-ssa-evrp-analyze.c (set_ssa_range_info): Pass value_range to ↵Aldy Hernandez5-55/+53
range_includes_zero_p. * gimple-ssa-evrp-analyze.c (set_ssa_range_info): Pass value_range to range_includes_zero_p. Do not special case VR_ANTI_RANGE. * tree-vrp.c (range_is_nonnull): Remove. (range_includes_zero_p): Accept value_range instead of min/max. (extract_range_from_binary_expr_1): Do not early bail on POINTER_PLUS_EXPR. Use range_includes_zero_p instead of range_is_nonnull. (extract_range_from_unary_expr): Use range_includes_zero_p instead of range_is_nonnull. (vrp_meet_1): Pass value_range to range_includes_zero_p. Do not special case VR_ANTI_RANGE. (vrp_finalize): Same. * tree-vrp.h (range_includes_zero_p): Pass value_range as argument instead of min/max. (range_is_nonnull): Remove. * vr-values.c (vrp_stmt_computes_nonzero): Use range_includes_zero_p instead of range_is_nonnull. (extract_range_basic): Pass value_range to range_includes_zero_p instead of range_is_nonnull. From-SVN: r263842
2018-08-24runtime: remove the dummy arg of getcallerspIan Lance Taylor2-6/+2
This is a port of https://golang.org/cl/109596 to the gofrontend, in preparation for updating libgo to 1.11. Original CL description: getcallersp is intrinsified, and so the dummy arg is no longer needed. Remove it, as well as a few dummy args that are solely to feed getcallersp. Reviewed-on: https://go-review.googlesource.com/131116 From-SVN: r263840
2018-08-24re PR fortran/86837 (Optimization breaks an unformatted read with implicit loop)Thomas Koenig4-3/+81
2018-08-24 Thomas Koenig <tkoenig@gcc.gnu.org> PR fortran/86837 * frontend-passes.c (var_in_expr_callback): New function. (var_in_expr): New function. (traverse_io_block): Use var_in_expr instead of gfc_check_dependency for checking if the variable depends on the previous interators. 2018-08-24 Thomas Koenig <tkoenig@gcc.gnu.org> PR fortran/86837 * gfortran.dg/implied_do_io_6.f90: New test. From-SVN: r263838
2018-08-24Add a testcase for PR middle-end/87092H.J. Lu2-0/+15
PR middle-end/87092 * gcc.dg/pr87092.c: New test. From-SVN: r263837
2018-08-24re PR c++/67012 (decltype(auto) with trailing return type)Marek Polacek7-1/+48
PR c++/67012 PR c++/86942 * decl.c (grokdeclarator): Disallow functions with trailing return type with decltype(auto) as its type. Also check the function if it's inner declarator doesn't exist * g++.dg/cpp0x/auto52.C: New test. * g++.dg/cpp1y/auto-fn52.C: New test. * g++.dg/cpp1y/auto-fn53.C: New test. * g++.dg/cpp1y/auto-fn54.C: New test. From-SVN: r263836
2018-08-24emit-rtl.c (init_emit_once): Do not emit MODE_POINTER_BOUNDS RTXes.Uros Bizjak17-280/+102
* emit-rtl.c (init_emit_once): Do not emit MODE_POINTER_BOUNDS RTXes. * emit-rtl.h (rtl_data): Remove return_bnd. * explow.c (trunc_int_for_mode): Do not handle POINTER_BOUNDS_MODE_P. * function.c (diddle_return_value): Do not handle crtl->return_bnd. * genmodes.c (complete_mode): Do not handle MODE_POINTER_BOUNDS. (POINTER_BOUNDS_MODE): Remove definition. (make_pointer_bounds_mode): Remove. (get_mode_class): Do not handle MODE_POINTER_BOUNDS. * machmode.h (POINTER_BOUNDS_MODE_P): Remove definition. (scalare_mode::includes_p): Do not handle MODE_POINTER_BOUNDS. * mode-classes.def: Do not define MODE_POINTER_BOUNDS. * stor-layout.c (int_mode_for_mode): Do not handle MODE_POINTER_BOUNDS. * tree-core.h (enum tree_index): Remove TI_POINTER_BOUNDS_TYPE. * varasm.c (output_constant_pool_2): Do not handle MODE_POINTER_BOUNDS. * config/i386/i386-modes.def (BND32, BND64): Remove. * config/i386/i386.c (dbx_register_map): Remove bound registers. (dbx64_register_map): Ditto. (svr4_dbx_register_map): Ditto. (indirect_thunk_bnd_needed): Remove. (indirect_thunks_bnd_used): Ditto. (indirect_return_bnd_needed): Ditto. (indirect_return_via_cx_bnd): Ditto. (enum indirect_thunk_prefix): Remove indirect_thunk_prefix_bnd. (indirect_thunk_name): Remove handling of indirect_thunk_prefix_bnd. (output_indirect_thunk): Ditto. Remove need_prefix argument. (output_indirect_thunk_function): Remove handling of indirect_return_bnd_needed, indirect_return_via_cx_bnd, indirect_thunk_bnd_needed and indirect_thunks_bnd_used variables. (ix86_save_reg): Remove handling of crtl->return_bnd. (ix86_legitimate_constant_p): Remove handling of POINTER_BOUNDS_MODE_P. (ix86_print_operand_address_as): Remove handling of UNSPEC_BNDMK_ADDR and UNSPEC_BNDLX_ADDR. (ix86_output_indirect_branch_via_reg): Remove handling of indirect_thunk_prefix_bnd. (ix86_output_indirect_branch_via_push): Ditto. (ix86_output_function_return): Ditto. (ix86_output_indirect_function_return): Ditto. (avoid_func_arg_motion): Do not handle UNSPEC_BNDSTX. * config/i386/i386.h (FIXED_REGISTERS): Remove bound registers. (CALL_USED_REGISTERS): Ditto. (REG_ALLOC_ORDER): Update for removal of bound registers. (HI_REGISTER_NAMES): Ditto. * config/i386/i386.md (UNSPEC_BNDMK, UNSPEC_BNDMK_ADDR, UNSPEC_BNDSTX) (UNSPEC_BNDLDX, UNSPEC_BNDLDX_ADDR, UNSPEC_BNDCL, UNSPEC_BNDCU) (UNSPEC_BNDCN, UNSPEC_MPX_FENCE): Remove. (BND0_REG, BND1_REG, BND2_REG, BND3_REG): Remove (FIRST_PSEUDO_REG): Update. (BND): Remove mode iterator. * config/i386/predicates.md (bnd_mem_operator): Remove. From-SVN: r263835
2018-08-24Define vect_perm for variable-length SVERichard Sandiford5-12/+28
Variable-length SVE now supports enough permutes to define vect_perm. The change to vect_perm_supported is currently a no-op because the function is only called with a count of 3. 2018-08-24 Richard Sandiford <richard.sandiford@arm.com> gcc/testsuite/ * lib/target-supports.exp (vect_perm_supported): Only return false for variable-length vectors if the permute size is not a power of 2. (check_effective_target_vect_perm) (check_effective_target_vect_perm_byte) (check_effective_target_vect_perm_short): Remove check for variable-length vectors. * gcc.dg/vect/slp-23.c: Add an XFAIL for variable-length SVE. * gcc.dg/vect/slp-perm-10.c: Likewise. * gcc.dg/vect/slp-perm-9.c: Add an XFAIL for variable-length vectors. From-SVN: r263834
2018-08-24Avoid is_constant calls in vectorizable_bswapRichard Sandiford6-7/+54
The "new" VEC_PERM_EXPR handling makes it easy to support bswap for variable-length vectors. 2018-08-24 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-stmts.c (vectorizable_bswap): Handle variable-length vectors. gcc/testsuite/ * gcc.target/aarch64/sve/bswap_1.c: New test. * gcc.target/aarch64/sve/bswap_2.c: Likewise. * gcc.target/aarch64/sve/bswap_3.c: Likewise. From-SVN: r263833
2018-08-24Handle SLP permutations for variable-length vectorsRichard Sandiford11-68/+281
The SLP code currently punts for all variable-length permutes. This patch makes it handle the easy case of N->N permutes in which the number of vector lanes is a multiple of N. Every permute then uses the same mask, and that mask repeats (with a stride) every N elements. The patch uses the same path for constant-length vectors, since it should be slightly cheaper in terms of compile time. 2018-08-24 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-vect-slp.c (vect_transform_slp_perm_load): Separate out the case in which the permute needs only a single element and repeats for every vector of the result. Extend that case to handle variable-length vectors. * tree-vect-stmts.c (vectorizable_load): Update accordingly. gcc/testsuite/ * gcc.target/aarch64/sve/slp_perm_1.c: New test. * gcc.target/aarch64/sve/slp_perm_2.c: Likewise. * gcc.target/aarch64/sve/slp_perm_3.c: Likewise. * gcc.target/aarch64/sve/slp_perm_4.c: Likewise. * gcc.target/aarch64/sve/slp_perm_5.c: Likewise. * gcc.target/aarch64/sve/slp_perm_6.c: Likewise. * gcc.target/aarch64/sve/slp_perm_7.c: Likewise. From-SVN: r263832
2018-08-24DWARF: Call set_indirect_string on DW_MACINFO_start_fileH.J. Lu4-0/+35
Since -gsplit-dwarf -g3 will output filename as indirect string, call set_indirect_string on DW_MACINFO_start_file for -gsplit-dwarf -g3. gcc/ PR debug/79342 * dwarf2out.c (save_macinfo_strings): Call set_indirect_string on DW_MACINFO_start_file for -gsplit-dwarf -g3. gcc/testsuite/ PR debug/79342 * gcc.dg/pr79342.: New test. From-SVN: r263831
2018-08-24cfg.h (struct control_flow_graph): Add edge_flags_allocated and ↵Richard Biener10-43/+94
bb_flags_allocated members. 2018-08-24 Richard Biener <rguenther@suse.de> * cfg.h (struct control_flow_graph): Add edge_flags_allocated and bb_flags_allocated members. (auto_flag): New RAII class for allocating flags. (auto_edge_flag): New RAII class for allocating edge flags. (auto_bb_flag): New RAII class for allocating bb flags. * cfgloop.c (verify_loop_structure): Allocate temporary edge flag dynamically. * cfganal.c (dfs_enumerate_from): Remove use of visited sbitmap in favor of temporarily allocated BB flag. * hsa-brig.c: Re-order includes. * hsa-dump.c: Likewise. * hsa-regalloc.c: Likewise. * print-rtl.c: Likewise. * profile-count.c: Likewise. From-SVN: r263830
2018-08-24rs6000: Check that the base of a TOCREL is the TOC (PR86989)Segher Boessenkool2-1/+9
There currently is nothing that prevents replacing the TOC_REGISTER in a TOCREL unspec with something else, like a pseudo, or a memory ref. This of course does not work. Fix that. Tested on powerpc64-linux {-m32,-m64}; committing. Segher 2018-08-24 Segher Boessenkool <segher@kernel.crashing.org> PR target/86989 * config/rs6000/rs6000.c (toc_relative_expr_p): Check that the base is the TOC register. --- gcc/config/rs6000/rs6000.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a967912..ed33912 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7932,7 +7932,9 @@ toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret, *tocrel_offset_ret = tocrel_offset; return (GET_CODE (tocrel_base) == UNSPEC - && XINT (tocrel_base, 1) == UNSPEC_TOCREL); + && XINT (tocrel_base, 1) == UNSPEC_TOCREL + && REG_P (XVECEXP (tocrel_base, 0, 1)) + && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER); } /* Return true if X is a constant pool address, and also for cmodel=medium -- 1.8.3.1 From-SVN: r263829
2018-08-24PR 87073/bootstrapAldy Hernandez2-8/+11
PR 87073/bootstrap * wide-int-range.cc (wide_int_range_div): Do not ignore result from wide_int_range_multiplicative_op. From-SVN: r263828
2018-08-24Daily bump.GCC Administrator1-1/+1
From-SVN: r263827
2018-08-23PR tree-optimization/87072 - false warning: array subscript is above array ↵Martin Sebor2-0/+20
bounds gcc/testsuite/ChangeLog: * gcc.dg/Warray-bounds-35.c: New test. From-SVN: r263822
2018-08-23tree-vect-data-refs.c (vect_grouped_store_supported): Fix typo "permutaion".Prathamesh Kulkarni2-1/+6
2018-08-23 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> * tree-vect-data-refs.c (vect_grouped_store_supported): Fix typo "permutaion". From-SVN: r263819
2018-08-23Fix typo 'exapnded' to 'expanded'Giuliano Belinassi4-2/+11
2018-08-23 Giuliano Belinassi <giuliano.belinassi@usp.br> gcc/ * genmatch.c (parser::parse_operation): Fix typo 'exapnded' to 'expanded'. gcc/ada/ * exp_unst.ads: Fix typo 'exapnded' to 'expanded'. From-SVN: r263818
2018-08-23scev: dump final value replacement expressionsAlexander Monakov2-1/+8
* tree-scalar-evolution.c (final_value_replacement_loop): Dump full GENERIC expression used for replacement. From-SVN: r263817
2018-08-23tree-vrp.c (abs_extent_range): Remove.Aldy Hernandez4-141/+168
* tree-vrp.c (abs_extent_range): Remove. (extract_range_into_wide_ints): Pass wide ints by reference. (extract_range_from_binary_expr_1): Rewrite the *DIV_EXPR code. Pass wide ints by reference in all calls to extract_range_into_wide_ints. * wide-int-range.cc (wide_int_range_div): New. * wide-int-range.h (wide_int_range_div): New. (wide_int_range_includes_zero_p): New. (wide_int_range_zero_p): New. From-SVN: r263813
2018-08-23[AARCH64] use "arch_enabled" attribute for aarch64.Matthew Malcomson3-94/+113
arm.md has some attributes "arch" and "arch_enabled" to aid enabling and disabling insn alternatives based on the architecture being targeted. This patch introduces a similar attribute in the aarch64 backend. The new attribute will be used to enable a new alternative for the atomic_store insn in a future patch, but is an atomic change in itself. The new attribute has values "any", "fp", "fp16", "simd", and "sve". These attribute values have been taken from the pre-existing attributes "fp", "fp16", "simd", and "sve". The standalone "fp" attribute has been reintroduced in terms of the "arch" attribute as it's needed for the xgene1.md scheduling file -- the use in this file can't be changed to check for `(eq_attr "arch" "fp")` as the file is reused by the arm.md machine description whose 'arch' attribute doesn't have an 'fp' value. 2018-08-23 Matthew Malcomson <matthew.malcomson@arm.com> * config/aarch64/aarch64.md (arches): New enum. (arch): New enum attr. (arch_enabled): New attr. (enabled): Now uses arch_enabled only. (simd, sve, fp16): Removed attribute. (fp): Attr now defined in terms of 'arch'. (*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64, *movti_aarch64, *movhf_aarch64, <optab><fcvt_target><GPF:mode>2, <FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3, <FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3): Merge 'fp' and 'simd' attributes into 'arch'. (*movsf_aarch64, *movdf_aarch64, *movtf_aarch64, *add<mode>3_aarch64, subdi3, neg<mode>2, <optab><mode>3, one_cmpl<mode>2, *<NLOGICAL:optab>_one_cmpl<mode>3, *xor_one_cmpl<mode>3, *aarch64_ashl_sisd_or_int_<mode>3, *aarch64_lshr_sisd_or_int_<mode>3, *aarch64_ashr_sisd_or_int_<mode>3, *aarch64_sisd_ushl): Convert use of 'simd' attribute into 'arch'. (load_pair_sw_<SX:mode><SX2:mode>, load_pair_dw_<DX:mode><DX2:mode>, store_pair_sw_<SX:mode><SX2:mode>, store_pair_dw_<DX:mode><DX2:mode>): Convert use of 'fp' attribute to 'arch'. * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>, move_lo_quad_internal_<mode>): (different modes) Merge 'fp' and 'simd' into 'arch'. (move_lo_quad_internal_be_<mode>, move_lo_quad_internal_be_<mode>): (different modes) Merge 'fp' and 'simd' into 'arch'. (*aarch64_combinez<mode>, *aarch64_combinez_be<mode>): Merge 'fp' and 'simd' into 'arch'. From-SVN: r263811
2018-08-23Fix recent bug in canonicalize_comparison (PR87026)Segher Boessenkool2-0/+10
The new code testing which way a comparison is best expressed creates a pseudoregister (by hand) and creates some insns with that. Such insns will no longer recog() when pseudo-registers are no longer aloowed (after reload). But we have an ifcvt pass after reload (ce3). This patch simply returns if we cannot create pseudos. PR rtl-optimization/87026 * expmed.c (canonicalize_comparison): If we can no longer create pseudoregisters, don't. From-SVN: r263810
2018-08-23PR target/86951 arm - Handle speculation barriers on pre-armv7 CPUsRichard Earnshaw4-6/+41
The AArch32 instruction sets prior to Armv7 do not define the ISB and DSB instructions that are needed to form a speculation barrier. While I do not know of any instances of cores based on those instruction sets being vulnerable to speculative side channel attacks it is possible to run code built for those ISAs on more recent hardware where they would become vulnerable. This patch works around this by using a library call added to libgcc. That code can then take any platform-specific actions necessary to ensure safety. For the moment I've only handled two cases: the library code being built for armv7 or later anyway and running on Linux. On Linux we can handle this by calling the kernel function that will flush a small amount of cache. Such a sequence ends with a ISB+DSB sequence if running on an Armv7 or later CPU. gcc: PR target/86951 * config/arm/arm-protos.h (arm_emit_speculation_barrier): New prototype. * config/arm/arm.c (speculation_barrier_libfunc): New static variable. (arm_init_libfuncs): Initialize it. (arm_emit_speculation_barrier): New function. * config/arm/arm.md (speculation_barrier): Call arm_emit_speculation_barrier for architectures that do not have DSB or ISB. (speculation_barrier_insn): Only match on Armv7 or later. libgcc: PR target/86951 * config/arm/lib1funcs.asm (speculation_barrier): New function. * config/arm/t-arm (LIB1ASMFUNCS): Add it to list of functions to build. From-SVN: r263806
2018-08-23re PR ipa/87024 (ICE in fold_stmt_1)Richard Biener4-1/+32
2018-08-23 Richard Biener <rguenther@suse.de> PR middle-end/87024 * tree-inline.c (copy_bb): Drop unused __builtin_va_arg_pack_len calls. * gcc.dg/pr87024.c: New testcase. From-SVN: r263805
2018-08-23[AArch64] Improve SVE handling of single-vector permutesRichard Sandiford7-12/+26
aarch64_vectorize_vec_perm_const was failing to set one_vector_p if the permute had only a single input. This in turn was hiding a problem in the SVE TBL handling: it accepted single-vector variable-length permutes, but sent them through the general two-vector aarch64_expand_sve_vec_perm, which is only set up to handle constant-length permutes. 2018-08-23 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_evpc_sve_tbl): Fix handling of single-vector TBLs. (aarch64_vectorize_vec_perm_const): Set one_vector_p when only one input is given. gcc/testsuite/ * gcc.dg/vect/no-vfa-vect-depend-2.c: Remove XFAIL. * gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise. * gcc.dg/vect/pr65947-13.c: Update for vect_fold_extract_last. * gcc.dg/vect/pr80631-2.c: Likewise. From-SVN: r263804
2018-08-23Fix aarch64_evpc_tbl guard (PR 85910)Richard Sandiford2-1/+7
This patch fixes a typo in aarch64_expand_vec_perm_const_1 that I introduced as part of the SVE changes. I don't know of any cases in which it has any practical effect, since we'll eventually try to use TBL as a variable permute instead. Having the code is still an important part of defining the interface properly and so we shouldn't simply drop it. 2018-08-23 Richard Sandiford <richard.sandiford@arm.com> gcc/ PR target/85910 * config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Fix aarch64_evpc_tbl guard. From-SVN: r263803
2018-08-23Signed zero for {max,min}val intrinsicsJanne Blomqvist2-21/+12
The Fortran standard specifies (e.g. F2018 7.4.3.2) that intrinsic procedures shall treat positive and negative real zero as equivalent, unless it is explicitly specified otherwise. For {max,min}val there is no such explicit mention. Thus, remove code to handle signed zeros. 2018-08-23 Janne Blomqvist <blomqvist.janne@gmail.com> * trans-intrinsic.c (gfc_conv_intrinsic_minmaxval): Delete HONOR_SIGNED_ZEROS checks. From-SVN: r263802
2018-08-23re PR fortran/86863 ([OOP][F2008] type-bound module procedure name not ↵Paul Thomas4-3/+84
recognized) 2017-08-23 Paul Thomas <pault@gcc.gnu.org> PR fortran/86863 * resolve.c (resolve_typebound_call): If the TBP is not marked as a subroutine, check the specific symbol. 2017-08-23 Paul Thomas <pault@gcc.gnu.org> PR fortran/86863 * gfortran.dg/submodule_32.f08: New test. From-SVN: r263799
2018-08-23Daily bump.GCC Administrator1-1/+1
From-SVN: r263798
2018-08-22tree-ssa-dse.c (compute_trims): Avoid folding away undefined behaviour.Bernd Edlinger2-0/+12
* tree-ssa-dse.c (compute_trims): Avoid folding away undefined behaviour. From-SVN: r263793
2018-08-22gfortran.texi: Mention that asynchronous I/O does not work on systems which ↵Thomas Koenig2-1/+8
lack condition... 2018-08-22 Thomas Koenig <tkoenig@gcc.gnu.org> * gfortran.texi: Mention that asynchronous I/O does not work on systems which lack condition variables, such as AIX. 2018-08-22 Thomas Koenig <tkoenig@gcc.gnu.org> * async.h: Set ASYNC_IO to zero if _AIX is defined. (struct adv_cond): If ASYNC_IO is zero, the struct has no members. (async_unit): If ASYNC_IO is zero, remove unneeded members. From-SVN: r263788
2018-08-22re PR fortran/86935 (Bad locus in ASSOCIATE statement)Janus Weil5-9/+44
fix PR 86935 2018-08-22 Janus Weil <janus@gcc.gnu.org> PR fortran/86935 * match.c (gfc_match_associate): Improve diagnostics for the ASSOCIATE statement. 2018-08-22 Janus Weil <janus@gcc.gnu.org> PR fortran/86935 * gfortran.dg/associate_3.f90: Update error message. * gfortran.dg/associate_39.f90: New test case. From-SVN: r263787
2018-08-22module.c (load_generic_interfaces): Move call to find_symbol() so that only ↵Andrew Benson2-3/+8
occurs if actually needed. 2018-08-22 Andrew Benson <abensonca@gmail.com> * module.c (load_generic_interfaces): Move call to find_symbol() so that only occurs if actually needed. From-SVN: r263784
2018-08-22re PR fortran/86888 ([F08] allocatable components of indirectly recursive type)Janus Weil11-32/+52
fix PR 86888 2018-08-22 Janus Weil <janus@gcc.gnu.org> PR fortran/86888 * decl.c (gfc_match_data_decl): Allow allocatable components of indirectly recursive type. * resolve.c (resolve_component): Remove two errors messages ... (resolve_fl_derived): ... and replace them by a new one. 2018-08-22 Janus Weil <janus@gcc.gnu.org> PR fortran/86888 * gfortran.dg/alloc_comp_basics_6.f90: Update an error message and add an additional case. * gfortran.dg/alloc_comp_basics_7.f90: New test case. * gfortran.dg/class_17.f03: Update error message. * gfortran.dg/class_55.f90: Ditto. * gfortran.dg/dtio_11.f90: Update error messages. * gfortran.dg/implicit_actual.f90: Add an error message. * gfortran.dg/typebound_proc_12.f90: Update error message. From-SVN: r263782
2018-08-22PR middle-end/87052 - STRING_CST printing incomplete in Gimple dumpsMartin Sebor5-48/+77
gcc/testsuite/ChangeLog: PR middle-end/87052 * gcc.dg/pr87052.c: New test. * gcc.dg/tree-ssa/dump-3.c: Adjust. gcc/ChangeLog: PR middle-end/87052 * tree-pretty-print.c (pretty_print_string): Add argument. (dump_generic_node): Call to pretty_print_string with string size. From-SVN: r263781
2018-08-22[ fix changelog ]Segher Boessenkool1-0/+1
2018-08-22 Segher Boessenkool <segher@kernel.crashing.org> PR rtl-optimization/86771 * combine.c (try_combine): Do not allow splitting a resulting PARALLEL of two SETs into those two SETs, one to be placed at i2, if that SETs destination is modified between i2 and i3. From-SVN: r263780
2018-08-22Change AArch64 specific FMAX/FMIN tests into generic MAX_EXPR/MIN_EXPR testsSzabolcs Nagy3-4/+11
gfortran now always uses MAX_EXPR/MIN_EXPR for MAX/MIN intrinsics, so the AArch64 specific FMAX/FMIN tests are no longer valid. 2018-08-22 Szabolcs Nagy <szabolcs.nagy@arm.com> * gfortran.dg/max_fmax_aarch64.f90: Rename to... * gfortran.dg/max_expr.f90: ...this. * gfortran.dg/min_fmin_aarch64.f90: Rename to... * gfortran.dg/min_expr.f90: ...this. From-SVN: r263778
2018-08-22combine: Do another check before splitting a parallel (PR86771)Segher Boessenkool2-2/+14
When combine splits a resulting parallel into its two SETs, it has to place one at i2, and the other stays at i3. This does not work if the destination of the SET that will be placed at i2 is modified between i2 and i3. This patch fixes it. * combine.c (try_combine): Do not allow splitting a resulting PARALLEL of two SETs into those two SETs, one to be placed at i2, if that SETs destination is modified between i2 and i3. From-SVN: r263776
2018-08-22[2/2] Fix bogus inner induction (PR 86725)Richard Sandiford7-0/+145
This patch is the second part of the fix for PR 86725. The problem in the original test is that for: outer1: x_1 = PHI <x_4(outer2), ...>; ... inner: x_2 = PHI <x_1(outer1), x_3(...)>; ... x_3 = ...; ... outer2: x_4 = PHI <x_3(inner)>; ... there are corner cases in which it is possible to classify the inner phi as an induction but not the outer phi. The -4.c test is a more direct example. After failing to classify x_1 as an induction, we go on to classify it as a double reduction (which is basically true). But we still classified the inner phi as an induction rather than as part of a reduction, leading to an ICE when trying to vectorise the outer phi. We analyse the phis for outer loops first, so the simplest fix is not to classify the phi as an induction if outer loop analysis said that it should be a reduction. The -2.c test is from the original PR. The -3.c test is a version in which "wo" really is used a reduction; this was already correctly rejected, but for the wrong reason ("inner-loop induction only used outside of the outer vectorized loop"). The -4.c test is another way of tickling the original problem without relying on the undefinedness of signed overflow. The -5.c test shows an (uninteresting) example in which the patch prevents a spurious failure to vectorise the outer loop. 2018-08-22 Richard Sandiford <richard.sandiford@arm.com> gcc/ PR tree-optimization/86725 * tree-vect-loop.c (vect_inner_phi_in_double_reduction_p): New function. (vect_analyze_scalar_cycles_1): Check it. gcc/testsuite/ PR tree-optimization/86725 * gcc.dg/vect/no-scevccp-pr86725-2.c: New test. * gcc.dg/vect/no-scevccp-pr86725-3.c: Likewise. * gcc.dg/vect/no-scevccp-pr86725-4.c: Likewise. * gcc.dg/vect/no-scevccp-pr86725-5.c: Likewise. From-SVN: r263774
2018-08-22[1/2] Fix bogus double reduction (PR 86725)Richard Sandiford4-0/+39
This patch is the first part of the fix for PR 86725. We would treat x_1 in: outer1: x_1 = PHI <x_4(outer2), ...>; ... inner: x_2 = ...x_1...; ... x_3 = ...; ... outer2: x_4 = PHI <x_3(inner)>; ... as a double reduction without checking what kind of statement x_2 is. In practice it has to be a phi, since for other x_2, x_1 would simply be a loop invariant that gets used for every inner loop iteration. The idea with doing this patch first is that, by checking x_2 really is a phi, we can hand off the validation of the rest of the reduction to the phi analysis in the inner loop. The test case is a variant of the one in the PR. 2018-08-22 Richard Sandiford <richard.sandiford@arm.com> gcc/ PR tree-optimization/86725 * tree-vect-loop.c (vect_is_simple_reduction): When treating an outer loop phi as a double reduction, make sure that the single user of the phi result is an inner loop phi. gcc/testsuite/ PR tree-optimization/86725 * gcc.dg/vect/no-scevccp-pr86725-1.c: New test. From-SVN: r263773
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