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2020-04-01Fix PR94043 by making vect_live_op generate lc-phiKewen Lin4-6/+73
As PR94043 shows, my commit r10-4524 exposed one issue in vectorizable_live_operation, which inserts one extra BB before the single exit, leading unexpected operand expansion and unexpected loop depth assertion. As Richi suggested, this patch is to teach vectorizable_live_operation to generate loop closed phi for vec_lhs, it looks like: loop; # lhs' = PHI <lhs> => loop; # vec_lhs' = PHI <vec_lhs> new_tree = BIT_FIELD_REF <vec_lhs', ...>; lhs' = new_tree; I noticed that there are some SLP cases that have same lhs and vec_lhs but different offsets, which can make us have more PHIs for the same vec_lhs there. But I think it would be fine since only one of them is actually live, the others should be eliminated by the following dce. So the patch doesn't check whether there is one phi for vec_lhs, just create one directly instead. Bootstrapped/regtested on powerpc64le-linux-gnu (LE) P8. 2020-04-01 Kewen Lin <linkw@gcc.gnu.org> gcc/ChangeLog PR tree-optimization/94043 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed phi for vec_lhs and use it for lane extraction. gcc/testsuite/ChangeLog PR tree-optimization/94043 * gfortran.dg/graphite/vect-pr94043.f90: New test.
2020-04-01c++: Fix DMI with lambda 'this' capture [PR94205]Jason Merrill6-2/+49
We represent 'this' in a default member initializer with a PLACEHOLDER_EXPR. Normally in constexpr evaluation when we encounter one it refers to ctx->ctor, but when we're creating a temporary of class type, that replaces ctx->ctor, so a PLACEHOLDER_EXPR that refers to the type of the member being initialized needs to be replaced before that happens. gcc/cp/ChangeLog 2020-03-31 Jason Merrill <jason@redhat.com> PR c++/94205 * constexpr.c (cxx_eval_constant_expression) [TARGET_EXPR]: Call replace_placeholders. * typeck2.c (store_init_value): Fix arguments to fold_non_dependent_expr.
2020-04-01c++: Adjust formatting.Jason Merrill2-49/+60
This patch has no semantic effect; committing it separately makes the change for 94205 easier to read. gcc/cp/ChangeLog 2020-03-31 Jason Merrill <jason@redhat.com> * constexpr.c (cxx_eval_constant_expression) [TARGET_EXPR]: Use local variables.
2020-04-01Daily bump.GCC Administrator1-1/+1
2020-04-01d: Merge UDAs between function prototype and definitions (PR90136)Iain Buclaw11-51/+146
This change fixes the symbol merging in get_symbol_decl to also consider prototypes. This allows the ability to set user defined attributes on the prototype of a function, which then get applied to the definition, if found later in the compilation. The lowering of UDAs to GCC attributes has been commonized into a single function called apply_user_attributes. gcc/d/ChangeLog: PR d/90136 * d-attribs.cc: Include dmd/attrib.h. (build_attributes): Redeclare as static. (apply_user_attributes): New function. * d-tree.h (class UserAttributeDeclaration): Remove. (build_attributes): Remove. (apply_user_attributes): Declare. (finish_aggregate_type): Remove attrs argument. * decl.cc (get_symbol_decl): Merge declaration prototypes with definitions. Use apply_user_attributes. * modules.cc (layout_moduleinfo_fields): Remove last argument to finish_aggregate_type. * typeinfo.cc (layout_classinfo_interfaces): Likewise. * types.cc (layout_aggregate_members): Likewise. (finish_aggregate_type): Remove attrs argument. (TypeVisitor::visit (TypeEnum *)): Use apply_user_attributes. (TypeVisitor::visit (TypeStruct *)): Remove last argument to finish_aggregate_type. Use apply_user_attributes. (TypeVisitor::visit (TypeClass *)): Likewise. gcc/testsuite/ChangeLog: PR d/90136 * gdc.dg/pr90136a.d: New test. * gdc.dg/pr90136b.d: New test. * gdc.dg/pr90136c.d: New test.
2020-03-31d: Add always_inline to the internal attribute table.Iain Buclaw2-0/+21
This attribute is not directly accessible from user code, rather it is indirectly added from the @forceinline attribute. Even so, a handler should be present for it to prevent false positive warnings. Said warnings are not something that could happen currently, but will become a problem from fixing PR90136 later. gcc/d/ChangeLog: * d-attribs.cc (d_langhook_common_attribute_table): Add always_inline. (handle_always_inline_attribute): New function.
2020-03-31libgccjit: add new version entry pointAndreaCorallo9-1/+179
gcc/jit/ChangeLog 2020-03-31 Andrea Corallo <andrea.corallo@arm.com> David Malcolm <dmalcolm@redhat.com> * docs/topics/compatibility.rst (LIBGCCJIT_ABI_13): New ABI tag plus add version paragraph. * libgccjit++.h (namespace gccjit::version): Add new namespace. * libgccjit.c (gcc_jit_version_major, gcc_jit_version_minor) (gcc_jit_version_patchlevel): New functions. * libgccjit.h (LIBGCCJIT_HAVE_gcc_jit_version): New macro. (gcc_jit_version_major, gcc_jit_version_minor) (gcc_jit_version_patchlevel): New functions. * libgccjit.map (LIBGCCJIT_ABI_13) New ABI tag. gcc/testsuite/ChangeLog 2020-03-31 Andrea Corallo <andrea.corallo@arm.com> * jit.dg/test-version.c: New testcase. * jit.dg/all-non-failing-tests.h: Add test-version.c.
2020-03-31d: Use memset to fill alignment holes with zeroes.Iain Buclaw5-47/+49
This patch removes the manual insertion of padding for fields in constructed struct literals, and instead uses memset() on the declaration being initialized. When compiling optimized builds, the intent is usually missed, and alignment holes end up with non-zero values in them anyway. gcc/d/ChangeLog: PR d/94424 * d-codegen.cc (build_alignment_field): Remove. (build_struct_literal): Don't insert alignment padding. * expr.cc (ExprVisitor::visit (AssignExp *)): Call memset before assigning struct literals. gcc/testsuite/ChangeLog: PR d/94424 * gdc.dg/pr94424.d: New test.
2020-03-31vect: ICE: in vectorizable_load, at tree-vect-stmts.c:9173 [PR94398]Felix Yang4-4/+53
In the testcase for PR94398, we're trying to compute: alignment_support_scheme = vect_supportable_dr_alignment (first_dr_info, false); gcc_assert (alignment_support_scheme); even for VMAT_GATHER_SCATTER, which always accesses individual elements. Here we should set alignment_support_scheme to dr_unaligned_supported the gather/scatter case instead of calling vect_supportable_dr_alignment. 2020-03-31 Felix Yang <felix.yang@huawei.com> gcc/ PR tree-optimization/94398 * tree-vect-stmts.c (vectorizable_store): Instead of calling vect_supportable_dr_alignment, set alignment_support_scheme to dr_unaligned_supported for gather-scatter accesses. (vectorizable_load): Likewise. gcc/testsuite/ PR tree-optimization/94398 * gcc.target/aarch64/pr94398.c: New test.
2020-03-31d: Use d_comdat_linkage on generated internal decl.Iain Buclaw2-1/+6
This adds weak linkage to internal TypeInfo data on top of the existing DECL_COMDAT, which helps in the unlikely event that two of the same TypeInfo data ends up in multiple places. gcc/d/ChangeLog: * typeinfo.cc (TypeInfoVisitor::internal_reference): Call d_comdat_linkage on generated decl.
2020-03-31amdgcn: generalize vector insn modesAndrew Stubbs2-660/+805
Replace all relevant explicit uses of V64 vectors with an iterator (albeit with only one entry). This is prerequisite to adding extra vector lengths. The changes are purely mechanical: comparing the mddump files from before and after shows only white-space differences and the use of GET_MODE_NUNITS. 2020-03-31 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF): New mode iterators. (vnsi, VnSI, vndi, VnDI): New mode attributes. (mov<mode>): Use <VnDI> in place of V64DI. (mov<mode>_exec): Likewise. (mov<mode>_sgprbase): Likewise. (reload_out<mode>): Likewise. (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64. (gather_load<mode>v64si): Rename to ... (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI, and <VnDI> in place of V64DI. (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI. (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI. (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>. (scatter_store<mode>v64si): Rename to ... (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>. (scatter<mode>_insn_1offset<exec_scatter>): Likewise. (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise. (scatter<mode>_insn_2offsets<exec_scatter>): Likewise. (ds_bpermute<mode>): Use <VnSI>. (addv64si3_vcc<exec_vcc>): Rename to ... (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI. (addv64si3_vcc_dup<exec_vcc>): Rename to ... (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI. (addcv64si3<exec_vcc>): Rename to ... (addc<mode>3<exec_vcc>): ... this, and use V_SI. (subv64si3_vcc<exec_vcc>): Rename to ... (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI. (subcv64si3<exec_vcc>): Rename to ... (subc<mode>3<exec_vcc>): ... this, and use V_SI. (addv64di3): Rename to ... (add<mode>3): ... this, and use V_DI. (addv64di3_exec): Rename to ... (add<mode>3_exec): ... this, and use V_DI. (subv64di3): Rename to ... (sub<mode>3): ... this, and use V_DI. (subv64di3_exec): Rename to ... (sub<mode>3_exec): ... this, and use V_DI. (addv64di3_zext): Rename to ... (add<mode>3_zext): ... this, and use V_DI and <VnSI>. (addv64di3_zext_exec): Rename to ... (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup): Rename to ... (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup_exec): Rename to ... (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup2): Rename to ... (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup2_exec): Rename to ... (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. (addv64di3_sext_dup2): Rename to ... (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>. (addv64di3_sext_dup2_exec): Rename to ... (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>. (<su>mulv64si3_highpart<exec>): Rename to ... (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>. (mulv64di3): Rename to ... (mul<mode>3): ... this, and use V_DI and <VnSI>. (mulv64di3_exec): Rename to ... (mul<mode>3_exec): ... this, and use V_DI and <VnSI>. (mulv64di3_zext): Rename to ... (mul<mode>3_zext): ... this, and use V_DI and <VnSI>. (mulv64di3_zext_exec): Rename to ... (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. (mulv64di3_zext_dup2): Rename to ... (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. (mulv64di3_zext_dup2_exec): Rename to ... (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. (<expander>v64di3): Rename to ... (<expander><mode>3): ... this, and use V_DI and <VnSI>. (<expander>v64di3_exec): Rename to ... (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>. (<expander>v64si3<exec>): Rename to ... (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. (v<expander>v64si3<exec>): Rename to ... (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. (<expander>v64si3<exec>): Rename to ... (<expander><vnsi>3<exec>): ... this, and use V_SI. (subv64df3<exec>): Rename to ... (sub<mode>3<exec>): ... this, and use V_DF. (truncv64di<mode>2): Rename to ... (trunc<vndi><mode>2): ... this, and use <VnDI>. (truncv64di<mode>2_exec): Rename to ... (trunc<vndi><mode>2_exec): ... this, and use <VnDI>. (<convop><mode>v64di2): Rename to ... (<convop><mode><vndi>2): ... this, and use <VnDI>. (<convop><mode>v64di2_exec): Rename to ... (<convop><mode><vndi>2_exec): ... this, and use <VnDI>. (vec_cmp<u>v64qidi): Rename to ... (vec_cmp<u><mode>di): ... this, and use <VnSI>. (vec_cmp<u>v64qidi_exec): Rename to ... (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>. (vcond_mask_<mode>di): Use <VnDI>. (maskload<mode>di): Likewise. (maskstore<mode>di): Likewise. (mask_gather_load<mode>v64si): Rename to ... (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. (mask_scatter_store<mode>v64si): Rename to ... (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. (*<reduc_op>_dpp_shr_v64di): Rename to ... (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. (*plus_carry_in_dpp_shr_v64si): Rename to ... (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI. (*plus_carry_dpp_shr_v64di): Rename to ... (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. (vec_seriesv64si): Rename to ... (vec_series<mode>): ... this, and use V_SI. (vec_seriesv64di): Rename to ... (vec_series<mode>): ... this, and use V_DI.
2020-03-31arc: Update operand printingClaudiu Zissulescu2-3/+8
Use HOST_WIDE_INT_PRINT_DEC macro instead of %ld for format printing. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_print_operand): Use HOST_WIDE_INT_PRINT_DEC macro.
2020-03-31arc: Cleanup compilation warningClaudiu Zissulescu2-4/+8
gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
2020-03-31[ARM][PATCH]: Add MVE ACLE intrinsics vbicq_n_* polymorphic variant support.Srinath Parvathaneni7-4/+49
For the following MVE ACLE intrinsics, polymorphic variant support is missing on the trunk. vbicq_n_s16, vbicq_n_s32, vbicq_n_u16 and vbicq_n_u32. This patch add the polymorphic variant support for above intrinsics. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic variant. (__arm_vbicq): Likewise. 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Modify. * gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
2020-03-31arc: Allow more ABIs in GLIBC_DYNAMIC_LINKERClaudiu Zissulescu2-1/+6
Enable big-endian suffixed dynamic linker per glibc multi-abi support. And to avoid a future churn and version pairingi hassles, also allow arc700 although glibc for ARC currently doesn't support it. gcc/ xxxx-xx-xx Vineet Gupta <vgupta@synopsys.com> * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
2020-03-31[ARM][PATCH]: Add support for MVE ACLE intrinsics polymorphic variants for ↵Srinath Parvathaneni25-686/+781
+mve.fp option. For the following MVE ACLE intrinsics, polymorphic variant supports only +mve option, support for +mve.fp is missing. vabavq_p_s16, vabavq_p_s32, vabavq_p_s8, vabavq_p_u16, vabavq_p_u32, vabavq_p_u8, vabavq_s16, vabavq_s32, vabavq_s8, vabavq_u16, vabavq_u32, vabavq_u8, vaddlvaq_p_s32, vaddlvaq_p_u32, vaddlvaq_s32, vaddlvaq_u32, vaddlvq_p_s32, vaddlvq_p_u32, vaddlvq_u32, vaddvaq_p_s16, vaddvaq_p_s32, vaddvaq_p_s8, vaddvaq_p_u16, vaddvaq_p_u32, vaddvaq_p_u8, vaddvaq_s16, vaddvaq_s32, vaddvaq_s8, vaddvaq_u16, vaddvaq_u32, vaddvaq_u8, vaddvq_p_s16, vaddvq_p_s32, vaddvq_p_s8, vaddvq_p_u16, vaddvq_p_u32, vaddvq_p_u8, vaddvq_s8, vaddvq_u16, vaddvq_u32, vaddvq_u8, vcmpcsq_m_n_u16, vcmpcsq_m_n_u32, vcmpcsq_m_n_u8, vcmpcsq_m_u16, vcmpcsq_m_u32, vcmpcsq_m_u8, vcmpcsq_n_u16, vcmpcsq_n_u32, vcmpcsq_n_u8, vcmpcsq_u16, vcmpcsq_u32, vcmpcsq_u8, vcmpeqq_n_f16, vcmpeqq_n_f32, vcmpgeq_m_n_s16, vcmpgeq_m_n_s32, vcmpgeq_m_n_s8, vcmpgtq_m_n_f16, vcmpgtq_m_n_f32, vcmpgtq_n_f16, vcmpgtq_n_f32, vcmphiq_m_n_u16, vcmphiq_m_n_u32, vcmphiq_m_n_u8, vcmphiq_m_u16, vcmphiq_m_u32, vcmphiq_m_u8, vcmphiq_n_u16, vcmphiq_n_u32, vcmphiq_n_u8, vcmphiq_u16, vcmphiq_u32, vcmphiq_u8, vcmpleq_m_n_f16, vcmpleq_m_n_f32, vcmpleq_n_f16, vcmpleq_n_f32, vcmpltq_m_n_f16, vcmpltq_m_n_f32, vcmpneq_m_n_f16, vcmpneq_m_n_f32, vcmpneq_n_f16, vcmpneq_n_f32, vmaxavq_p_s16, vmaxavq_p_s32, vmaxavq_p_s8, vmaxavq_s16, vmaxavq_s32, vmaxavq_s8, vmaxq_x_s16, vmaxq_x_s32, vmaxq_x_s8, vmaxq_x_u16, vmaxq_x_u32, vmaxq_x_u8, vmaxvq_p_s16, vmaxvq_p_s32, vmaxvq_p_s8, vmaxvq_p_u16, vmaxvq_p_u32, vmaxvq_p_u8, vmaxvq_s16, vmaxvq_s32, vmaxvq_s8, vmaxvq_u16, vmaxvq_u32, vmaxvq_u8, vminavq_p_s16, vminavq_p_s32, vminavq_p_s8, vminavq_s16, vminavq_s32, vminavq_s8, vminq_x_s16, vminq_x_s32, vminq_x_s8, vminq_x_u16, vminq_x_u32, vminq_x_u8, vminvq_p_s16, vminvq_p_s32, vminvq_p_s8, vminvq_p_u16, vminvq_p_u32, vminvq_p_u8, vminvq_s16, vminvq_s32, vminvq_s8, vminvq_u16, vminvq_u32, vminvq_u8, vmladavaq_p_s16, vmladavaq_p_s32, vmladavaq_p_s8, vmladavaq_p_u16, vmladavaq_p_u32, vmladavaq_p_u8, vmladavaq_s16, vmladavaq_s32, vmladavaq_s8, vmladavaq_u16, vmladavaq_u32, vmladavaq_u8, vmladavaxq_s16, vmladavaxq_s32, vmladavaxq_s8, vmladavq_p_s16, vmladavq_p_s32, vmladavq_p_s8, vmladavq_p_u16, vmladavq_p_u32, vmladavq_p_u8, vmladavq_s16, vmladavq_s32, vmladavq_s8, vmladavq_u16, vmladavq_u32, vmladavq_u8, vmladavxq_p_s16, vmladavxq_p_s32, vmladavxq_p_s8, vmladavxq_s16, vmladavxq_s32, vmladavxq_s8, vmlaldavaq_s16, vmlaldavaq_s32, vmlaldavaq_u16, vmlaldavaq_u32, vmlaldavaxq_s16, vmlaldavaxq_s32, vmlaldavq_p_s16, vmlaldavq_p_s32, vmlaldavq_p_u16, vmlaldavq_p_u32, vmlaldavq_s16, vmlaldavq_s32, vmlaldavq_u16, vmlaldavq_u32, vmlaldavxq_p_s16, vmlaldavxq_p_s32, vmlsdavaq_s16, vmlsdavaq_s32, vmlsdavaq_s8, vmlsdavaxq_s16, vmlsdavaxq_s32, vmlsdavaxq_s8, vmlsdavq_p_s16, vmlsdavq_p_s32, vmlsdavq_p_s8, vmlsdavq_s16, vmlsdavq_s32, vmlsdavq_s8, vmlsdavxq_p_s16, vmlsdavxq_p_s32, vmlsdavxq_p_s8, vmlsdavxq_s16, vmlsdavxq_s32, vmlsdavxq_s8, vmlsldavaq_s16, vmlsldavaq_s32, vmlsldavaxq_s16, vmlsldavaxq_s32, vmlsldavq_p_s16, vmlsldavq_p_s32, vmlsldavq_s16, vmlsldavq_s32, vmlsldavxq_p_s16, vmlsldavxq_p_s32, vmlsldavxq_s16, vmlsldavxq_s32, vmovlbq_x_s16, vmovlbq_x_s8, vmovlbq_x_u16, vmovlbq_x_u8, vmovltq_x_s16, vmovltq_x_s8, vmovltq_x_u16, vmovltq_x_u8, vmulhq_x_s16, vmulhq_x_s32, vmulhq_x_s8, vmulhq_x_u16, vmulhq_x_u32, vmulhq_x_u8, vmullbq_int_x_s16, vmullbq_int_x_s32, vmullbq_int_x_s8, vmullbq_int_x_u16, vmullbq_int_x_u32, vmullbq_int_x_u8, vmullbq_poly_x_p16, vmullbq_poly_x_p8, vmulltq_int_x_s16, vmulltq_int_x_s32, vmulltq_int_x_s8, vmulltq_int_x_u16, vmulltq_int_x_u32, vmulltq_int_x_u8, vmulltq_poly_x_p16, vmulltq_poly_x_p8, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vrmlaldavhaxq_s32, vrmlaldavhq_p_s32, vrmlaldavhq_p_u32, vrmlaldavhq_s32, vrmlaldavhq_u32, vrmlaldavhxq_p_s32, vrmlaldavhxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vrmlsldavhq_p_s32, vrmlsldavhq_s32, vrmlsldavhxq_p_s32, vrmlsldavhxq_s32, vstrbq_p_s16, vstrbq_p_s32, vstrbq_p_s8, vstrbq_p_u16, vstrbq_p_u32, vstrbq_p_u8, vstrbq_s16, vstrbq_s32, vstrbq_s8, vstrbq_scatter_offset_p_s16, vstrbq_scatter_offset_p_s32, vstrbq_scatter_offset_p_s8, vstrbq_scatter_offset_p_u16, vstrbq_scatter_offset_p_u32, vstrbq_scatter_offset_p_u8, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s8, vstrbq_scatter_offset_u16, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u8, vstrbq_u16, vstrbq_u32, vstrbq_u8, vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64, vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64, vstrdq_scatter_shifted_offset_u64. This patch adds the support for MVE ACLE intrinsics polymorphic variants with +mve.fp option. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the common section of both MVE Integer and MVE Floating Point. (vaddvq): Likewise. (vaddlvq_p): Likewise. (vaddvaq): Likewise. (vaddvq_p): Likewise. (vcmpcsq): Likewise. (vmlsdavxq): Likewise. (vmlsdavq): Likewise. (vmladavxq): Likewise. (vmladavq): Likewise. (vminvq): Likewise. (vminavq): Likewise. (vmaxvq): Likewise. (vmaxavq): Likewise. (vmlaldavq): Likewise. (vcmphiq): Likewise. (vaddlvaq): Likewise. (vrmlaldavhq): Likewise. (vrmlaldavhxq): Likewise. (vrmlsldavhq): Likewise. (vrmlsldavhxq): Likewise. (vmlsldavxq): Likewise. (vmlsldavq): Likewise. (vabavq): Likewise. (vrmlaldavhaq): Likewise. (vcmpgeq_m_n): Likewise. (vmlsdavxq_p): Likewise. (vmlsdavq_p): Likewise. (vmlsdavaxq): Likewise. (vmlsdavaq): Likewise. (vaddvaq_p): Likewise. (vcmpcsq_m_n): Likewise. (vcmpcsq_m): Likewise. (vmladavxq_p): Likewise. (vmladavq_p): Likewise. (vmladavaxq): Likewise. (vmladavaq): Likewise. (vminvq_p): Likewise. (vminavq_p): Likewise. (vmaxvq_p): Likewise. (vmaxavq_p): Likewise. (vcmphiq_m): Likewise. (vaddlvaq_p): Likewise. (vmlaldavaq): Likewise. (vmlaldavaxq): Likewise. (vmlaldavq_p): Likewise. (vmlaldavxq_p): Likewise. (vmlsldavaq): Likewise. (vmlsldavaxq): Likewise. (vmlsldavq_p): Likewise. (vmlsldavxq_p): Likewise. (vrmlaldavhaxq): Likewise. (vrmlaldavhq_p): Likewise. (vrmlaldavhxq_p): Likewise. (vrmlsldavhaq): Likewise. (vrmlsldavhaxq): Likewise. (vrmlsldavhq_p): Likewise. (vrmlsldavhxq_p): Likewise. (vabavq_p): Likewise. (vmladavaq_p): Likewise. (vstrbq_scatter_offset): Likewise. (vstrbq_p): Likewise. (vstrbq_scatter_offset_p): Likewise. (vstrdq_scatter_base_p): Likewise. (vstrdq_scatter_base): Likewise. (vstrdq_scatter_offset_p): Likewise. (vstrdq_scatter_offset): Likewise. (vstrdq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_shifted_offset): Likewise. (vmaxq_x): Likewise. (vminq_x): Likewise. (vmovlbq_x): Likewise. (vmovltq_x): Likewise. (vmulhq_x): Likewise. (vmullbq_int_x): Likewise. (vmullbq_poly_x): Likewise. (vmulltq_int_x): Likewise. (vmulltq_poly_x): Likewise. (vstrbq): Likewise. gcc/testsuite/ChangeLog: 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Modify. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
2020-03-31aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]Jakub Jelinek5-1/+47
The following testcase ICEs in final_scan_insn_1. The problem is in the @aarch64_compare_and_swaphi define_insn_and_split, since 9 it uses aarch64_plushi_operand predicate for the "expected value" operand, which allows either 0..0xfff constants or 0x1000..0xf000 constants (i.e. HImode values which when zero extended are either 0..0xfff or (0..0xfff) << 12). The problem is that RA doesn't care about predicates, it honors just constraints and the used constraint on the operand is n, which means any HImode CONST_SCALAR_INT. In the testcase LRA thus propagates the -1 value into the insn. This is a define_insn_and_split which requires mandatory split. But during split2 pass, we check the predicate (and don't check constraints), which fails and thus we don't split it and during final ICE because the mandatory splitting didn't happen. The following patch fixes it by adding a matching constraint to the predicate and using it. 2020-03-31 Jakub Jelinek <jakub@redhat.com> PR target/94368 * config/aarch64/constraints.md (Uph): New constraint. * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr. (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's constraint. * gcc.dg/pr94368.c: New test.
2020-03-31fold-const: Fix division folding with vector operands [PR94412]Jakub Jelinek4-4/+42
The following testcase is miscompiled since 4.9, we treat unsigned vector types as if they were signed and "optimize" negations across it. 2020-03-31 Marc Glisse <marc.glisse@inria.fr> Jakub Jelinek <jakub@redhat.com> PR middle-end/94412 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P. * gcc.c-torture/execute/pr94412.c: New test. Co-authored-by: Marc Glisse <marc.glisse@inria.fr>
2020-03-31store-merging: Allow enums during bswap recognition [PR94403]Jakub Jelinek4-1/+46
The following testcase is optimized with char/unsigned char/signed char, but not with std::byte. The following patch fixes that. Didn't use INTEGRAL_TYPE_P because bswapping bools is just too weird. 2020-03-31 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/94403 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also ENUMERAL_TYPE lhs_type. * g++.dg/tree-ssa/pr94403.C: New test.
2020-03-31forwprop: Pattern recognize more rotates [PR94344]Jakub Jelinek4-4/+110
The following patch adjusts simplify_rotate to recognize more rotates, basically we allow even some same precision integral -> integral conversions, with the requirement that the RSHIFT_EXPR operand has to be done in unsigned type (i.e. logical right shift), so that we compensate for the combiner no longer being able to simplify those into rotates on some targets. 2020-03-31 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/94344 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision conversions, either on both operands of |^+ or just one. Handle also extra same precision conversion on RSHIFT_EXPR first operand provided RSHIFT_EXPR is performed in unsigned type. * gcc.dg/pr94344.c: New test.
2020-03-30lra: set insn_code_data to NULL when freeingDavid Malcolm4-1/+23
libgccjit's test-threads.c repeatedly compiles and runs numerous tests, each in a separate thread. Attempting to add an empty test that generates no code leads to a double-free ICE within that thread, within lra.c's finish_insn_code_data_once. The root cause is that the insn_code_data array is cleared in init_insn_code_data_once, but this is only called the first time a cgraph_node is expanded [1], whereas the "loop-over-all-elements and free them" is unconditionally called in finalize [2]. Hence if there are no functions: * the array is not re-initialized for the empty context * when finish_insn_code_data_once is called for the empty context it still contains the freed pointers from the previous context that held the jit mutex, and hence the free is a double-free. This patch sets the pointers to NULL after freeing them, fixing the ICE. [1] init_insn_code_data_once is called via lra_init_once called by ira_init_once called by initialize_rtl, via: if (!rtl_initialized) ira_init_once (); called by init_function_start called by cgraph_node::expand [2]: finish_insn_code_data_once is called by: lra_finish_once called by finalize gcc/ChangeLog: * lra.c (finish_insn_code_data_once): Set the array elements to NULL after freeing them. gcc/testsuite/ChangeLog: * jit.dg/all-non-failing-tests.h: Add test-empty.c
2020-03-31Daily bump.GCC Administrator1-1/+1
2020-03-30Update gcc sv.po.Joseph Myers2-221/+160
* sv.po: Update.
2020-03-30c++: Fix comparison of fn() and ns::fn() [PR90711]Jason Merrill3-1/+57
The resolution of CWG issue 1321 clarified that when deciding whether two expressions involving template parameters are equivalent, two dependent function calls where the function is named with an unqualified-id are considered to be equivalent if the name is the same, even if unqualified lookup finds different sets of functions. We were wrongly treating qualified-ids the same way, so that EXISTS and test::EXISTS were considered to be equivalent even though they are looking up the name in different scopes. This also causes a mangling bug, but I don't think it's safe to fix that for GCC 10; this patch just fixes the comparison. gcc/cp/ChangeLog 2020-03-30 Jason Merrill <jason@redhat.com> PR c++/90711 * tree.c (cp_tree_equal) [CALL_EXPR]: Compare KOENIG_LOOKUP_P. (called_fns_equal): Check DECL_CONTEXT.
2020-03-30c++: Fix handling of internal fn calls in statement expressions [PR94385]Jakub Jelinek4-1/+25
The following testcase ICEs, because the FE when processing the statement expression changes the .VEC_CONVERT internal fn CALL_EXPR into .PHI call. That is because the internal fn call is recorded in the base.u.ifn field, which overlaps base.u.bits.lang_flag_1 which is used for STMT_IS_FULL_EXPR_P, so this essentially does ifn |= 2 on little-endian. STMT_IS_FULL_EXPR_P bit is used in: cp-gimplify.c- if (STATEMENT_CODE_P (code)) cp-gimplify.c- { cp-gimplify.c- saved_stmts_are_full_exprs_p = stmts_are_full_exprs_p (); cp-gimplify.c- current_stmt_tree ()->stmts_are_full_exprs_p cp-gimplify.c: = STMT_IS_FULL_EXPR_P (*expr_p); cp-gimplify.c- } and pt.c- if (STATEMENT_CODE_P (TREE_CODE (t))) pt.c: current_stmt_tree ()->stmts_are_full_exprs_p = STMT_IS_FULL_EXPR_P (t); so besides being wrong on some other codes, it actually isn't beneficial at all to set it on anything else, so the following patch restricts it to trees with STATEMENT_CODE_P TREE_CODE. 2020-03-30 Jakub Jelinek <jakub@redhat.com> PR c++/94385 * semantics.c (add_stmt): Only set STMT_IS_FULL_EXPR_P on trees with STATEMENT_CODE_P code. * c-c++-common/pr94385.c: New test.
2020-03-30Define TRY_EMPTY_VM_SPACE for riscv64-linuxAndreas Schwab2-0/+7
* config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]: Define.
2020-03-30RS6000 Allow builtin initialization regardless of maskWill Schmidt10-30/+230
Disable the code that limits initialization of builtins based on the rs6000_builtin_mask. This allows all built-ins to be properly referenced when building code using #pragma for cpu targets newer than what was specified by the -mcpu default. The use of built-ins is still properly limited by logic within altivec_resolve_overloaded_builtin(). 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com> gcc/ * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code to skip defining builtins based on builtin_mask. gcc/testsuite/ * gcc.target/powerpc/pragma_power6.c: New. * gcc.target/powerpc/pragma_power7.c: New. * gcc.target/powerpc/pragma_power8.c: New. * gcc.target/powerpc/pragma_power9.c: New. * gcc.target/powerpc/pragma_misc9.c: New. * gcc.target/powerpc/vsu/vec-all-nez-7.c: Update error message. * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Update error message.
2020-03-30Update bswap64-4 test for desired resultsWill Schmidt2-2/+9
Update existing testcase powerpc/bswap64-4.c to reflect that we generate ldbrx and stdbrx instructions for newer cpu targets, versus the pair of lwbrx and stwbrx instructions as seen on previous cpu targets. 2020-03-24 Will Schmidt <will_schmidt@vnet.ibm.com> gcc/testsuite/ * gcc.target/powerpc/bswap64-4.c: Update scan-assembler expected results.
2020-03-30i386: Fix up *one_cmplv*2* insn with avx512f [PR94343]Jakub Jelinek5-6/+56
This define_insn has two issues. One is that with -mavx512f -mno-avx512vl it can emit an AVX512VL-only insn - 128-bit or 256-bit EVEX encoded vpternlog{d,q}. Another one is that because there is no vpternlog{b,w}, we emit vpternlogd instead, but then we shouldn't pretend we support masking of that, because we don't. The first one can be fixed by forcing the use of %zmm* registers instead of %xmm* or %ymm* if AVX512F but not AVX512VL, like we do for a couple of other insns (although that is primarily done in order to support %xmm16+ regs). But we need to make sure that in that case the input operand isn't memory, because while we can read and store the higher bits of registers, we don't want to read from memory more bytes than what we should read. A variant to these two if_then_else set attrs, condition in the output and larger condition would be 4 different define_insns (one with something like VI48_AVX512VL iterator, masking, no g modifiers and "vm" input constraint, another one with VI48_AVX iterator, !TARGET_AVX512VL in condition, no masking, g modifiers and "v" input constraint, one with VI12_AVX512VL iterator, no masking, no g modifiers and "vm" input constraint and last one with VI12_AVX2 iterator, !TARGET_AVX512VL in condition, no masking, g modifiers and "v" input constraint, but I think having one pattern is shorter than that. 2020-03-30 Jakub Jelinek <jakub@redhat.com> PR target/94343 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input operand is a register. Don't enable masked variants for V*[QH]Imode. * gcc.target/i386/avx512f-pr94343.c: New test. * gcc.target/i386/avx512vl-pr94343.c: New test.
2020-03-30XFAIL pr57193.c test-case.Martin Liska2-1/+7
PR rtl-optimization/87716 * gcc.target/i386/pr57193.c: XFAIL a test-case.
2020-03-30Fix scan pattern of vect-8.f90 dump.Martin Liska2-1/+7
PR testsuite/94402 * gfortran.dg/vect/vect-8.f90: Allow 22 or 23 loops to be vectorized (based on libmvec presence).
2020-03-30Fix vextract* masked patterns [PR93069]Jakub Jelinek5-3/+41
The AVX512F documentation clearly states that in instructions where the destination is a memory only merging-masking is possible, not zero-masking, and the assembler enforces that. The testcase in this patch fails to assemble because of Error: unsupported masking for `vextracti32x8' on vextracti32x8 $0x0, %zmm1, -64(%rsp){%k1}{z} For the vector extraction patterns, we apparently have 7 *_maskm patterns that only accept memory destinations and rtx_equal_p merge-masking source for it, 7 *<mask_name> corresponding patterns that allow memory destination only for the non-masked cases (through <store_mask_constraint>), then 2 *<mask_name> patterns (lo ssehalf V16FI and lo ssehalf VI8F_256 ones) which do allow memory destination even for masked cases and are the cause of the testsuite failure, because we must not allow C constraint if the destination is m, and finally one pair of patterns (separate * and *_mask, hi ssehalf VI4F_256), which has another issue (for which I don't have a testcase though), where if it would match zero-masking with register destination, it wouldn't emit the needed {z} into assembly. The attached patch fixes those 3 issues only, perhaps more suitable for backporting. 2020-03-30 Jakub Jelinek <jakub@redhat.com> PR target/93069 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use <store_mask_constraint> instead of m in output operand constraint. (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of %{%3%}. * gcc.target/i386/avx512vl-pr93069.c: New test. * gcc.dg/vect/pr93069.c: New test.
2020-03-30[RS6000] Put call cookie back in AIX/ELFv2 call patternsAlan Modra3-89/+52
-mlongcall -mno-pltseq is supposed to emit long calls by using indirect calls. It differs from -mlongcall -mpltseq in that the function addresses are not placed in the PLT and thus lazy PLT resolution is not available, affecting programs that dlopen shared libraries. In the case of -mcpu=future -mpcrel -mlongcall -mno-pltseq we see an indirect call being generated, but combine merrily optimises the sequence back to a direct call. call_indirect_pcrel is enough like call_nonlocal_aix that this can happen. This patch puts the call cookie back in the call rtl, removed by git commit f90f960ca8, in order to disable the optimisation for long calls. When that is done for call_local_aix the pattern becomes the same as call_local32/64, so I merged them. The only difference besides mode between call_local32 and call_local64, dating back to 1998 commit a260abc996, is that call_local64 has TARGET_64BIT in the predicate. That alone doesn't seem reason enough to need separate patterns; The P mode iterator selects DI on TARGET_64BIT anyway. * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern. (rs6000_indirect_call_template_1): Adjust to suit. * config/rs6000/rs6000.md (call_local): Merge call_local32, call_local64, and call_local_aix. (call_value_local): Simlarly. (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit, and disable pattern when CALL_LONG. (call_indirect_aix, call_value_indirect_aix): Adjust rtl. (call_indirect_elfv2, call_indirect_pcrel): Likewise. (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
2020-03-30Daily bump.GCC Administrator1-1/+1
2020-03-29doc: Update -falign-functions/-falign-loops/-falign-jumpsH.J. Lu2-3/+15
Change -falign-functions=N to Align the start of functions to the next power-of-two greater than or equal to N. Add If '-falign-labels' is greater than this value, then its value is used instead. to -falign-loops=N and -falign-jumps=N. PR driver/94381 * doc/invoke.texi: Update -falign-functions, -falign-loops and -falign-jumps documentation.
2020-03-29testsuite: Handle more kinds of gdc.test test flags and directives.Iain Buclaw2-26/+59
This patch adds cases for JSON and D header file generation flags in the testsuite, and sets up the test accordingly to only compile, then check that the expected output file exists. Support has also been added for the DFLAGS test directive, which disables testing with all default flag permutations. gcc/testsuite/ChangeLog: * lib/gdc-utils.exp: (gdc-convert-args): Handle compilation test arguments -D, -H, -X, and set compilable_output_file_ext. (gdc-convert-test): Document and add cases DFLAGS and EXTRA_CPP_SOURCES. Add dg-final entry for output generation tests, and set compilable_do_what to compile. (gdc-do-test): Define compilable_do_what, default to assemble.
2020-03-29testsuite: Move C++ tests in gdc.test into own subdirectory.Iain Buclaw15-43/+122
Tests have been moved into runnable_cxx as part of upstream dmd 3e10e2dd2. The extra flags required for tests that mix C++ and D are now limited to only a small subset of tests, rather than applied to all tests across gdc.dg and gdc.test. Reviewed-on: https://github.com/dlang/dmd/pull/10980 gcc/testsuite/ChangeLog: * gdc.test/runnable_cxx/runnable_cxx.exp: New file. * lib/gdc-utils.exp (gdc-do-test): Add case for runnable_cxx. * lib/gdc.exp (gdc_include_flags): Only add flags for libstdc++-v3 if GDC_INCLUDE_CXX_FLAGS is true. (gdc_link_flags): Likewise. (gdc_init): Move setting of default gdc test flags to... (gdc_target_compile): ...here.
2020-03-29Fix typo in a warning related to flatten.Martin Liska2-2/+7
PR ipa/94363 * cgraphunit.c (process_function_and_variable_attributes): Remove double 'attribute' words.
2020-03-29Delete duplicate .align output.John David Anglin2-1/+5
2020-03-29 John David Anglin <dave.anglin@bell.net> * gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate .align output.
2020-03-29testsuite: Split up gdc-test.exp into each subdirectoryIain Buclaw5-30/+117
Use multiple test scripts, one for each subdirectory containing test files, instead of having one test script to manage them all. This allows removing some workarounds, such as the need to create symlinks in the test run directory. gcc/testsuite/ChangeLog: * gdc.test/compilable/compilable.exp: New file. * gdc.test/fail_compilation/fail_compilation.exp: New file. * gdc.test/gdc-test.exp: Remove. * gdc.test/runnable/runnable.exp: New file. * lib/gdc-utils.exp: ...this. Remove load_lib gdc-dg.exp. (dmd2dg): Rename to... (gdc-convert-test): ...this. (gdc-do-test): Add testcases parameter and remove subdir handling.
2020-03-29Daily bump.GCC Administrator1-1/+1
2020-03-29testsuite: adjust modulo-sched compare-debug testsRoman Zhuykov3-2/+10
Without this patch tortured tests eventually fail because of another known issue which I plan to fix later in stage1. * gcc.dg/torture/pr87197-debug-sms.c: Move to ... * gcc.dg/sms-compare-debug-1.c: ... this. Add -O2. * gcc.c-torture/execute/pr70127-debug-sms.c: Move to ... * gcc.dg/sms-compare-debug-2.c: ... this. Add -O2.
2020-03-28Patch for PR94246Paul Thomas4-37/+113
2020-03-28[Fortran] Fix result-variable handling of MODULE PROCEDURE (PR94348)Tobias Burnus4-5/+50
PR fortran/94348 * decl.c (gfc_match_submod_proc): Add result var to the proc's namespace. PR fortran/94348 * gfortran.dg/module_procedure_3.f90: New.
2020-03-28c++: Diagnose when "requires" is used instead of "requires requires" [PR94306]Patrick Palka4-1/+29
This adds support to detect and recover from the case where an opening brace immediately follows the start of a requires-clause. So rather than emitting the error error: expected primary-expression before '{' token followed by a slew of irrevelant errors, we now assume the user had intended to write "requires requires {" and diagnose and recover accordingly. gcc/cp/ChangeLog: PR c++/94306 * parser.c (cp_parser_requires_clause_opt): Diagnose and recover from "requires {" when "requires requires {" was probably intended. gcc/testsuite/ChangeLog: PR c++/94306 * g++.dg/concepts/diagnostic8.C: New test.
2020-03-28c++: requires-expression outside of a template is misevaluated [PR94252]Patrick Palka10-12/+91
This PR shows that a REQUIRES_EXPR outside of a template can sometimes be misevaluated. This happens because the evaluation routine tsubst_requires_expr (and diagnose_requires_expr) assumes the REQUIRES_EXPR's subtrees are templated trees and that therefore it's safe to call tsubst_expr on them. But this assumption isn't valid when we've parsed a REQUIRES_EXPR outside of a template context. In order to make this assumption valid here, this patch sets processing_template_decl to non-zero before parsing the body of a REQUIRES_EXPR so that its subtrees are indeed always templated trees. gcc/cp/ChangeLog: PR c++/94252 * constraint.cc (tsubst_compound_requirement): Always suppress errors from type_deducible_p and expression_convertible_p, as they're not substitution errors. (diagnose_atomic_constraint) <case INTEGER_CST>: Remove this case so that we diagnose INTEGER_CST expressions of non-bool type via the default case. * cp-gimplify.c (cp_genericize_r) <case REQUIRES_EXPR>: New case. * parser.c (cp_parser_requires_expression): Always parse the requirement body as if we're processing a template, by temporarily incrementing processing_template_decl. Afterwards, if we're not actually in a template context, perform semantic processing to diagnose any invalid types and expressions. * pt.c (tsubst_copy_and_build) <case REQUIRES_EXPR>: Remove dead code. * semantics.c (finish_static_assert): Explain an assertion failure when the condition is a REQUIRES_EXPR like we do when it is a concept check. gcc/testsuite/ChangeLog: PR c++/94252 * g++.dg/concepts/diagnostic7.C: New test. * g++.dg/concepts/pr94252.C: New test. * g++.dg/cpp2a/concepts-requires18.C: Adjust to expect an additional diagnostic.
2020-03-28c++: Respect current_constraint_diagnosis_depth in diagnose_compound_requirementPatrick Palka7-14/+32
The previous patch tries to avoid changing our current default diagnostics. But for the sake of consistency we arguably should also respect current_constraint_diagnosis_depth in diagnose_compound_requirement() like we do in the other error-replaying diagnostic routines. But doing so would be a change to our default diagnostics behavior, so the change has been split out into this separate patch for separate consideration. gcc/cp/ChangeLog: * constraint.cc (diagnose_compound_requirement): When diagnosing a compound requirement, maybe replay the satisfaction failure, subject to the current diagnosis depth. gcc/testsuite/ChangeLog: * g++.dg/concepts/diagnostic1.C: Pass -fconcepts-diagnostics-depth=2. * g++.dg/concepts/diagnostic5.C: Adjust expected diagnostics. * g++.dg/cpp2a/concepts-iconv1.C: Pass -fconcepts-diagnostics-depth=2. * g++.dg/cpp2a/concepts-requires5.C: Likewise.
2020-03-28c++: Replay errors during diagnosis of constraint satisfaction failuresPatrick Palka8-21/+218
This patch adds a new flag -fconcepts-diagnostics-depth to the C++ frontend which controls how deeply we replay errors when diagnosing a constraint satisfaction failure. The default is -fconcepts-diagnostics-depth=1 which diagnoses only the topmost constraint satisfaction failure and is consistent with our behavior before this patch. By increasing this flag's value, the user can control how deeply they want the compiler to explain a constraint satisfaction error. For example, if the unsatisfied constraint is a disjunction, then the default behavior is to just say "no branch in the disjunction is satisfied", but with -fconcepts-diagnostics-depth=2 we will additionally replay and diagnose the error in each branch of the disjunction. And if the unsatisfied constraint is a requires expression, then we will replay the error in the requires expression, etc. This proceeds recursively until there is nothing more to replay or we exceeded the maximum depth specified by the flag. Implementation wise, this patch essentially just uncomments the existing commented-out code that performs the error-replaying, and along the way adds logic to keep track of and limit the current replay depth. Besides that, there is a new routine collect_operands_of_disjunction which flattens a disjunction and collects all of its operands into a vector. The extra diagnostics enabled by this flag are at times longer than they need to be (e.g. "the operand is_array_v<...> is unsatisfied because \n the expression is_array_v<...> [with ...] evaluated to false") and not immediately easy to follow (especially when there are nested disjunctions), but the transparency provided by these optional diagnostics seems to be pretty helpful in practice. gcc/c-family/ChangeLog: * c.opt: Add -fconcepts-diagnostics-depth. gcc/cp/ChangeLog: * constraint.cc (finish_constraint_binary_op): Set the location of EXPR as well as its range, because build_x_binary_op doesn't always do so. (current_constraint_diagnosis_depth): New. (concepts_diagnostics_max_depth_exceeded_p): New. (collect_operands_of_disjunction): New. (satisfy_disjunction): When diagnosing a satisfaction failure, maybe replay each branch of the disjunction, subject to the current diagnosis depth. (diagnose_valid_expression): When diagnosing a satisfaction failure, maybe replay the substitution error, subject to the current diagnosis recursion. (diagnose_valid_type): Likewise. (diagnose_nested_requiremnet): Likewise. (diagnosing_failed_constraint::diagnosing_failed_constraint): Increment current_constraint_diagnosis_depth when diagnosing. (diagnosing_failed_constraint::~diagnosing_failed_constraint): Decrement current_constraint_diagnosis_depth when diagnosing. (diagnosing_failed_constraint::replay_errors_p): New static member function. (diagnose_constraints): Don't diagnose if concepts_diagnostics_max_depth is 0. Emit a one-off note to increase -fconcepts-diagnostics-depth if the limit was exceeded. * cp-tree.h (diagnosing_failed_constraint::replay_errors_p): Declare. gcc/testsuite/ChangeLog: * g++.dg/concepts/diagnostic2.C: Expect "no operand" instead of "neither operand". * g++.dg/concepts/diagnostic5.C: New test.
2020-03-28c: After issuing errors about array size, for error-recovery don't make the ↵Jakub Jelinek5-0/+29
array VLA [PR93573] After we report various errors about array size, we set for error-recovery the size to be 1, but because size_int_const is false, it still means we pretend the array is a VLA, can emit a second diagnostics in that case etc. E.g. $ ./cc1.unpatched -quiet a.c a.c:1:5: error: size of array ‘f’ has non-integer type 1 | int f[100.0]; | ^ a.c:1:1: warning: variably modified ‘f’ at file scope 1 | int f[100.0]; | ^~~ $ ./cc1 -quiet a.c a.c:1:5: error: size of array ‘f’ has non-integer type 1 | int f[100.0]; | ^ 2020-03-28 Jakub Jelinek <jakub@redhat.com> PR c/93573 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const to true after setting size to integer_one_node. * gcc.dg/pr93573-1.c: New test. * gcc.dg/pr93573-2.c: New test.
2020-03-28reassoc: Fix -fcompare-debug bug in reassociate_bb [PR94329]Jakub Jelinek4-7/+31
The following testcase FAILs with -fcompare-debug, because reassociate_bb mishandles the case when the last stmt in a bb has zero uses. In that case reassoc_remove_stmt (like gsi_remove) moves the iterator to the next stmt, i.e. gsi_end_p is true, which means the code sets the iterator back to gsi_last_bb. The problem is that the for loop does gsi_prev on that before handling the next statement, which means the former penultimate stmt, now last one, is not processed by reassociate_bb. Now, with -g, if there is at least one debug stmt at the end of the bb, reassoc_remove_stmt moves the iterator to that following debug stmt and we just do gsi_prev and continue with the former penultimate non-debug stmt, now last non-debug stmt. The following patch fixes that by not doing the gsi_prev in this case; there are too many continue; cases, so I didn't want to copy over the gsi_prev to all of them, so this patch uses a bool for that instead. The second gsi_end_p check isn't needed anymore, because when we don't do the undesirable gsi_prev after gsi = gsi_last_bb, the loop !gsi_end_p (gsi) condition will catch the removal of the very last stmt from a bb. 2020-03-28 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/94329 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt on the last stmt in a bb, make sure gsi_prev isn't done immediately after gsi_last_bb. * gfortran.dg/pr94329.f90: New test.
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