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2016-08-04re PR target/70677 (Suboptimal cond on AVR: unneeded stack frame)Georg-Johann Lay2-0/+9
PR 70677 * common/config/avr/avr-common.c (avr_option_optimization_table) [OPT_LEVELS_ALL]: Turn off -fcaller-saves. From-SVN: r239117
2016-08-04re PR target/55181 (Expensive shift loop where a bit-testing instruction ↵Georg-Johann Lay2-0/+29
could be used) PR 55181 * config/avr/avr.md: New pattern to work around do_store_flag generating shift instructions for bit extractions. From-SVN: r239116
2016-08-04re PR c++/70229 (error: constexpr constructor does not have empty body)Marek Polacek4-1/+55
PR c++/70229 * constexpr.c (check_constexpr_ctor_body_1): Allow typedef declarations. * g++.dg/cpp0x/constexpr-ctor19.C: New test. From-SVN: r239115
2016-08-04re PR rtl-optimization/71984 (wrong code with -O -mavx512cd)Richard Biener2-0/+8
2016-08-04 Richard Biener <rguenther@suse.de> PR middle-end/71984 * gcc.dg/torture/pr71984.c: Guard correctness check for little-endian. From-SVN: r239114
2016-08-04tree-vrp.c (set_value_range): Use vrp_equiv_obstack with BITMAP_ALLOC.Kugan Vivekanandarajah2-10/+21
gcc/ChangeLog: 2016-08-04 Kugan Vivekanandarajah <kuganv@linaro.org> * tree-vrp.c (set_value_range): Use vrp_equiv_obstack with BITMAP_ALLOC. (add_equivalence): Likewise. (get_value_range): Allocate value range with vrp_value_range_pool. (vrp_initialize): Initialize vrp_equiv_obstack for equiv allocation. (vrp_finalize): Relase vrp_equiv_obstack and vrp_value_range_pool. From-SVN: r239113
2016-08-04Daily bump.GCC Administrator1-1/+1
From-SVN: r239112
2016-08-04escape: Enable escape analysis in gccgo.Ian Lance Taylor3-1/+12
Off by default, enabled through -fgo-optimize-allocs. Reviewed-on: https://go-review.googlesource.com/22378 From-SVN: r239109
2016-08-03rs6000.c (rs6000_option_override_internal): Make LRA the default for the ↵Peter Bergner2-0/+9
rs6000 port. * config/rs6000/rs6000.c (rs6000_option_override_internal): Make LRA the default for the rs6000 port. From-SVN: r239105
2016-08-03gotest: multiple +build lines must all be trueIan Lance Taylor1-1/+1
The code that handled +build lines did not correctly require them to all be true. While looking into this I discovered that multiple +build lines were mishandled in a different way, because the shell does not preseve line breaks in backquoted data. Look for the +build token to tell us when we are switching from one +build line to another. Reviewed-on: https://go-review.googlesource.com/25460 From-SVN: r239100
2016-08-0320160802-1.c: New testcase.Andrew Pinski2-0/+17
2016-08-03 Andrew Pinski <apinski@cavium.com> * gcc.c-torture/compile/20160802-1.c: New testcase. From-SVN: r239099
2016-08-03compiler: improve type caching for interface typesIan Lance Taylor2-5/+18
Add a cached to Interface_info_expression::do_type() so as to reuse previously created interface types. This change reduces gccgo peak heap usage when compiling the "fmt" package from around 16mb to around 10mb. Fixes golang/go#16334 Reviewed-on: https://go-review.googlesource.com/24890 From-SVN: r239095
2016-08-03re PR middle-end/71876 (longjmp is miscompiled with -ffreestanding)Bernd Edlinger2-37/+22
2016-08-03 Bernd Edlinger <bernd.edlinger@hotmail.de> PR middle-end/71876 * calls.c (special_function_p): Remove special handling of "setjmp_syscall", "qsetjmp", "longjmp", "siglongjmp" and the prefix "__x". Recognize "savectx", "vfork" and "getcontext" only without prefix. Remove potentially unsafe ECF_LEAF and ECF_NORETURN. From-SVN: r239092
2016-08-03re PR rtl-optimization/72778 (internal compiler error: in create_pre_exit, ↵Vladimir Makarov2-4/+34
at mode-switching.c:451) 2016-08-03 Vladimir Makarov <vmakarov@redhat.com> PR middle-end/72778 * lra-spills.c (regno_in_use_p): Check bb and regno modification. Don't stop on regular insns. From-SVN: r239091
2016-08-03nvptx.c (nvptx_declare_function_name): Round frame size to DImode boundary.Nathan Sidwell2-4/+14
gcc/ * config/nvptx/nvptx.c (nvptx_declare_function_name): Round frame size to DImode boundary. (nvptx_propagate): Likewise. libgomp/ * testsuite/libgomp.oacc-c-c++-common/crash-1.c: New. From-SVN: r239086
2016-08-03escape: Stack allocate non-escaping expressions.Ian Lance Taylor2-8/+44
Stack allocate expressions that the analysis tracked and determined did not escape. Reviewed-on: https://go-review.googlesource.com/22377 From-SVN: r239083
2016-08-03lang.opt: New option -fdec-intrinsic-ints.Fritz Reese9-14/+542
2016-08-03 Fritz Reese <fritzoreese@gmail.com> gcc/fortran/ * lang.opt: New option -fdec-intrinsic-ints. * options.c (set_dec_flags): Enable with -fdec. * gfortran.texi, invoke.texi, intrinsics.texi: Update documentation. * intrinsic.c (add_function, add_subroutine): New B/I/J/K intrinsic variants. gcc/testsuite/gfortran.dg/ * dec_intrinsic_ints.f90: New testcase. From-SVN: r239078
2016-08-03pr71403-1.c: Use dg-additional-options and remove -O3.Richard Biener4-3/+10
2016-08-03 Richard Biener <rguenther@suse.de> * c-c++-common/ubsan/pr71403-1.c: Use dg-additional-options and remove -O3. * c-c++-common/ubsan/pr71403-2.c: Likewise. * c-c++-common/ubsan/pr71403-3.c: Likewise. From-SVN: r239077
2016-08-03loadpre2.c: Disable LIM.Richard Biener5-4/+11
2016-08-03 Richard Biener <rguenther@suse.de> * gcc.dg/tree-ssa/loadpre2.c: Disable LIM. * gcc.dg/tree-ssa/loadpre21.c: Likewise. * gcc.dg/tree-ssa/loadpre22.c: Likewise. * gcc.dg/tree-ssa/ssa-pre-23.c: Likewise. From-SVN: r239071
2016-08-03Fix tests that break unnecessarily for avr.Senthil Kumar Selvaraj6-1/+16
Require int32plus for tests that assume so, and conditionally skip pr44024.c, as it only works if the target allows deletion of null pointer checks. gcc/testsuite/ChangeLog * gcc.dg/init-excess-2.c: Require int32plus. * gcc.dg/pr44024.c: Skip if target keeps null pointer checks. * gcc.dg/pr59963-2.c: Require int32plus. * gcc.dg/pr71084.c: Cast pointer to intprt_t. * gcc.dg/unroll-7.c: Require int32plus. From-SVN: r239065
2016-08-03[RS6000] power8 unaligned fp load/storeAlan Modra3-6/+13
According to the POWER8 Processor User’s Manual and some experimentation on power8 hardware, unaligned fp load/store on power8 does not invoke the alignment interrupt. * config/rs6000/rs6000.h (SLOW_UNALIGNED_ACCESS): Make scalar float access depend on TARGET_EFFICIENT_UNALIGNED_VSX. * config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Renamed from -mefficient-unaligned-vector. Note that this affects fp too. From-SVN: r239013
2016-08-03[RS6000] cost SLOW_UNALIGNED_ACCESSAlan Modra2-0/+10
* config/rs6000/rs6000.c (rs6000_rtx_costs): Make unaligned mem cost more. From-SVN: r239012
2016-08-03[RS6000] Force source of fix_trunc<mode>si2 to regAlan Modra2-5/+10
* config/rs6000/rs6000.md (fix_trunc<mode>si2): Force source operand to a reg. Localize vars. From-SVN: r239011
2016-08-03[RS6000] Remove negative from option help stringsAlan Modra2-18/+23
* config/rs6000/rs6000.opt: Remove negatives from help strings and comments. From-SVN: r239010
2016-08-03[RS6000] Delete duplicate codeAlan Modra2-41/+22
This removes the duplicate (TARGET_POWERPC64 && size == 16) block. * config/rs6000/rs6000.c (rs6000_secondary_reload_direct_move): Delete duplicated code. From-SVN: r239009
2016-08-03Daily bump.GCC Administrator1-1/+1
From-SVN: r239008
2016-08-02escape: Add basic debugging.Chris Manghane10-7/+577
Emit basic debug information when compiling with the flag -fgo-debug-escape#. Reviewed-on: https://go-review.googlesource.com/22376 2016-08-02 Chris Manghane <cmang@google.com> * lang.opt: Add -fgo-debug-escape option. * go-c.h (go_create_gogo): Add debug_escape_level parameter. * go-lang.c (go_langhook_init): Pass go_debug_escape_level to go_create_gogo. From-SVN: r239002
2016-08-02re PR rtl-optimization/72778 (internal compiler error: in create_pre_exit, ↵Vladimir Makarov2-6/+22
at mode-switching.c:451) 2016-08-02 Vladimir Makarov <vmakarov@redhat.com> PR middle-end/72778 * lra-spills.c (regno_in_use_p): New. (lra_final_code_change): Use it. From-SVN: r239000
2016-08-02expr.c (push_value): Only call flush_quick_stack for non-constant arguments.Roger Sayle2-46/+95
2016-08-02 Roger Sayle <roger@nextmovesoftware.com> * expr.c (push_value): Only call flush_quick_stack for non-constant arguments. (build_java_throw_out_of_bounds_exception): No longer wrap calls to _Jv_ThowBadArrayIndex in a COMPOUND_EXPR as no longer needed. (java_check_reference): Annotate COND_EXPR with __builtin_expect to indicate that calling _Jv_ThrowNullPointerException is unlikely. (build_java_arrayaccess): Construct an unlikely COND_EXPR instead of a TRUTH_ANDIF_EXPR in a COMPOUND_EXPR. Only generate array index MULT_EXPR when size_exp is not unity. (build_array_length_annotation): When optimizing, generate a write to the allocated array's length field to expose constant lengths to GCC's optimizers. (build_newarray): Call new build_array_length_annotation. (build_anewarray): Likewise. (expand_java_multianewarray): Fix whitespace. (expand_java_return): Likewise. (expand_invoke): Likewise. (load_type_state): Likewise. From-SVN: r238992
2016-08-02re PR rtl-optimization/69847 (Spec 2006 403.gcc slows down with -mlra vs. ↵Vladimir Makarov7-162/+533
reload on PowerPC) 2016-08-02 Vladimir Makarov <vmakarov@redhat.com> PR rtl-optimization/69847 * lra-int.h (struct lra-reg): Use restore_rtx instead of restore_regno. (lra_rtx_hash): New. * lra.c (initialize_lra_reg_info_element): Use restore_rtx instead of restore_regno. (lra_rtx_hash): Rename and move lra-remat.c::rtx_hash. * lra-remat.c (rtx_hash): Rename and Move to lra.c. * lra-spills.c (lra_final_code_change): Don't delete insn when the next insn is USE with the same reg as the current insn source. * lra-constraints.c (curr_insn_transform): Use restore_rtx instead of restore_regno. (lra_constraints_init): Call initiate_invariants. (lra_constraints_finish): Call finish_invariants. (struct invariant, invariant_t, invariant_ptr_t): New. (const_invariant_ptr_t, invariants, invariants_pool): New. (invariant_table, invariant_hash, invariant_eq_p): New. (insert_invariant, initiate_invariants, finish_invariants): New. (clear_invariants, invalid_invariant_regs): New. (inherit_reload_reg, split_reg, fix_bb_live_info): Use restore_rtx instead of restore_regno. (invariant_p, process_invariant_for_inheritance): New. (inherit_in_ebb): Implement invariant inheritance. (lra_inheritance): Initialize and finalize invalid_invariant_regs. (remove_inheritance_pseudos): Implement undoing invariant inheritance. (undo_optional_reloads, lra_undo_inheritance): Use restore_rtx instead of restore_regno. * lra-assigns.c (regno_live_length): New. (reload_pseudo_compare_func): Use regno_live_length. (assign_by_spills): Use restore_rtx instead of restore_regno. (lra_assign): Ditto. Initiate regno_live_length. From-SVN: r238991
2016-08-02[Patch AArch64 Obvious] Fix Bootstrap for my mistake in r238977James Greenhalgh2-1/+6
I deleted an 'f' halfway through a line when applying r238977. Not sure how I managed it, but entirely my fault. gcc/ * config/aarch64/arm_neon.h (vminnm_f64): Add back missing 'f' from __builtin_aarch64_fmindf. From-SVN: r238989
2016-08-02re PR tree-optimization/34114 (Missed optimization: cannot determine loop ↵Bin Cheng4-15/+121
termination) PR tree-optimization/34114 * tree-ssa-loop-niter.c (number_of_iterations_ne): Prove no-overflow information for more control IVs. gcc/testsuite PR tree-optimization/34114 * gcc.dg/tree-ssa/loop-42.c: New test. From-SVN: r238983
2016-08-02re PR tree-optimization/34114 (Missed optimization: cannot determine loop ↵Bin Cheng2-7/+66
termination) PR tree-optimization/34114 * fold-const.c (multiple_of_p): Improve MULT_EXPR, PLUS_EXPR, PLUS_EXPR case. Handle SSA_NAME case. From-SVN: r238982
2016-08-02[PATCH AArch64] Add more AArch64 NEON intrinsicsTamar Christina9-39/+166
Add vmaxnm_f64, vminnm_f64, vmax_f64, vmin_f64. Committed on behalf of Tamar Christina <tamar.christina@arm.com> . gcc/ * config/aarch64/aarch64-simd-builtins.def (__builtin_aarch64_fmindf): Change BUILTIN_VDQF to BUILTIN_VDQF_DF. (__builtin_aarch64_fmaxdf): Likewise. (__builtin_aarch64_smin_nandf): Likewise. (__builtin_aarch64_smax_nandf): Likewise. * config/aarch64/aarch64-simd.md (<fmaxmin><mode>3): Remove. * config/aarch64/aarch64.md (<fmaxmin><mode>3): Rename to... (<fmaxmin><mode>3): ...this. * config/aarch64/arm_neon.h (vmaxnm_f64): New. (vminnm_f64): Likewise. (vmin_f64): Likewise. (vmax_f64): Likewise. * config/aarch64/iterators.md (FMAXMIN): Merge with... (FMAXMIN_UNS): ...this. (fmaxmin): Merged with (fmaxmin_op): ...this... (maxmin_uns_op): ...in to this. gcc/testsuite/ * gcc.target/aarch64/vminmaxnm.c: New. * gcc.target/aarch64/simd/vminmaxnm_1.c (main): Added float64x1_t tests. From-SVN: r238977
2016-08-02Daily bump.GCC Administrator1-1/+1
From-SVN: r238976
2016-08-01rs6000-c.c (altivec_resolve_overloaded_builtin): Add support for vec_extract ↵Michael Meissner10-17/+571
on vector float... [gcc] 2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add support for vec_extract on vector float, vector int, vector short, and vector char vector types. * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add vector float, vector int, vector short, and vector char optimizations on 64-bit ISA 2.07 systems for both constant and variable element numbers. (rs6000_split_vec_extract_var): Likewise. * config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Allow SFmode to be Altivec registers on ISA 2.07 and above. (vsx_extract_v4sf): Delete alternative that hard coded element 0, which never was matched due to the split occuring before register allocation (and the code would not have worked on little endian systems if it did match). Allow extracts to go to the Altivec registers if ISA 2.07 (power8). Change from using "" around the C++ code to using {}'s. (vsx_extract_v4sf_<mode>_load): New insn to optimize vector float vec_extracts when the vector is in memory. (vsx_extract_v4sf_var): New insn to optimize vector float vec_extracts when the element number is variable on 64-bit ISA 2.07 systems. (vsx_extract_<mode>, VSX_EXTRACT_I iterator): Add optimizations for 64-bit ISA 2.07 as well as ISA 3.0. (vsx_extract_<mode>_p9, VSX_EXTRACT_I iterator): Likewise. (vsx_extract_<mode>_p8, VSX_EXTRACT_I iterator): Likewise. (vsx_extract_<mode>_load, VSX_EXTRACT_I iterator): New insn to optimize vector int, vector short, and vector char vec_extracts when the vector is in memory. (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): New insn to optimize vector int, vector short, and vector char vec_extracts when the element number is variable. [gcc/testsuite] 2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/vec-extract-5.c: New tests to test vec_extract for vector float, vector int, vector short, and vector char. * gcc.target/powerpc/vec-extract-6.c: Likewise. * gcc.target/powerpc/vec-extract-7.c: Likewise. * gcc.target/powerpc/vec-extract-8.c: Likewise. * gcc.target/powerpc/vec-extract-9.c: Likewise. From-SVN: r238971
2016-08-01Warn about mangled name change even if DECL_REALLY_EXTERN.Jason Merrill2-29/+34
* mangle.c (mangle_decl): Warn about mangled name change even if DECL_REALLY_EXTERN. From-SVN: r238966
2016-08-01mangle.c (get_abi_tags): New.Jason Merrill2-17/+34
* mangle.c (get_abi_tags): New. (find_substitution, write_unqualified_name, write_abi_tags) (maybe_check_abi_tags): Use it. From-SVN: r238965
2016-08-01* mangle.c (mangle_decl): Fix mangled name change warning.Jason Merrill4-5/+8
From-SVN: r238964
2016-08-01re PR target/71948 ([avr] Make progmem work on reduced Tiny cores by adding ↵Georg-Johann Lay2-1/+7
0x4000 to symbols) PR target/71948 * config/avr/avr.c (AVR_SYMBOL_FLAG_TINY_PM): Use a value that does not overlap with other symbol flags. From-SVN: r238961
2016-08-01This patch optimizes the prolog and epilog code to reduce the number of ↵Wilco Dijkstra12-221/+260
instructions and avoid multiple writes to SP. This patch optimizes the prolog and epilog code to reduce the number of instructions and avoid multiple writes to SP. The key idea is that epilogs are almost exact reverses of prologs, and thus all the decisions only need to be taken once. The frame layout is decided in aarch64_layout_frame() and decisions recorded in the new aarch64_frame fields initial_adjust, callee_adjust, callee_offset and final_adjust. A generic frame setup consists of 5 basic steps: 1. sub sp, sp, initial_adjust 2. stp reg1, reg2, [sp, -callee_adjust]! (push if callee_adjust != 0) 3. add fp, sp, callee_offset (if frame_pointer_needed) 4. stp reg3, reg4, [sp, callee_offset + N*16] (store remaining callee-saves) 5. sub sp, sp, final_adjust The epilog reverses this, and may omit step 3 if alloca wasn't used. gcc/ * config/aarch64/aarch64.h (aarch64_frame): Remove padding0 and hardfp_offset. Add locals_offset, initial_adjust, callee_adjust, callee_offset and final_adjust. * config/aarch64/aarch64.c (aarch64_layout_frame): Remove unused padding0 and hardfp_offset initializations. Choose frame layout and set frame variables accordingly. Use INVALID_REGNUM instead of FIRST_PSEUDO_REGISTER. (aarch64_push_regs): Use INVALID_REGNUM, not FIRST_PSEUDO_REGISTER. (aarch64_pop_regs): Likewise. (aarch64_expand_prologue): Remove all decision code, just emit prolog according to frame variables. (aarch64_expand_epilogue): Remove all decision code, just emit epilog according to frame variables. (aarch64_initial_elimination_offset): Use offset to local/arg area. testsuite/ * gcc.target/aarch64/test_frame_10.c: Fix test to check for a single stack adjustment, no writeback. * gcc.target/aarch64/test_frame_12.c: Likewise. * gcc.target/aarch64/test_frame_13.c: Likewise. * gcc.target/aarch64/test_frame_15.c: Likewise. * gcc.target/aarch64/test_frame_6.c: Likewise. * gcc.target/aarch64/test_frame_7.c: Likewise. * gcc.target/aarch64/test_frame_8.c: Likewise. * gcc.target/aarch64/test_frame_16.c: New test. From-SVN: r238960
2016-08-01PR c++/72766 - ICE with VLAJason Merrill4-1/+22
* constexpr.c (cxx_eval_pointer_plus_expression): Check constancy of nelts. * cp-gimplify.c (cp_fully_fold): Only maybe_constant_value in C++11 and up. From-SVN: r238957
2016-08-01Convert V1TImode register to TImode in debug insnH.J. Lu4-0/+45
TImode register referenced in debug insn can be converted to V1TImode by scalar to vector optimization. When converting a TImode store to V1TImode, we need to check all debug insns on its use chain to convert the V1TImode register to SUBREG TImode if source register is undefined. gcc/ PR target/72748 * config/i386/i386.c (timode_scalar_chain::convert_insn): Call fix_debug_reg_uses after changing source register mode to V1TImode if source register is undefined. gcc/testsuite/ PR target/72748 * gcc.target/i386/pr72748.c: New test. From-SVN: r238956
2016-08-01re PR tree-optimization/71818 (ICE in as_a, at is-a.h:192 w/ -O2 ↵Alan Hayward4-1/+45
-ftree-vectorize) 2016-08-01 Alan Hayward <alan.hayward@arm.com> gcc/ PR tree-optimization/71818 * tree-vect-loop-manip.c (vect_can_advance_ivs_p): Don't advance IVs with non invariant evolutions testsuite/ PR tree-optimization/71818 * gcc.dg/vect/pr71818.c: New From-SVN: r238955
2016-08-01Change dump expectation in PR71857Martin Liska2-1/+6
PR tree-optimization/71857 * gcc.dg/tree-ssa/ivopt_mult_4.c: Change expectation. From-SVN: r238953
2016-08-01re PR target/72767 ([avr] Some branches report too small insn length)Georg-Johann Lay2-2/+8
PR target/72767 * config/avr/avr.md (length) [branch]: Correct insn length attribute for forward branches. From-SVN: r238948
2016-08-01extend.texi (AVR Built-in Functions): Document __builtin_avr_nops.Georg-Johann Lay4-0/+42
* doc/extend.texi (AVR Built-in Functions): Document __builtin_avr_nops. * config/avr/builtins.def (NOPS): New. * config/avr/avr.c (avr_expand_nops): New static function. (avr_expand_builtin): Use it to handle AVR_BUILTIN_NOPS. From-SVN: r238947
2016-08-01[AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STPKyrylo Tkachov4-2/+34
* config/aarch64/aarch64.c (aarch64_classify_address): Use DImode when performing aarch64_offset_7bit_signed_scaled_p check for TImode LDP/STP addresses. * gcc.target/aarch64/ldp_stp_unaligned_1.c: New test. From-SVN: r238938
2016-08-01aarch64.c (vulcan_tunings): Update vulcan L1 cache_line_size.Virendra Pathak2-1/+6
2016-08-01 Virendra Pathak <virendra.pathak@broadcom.com> * config/aarch64/aarch64.c (vulcan_tunings): Update vulcan L1 cache_line_size. From-SVN: r238937
2016-08-01extend shift count warnings to vector typesJan Beulich6-27/+148
gcc/c/ 2016-08-01 Jan Beulich <jbeulich@suse.com> * c-fold.c (c_fully_fold_internal): Also emit shift count warnings for vector types. * c-typeck.c (build_binary_op): Likewise. gcc/testsuite/ 2016-08-01 Jan Beulich <jbeulich@suse.com> * gcc.dg/vshift-6.c, gcc.dg/vshift-7.c: New. From-SVN: r238936
2016-08-01Daily bump.GCC Administrator1-1/+1
From-SVN: r238933
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