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2020-05-17Move array bounds checking out of vrp_prop and into its own class.Aldy Hernandez2-37/+73
2020-05-17Daily bump.GCC Administrator1-1/+1
2020-05-16coroutines: Implicitly movable objects should use move CTORs for co_return.Iain Sandoe4-35/+150
This is a case where the standard contains conflicting information. after discussion between implementators, the accepted intent is of [class.copy.elision]. This amends the handling of co_return statements to follow that. gcc/cp/ChangeLog: 2020-05-16 Iain Sandoe <iain@sandoe.co.uk> * coroutines.cc (finish_co_return_stmt): Implement rules from [class.copy.elision] /3. gcc/testsuite/ChangeLog: 2020-05-16 Iain Sandoe <iain@sandoe.co.uk> * g++.dg/coroutines/co-return-syntax-10-movable.C: New test.
2020-05-16Consolidate a couple peepholes and improve peepholes that combine stack ↵Jeff Law3-41/+43
allocations with stack stores. * config/h8300/h8300.md (SFI iterator): New iterator for SFmode and SImode. * config/h8300/peepholes.md (memory comparison): Use mode iterator to consolidate 3 patterns into one. (stack allocation and stack store): Handle SFmode. Handle 8 byte allocations.
2020-05-16Daily bump.GCC Administrator1-1/+1
2020-05-15c++: decltype of invalid non-dependent expr [PR57943]Patrick Palka4-0/+26
We sometimes fail to reject an invalid non-dependent operand to decltype when inside a template, because finish_decltype_type resolves the decltype to the TREE_TYPE of the operand before we ever instantiate and fully process the operand. Fix this by adding a call to instantiate_non_dependent_expr_sfinae in finish_decltype_type. gcc/cp/ChangeLog: PR c++/57943 * semantics.c (finish_decltype_type): Call instantiate_non_dependent_expr_sfinae on the expression. gcc/testsuite/ChangeLog: PR c++/57943 * g++.dg/cpp0x/decltype76.C: New test.
2020-05-15libgo: only build syscall test with -static if it worksIan Lance Taylor1-1/+1
Test whether -static works, and use it if possible. This time for sure. For PR go/95061 Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/234024
2020-05-15c++: Enable coroutines with -std=c++20.Jason Merrill5-12/+17
Now that GCC 10 is out it seems time. People can still choose to disable coroutines with -fno-coroutines. This also switches the coroutines testsuite to run in C++20 mode. The change to coro.h is only necessary for co-await-11-forwarding.C; we could alternatively #include <utility> just in that file. gcc/c-family/ChangeLog 2020-05-15 Jason Merrill <jason@redhat.com> * c-opts.c (set_std_cxx20): Set flag_coroutines. gcc/testsuite/ChangeLog 2020-05-15 Jason Merrill <jason@redhat.com> * g++.dg/coroutines/coro.h: Always #include <utility>. * g++.dg/coroutines/coroutines.exp (DEFAULT_COROFLAGS): Use -std=c++20.
2020-05-15analyzer: Remove stray semicolon.Jason Merrill1-1/+1
2020-05-15rs6000: BU_FUTURE_MISC_2 requires powerpc64Segher Boessenkool2-1/+7
BU_FUTURE_MISC_2 is (currently) only used for instructions that require 64-bit registers. 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require RS6000_BTM_POWERPC64.
2020-05-15rs6000/testsuite: Use the int128 selector where neededSegher Boessenkool7-0/+15
Tests that use the __int128 type need to use the int128 selector. 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org> gcc/testsuite/ * gcc.target/powerpc/vec-gnb-0.c: Use int128 effective target. * gcc.target/powerpc/vec-gnb-1.c: Ditto. * gcc.target/powerpc/vec-gnb-2.c: Ditto. * gcc.target/powerpc/vec-ternarylogic-8.c: Ditto. * gcc.target/powerpc/vec-ternarylogic-9.c: Ditto. * gcc.target/powerpc/vec-ternarylogic-10.c: Ditto.
2020-05-15rs6000/testsuite: Use lp64 in cnttzdm-0.cSegher Boessenkool2-0/+5
2020-05-15 Segher Boessenkool <segher@kernel.crashing.org> gcc/testsuite/ * gcc.target/powerpc/cnttzdm-0.c: Use lp64.
2020-05-15rs6000/testsuite: Don't use powerpc64 effective targetSegher Boessenkool8-7/+17
The powerpc64 effective target unfortunately does not mean the target has 64-bit instructions enabled (i.e., -mpowerpc64): instead, it means that the assembler supports it. Let's use the lp64 effective target instead for these tests. 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org> gcc/testsuite/ * gcc.target/powerpc/cntlzdm-0.c: Use lp64 instead of powerpc64. * gcc.target/powerpc/cntlzdm-1.c: Ditto. * gcc.target/powerpc/cnttzdm-1.c: Ditto. * gcc.target/powerpc/pdep-0.c: Ditto. * gcc.target/powerpc/pdep-1.c: Ditto. * gcc.target/powerpc/pextd-0.c: Ditto. * gcc.target/powerpc/pextd-1.c: Ditto.
2020-05-15rs6000/testsuite: Use -mdejagnu-cpu= instead of -mcpu=Segher Boessenkool23-22/+47
A bunch of new cases snuck in. 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org> gcc/testsuite/ * gcc.target/powerpc/pdep-0.c: Change -mcpu= to -mdejagnu-cpu=. * gcc.target/powerpc/pdep-1.c: Ditto. * gcc.target/powerpc/pextd-0.c: Ditto. * gcc.target/powerpc/pextd-1.c: Ditto. * gcc.target/powerpc/pr90763.c: Ditto. * gcc.target/powerpc/pr91275.c: Ditto. * gcc.target/powerpc/pr92796.c: Ditto. * gcc.target/powerpc/pr93658.c: Ditto. * gcc.target/powerpc/pr93800.c: Ditto. * gcc.target/powerpc/setbceq.c: Ditto. * gcc.target/powerpc/setbcge.c: Ditto. * gcc.target/powerpc/setbcgt.c: Ditto. * gcc.target/powerpc/setbcle.c: Ditto. * gcc.target/powerpc/setbclt.c: Ditto. * gcc.target/powerpc/setbcne.c: Ditto. * gcc.target/powerpc/setnbceq.c: Ditto. * gcc.target/powerpc/setnbcge.c: Ditto. * gcc.target/powerpc/setnbcgt.c: Ditto. * gcc.target/powerpc/setnbcle.c: Ditto. * gcc.target/powerpc/setnbclt.c: Ditto. * gcc.target/powerpc/setnbcne.c: Ditto. * gcc.target/powerpc/xxgenpc-runnable.c: Ditto.
2020-05-15c++: Revert unnecessary parts of fix for [PR90996]Patrick Palka4-19/+35
The process_init_constructor_array part of my PR90996 patch turns out to be neither necessary nor sufficient to make the pr90996.C testcase work, and I wasn't able to come up with a testcase that demonstrates this part is ever necessary. gcc/cp/ChangeLog: Revert: 2020-04-07 Patrick Palka <ppalka@redhat.com> PR c++/90996 * typeck2.c (process_init_constructor_array): Propagate CONSTRUCTOR_PLACEHOLDER_BOUNDARY up from each element initializer to the array initializer. gcc/testsuite/ChangeLog: PR c++/90996 * g++.dg/cpp1y/pr90996.C: Turn into execution test to verify that each PLACEHOLDER_EXPR gets correctly resolved.
2020-05-15PR c++/93286 - ICE with __is_constructible and variadic template.Jason Merrill4-183/+101
My GCC 10 patch for 93286 fixed the missing piece in tsubst's handling of lists vs. that in tsubst_copy_and_build, but it would be better to share the code between them. gcc/cp/ChangeLog 2020-05-15 Jason Merrill <jason@redhat.com> PR c++/93286 - ICE with __is_constructible and variadic template. * pt.c (tsubst_tree_list): New. (tsubst, tsubst_copy_and_build): Use it. * decl2.c (is_late_template_attribute): Handle error_mark_node args.
2020-05-15Fix undefined behavior in pr33922.c.Aldy Hernandez1-2/+1
It was causing evrp to perform an undefined transformation that rvrp was not doing and causing a trap.
2020-05-15[Fortran] OpenMP 5 – permit more sharing clauses for SIMD (PR94690)Tobias Burnus4-11/+82
gcc/fortran/ PR fortran/94690 * openmp.c (resolve_omp_do): Permit more clauses for SIMD iteration variables. gcc/testsuite/ PR fortran/94690 * gfortran.dg/gomp/openmp-simd-4.f90: New test.
2020-05-15i386: Allow SI, DI and TImode pushes from XMM registersUros Bizjak2-26/+62
Also change XMM register constraint from "x" to "v" in FP push insns. gcc/ChangeLog: 2020-05-15 Uroš Bizjak <ubizjak@gmail.com> * config/i386/i386.md (SWI48DWI): New mode iterator. (*push<mode>2): Allow XMM registers. (*pushdi2_rex64): Ditto. (*pushsi2_rex64): Ditto. (*pushsi2): Ditto. (push XMM reg splitter): New splitter (*pushdf) Change "x" operand constraint to "v". (*pushsf_rex64): Ditto. (*pushsf): Ditto.
2020-05-15c++: Fix thinkos in template_args_equal change.Nathan Sidwell2-2/+6
Arseny Solokha noticed I'd flubbed this patch, and it was not saying what I thought it was saying. Unfortunately that didn't break anything (otherwise I'd've noticed). Fixed thusly. * pt.c (template_args_equal): Fix thinkos in previous 'cleanup'.
2020-05-15tree-optimization/92260 - improve fixRichard Biener2-13/+12
This improves the fix for PR92260 changing the number of vector computation to the canonical one, not needing to look at the using stmt. 2020-05-15 Richard Biener <rguenther@suse.de> PR tree-optimization/92260 * tree-vect-slp.c (vect_get_constant_vectors): Compute the number of vector stmts in a canonical way.
2020-05-15Adjusts tests for rvrp execution.Aldy Hernandez35-34/+39
The following are the known regressions: > FAIL: gfortran.dg/integer_exponentiation_2.f90 -O2 (test for excess errors) > FAIL: gfortran.dg/integer_exponentiation_2.f90 -O3 -fomit-frame-pointer -funroll-loops -fpeel -loops -ftracer -finline-functions (test for excess errors) > FAIL: gfortran.dg/integer_exponentiation_2.f90 -O3 -g (test for excess errors) > FAIL: gfortran.dg/pr41043.f90 -O (test for excess errors) Fortran timeouts during compilation. Will analyze next week. > FAIL: gcc.dg/tree-ssa/pr88367.c scan-tree-dump-times optimized "bar \\(\\);" 2 -fno-delete-null-pointer-checks problem. Discussing with Andrew.
2020-05-15Fix clang [-Wmisleading-indentation] in hsa-gen.c.Martin Liska2-7/+12
* hsa-gen.c (get_symbol_for_decl): Fix misleading indentation warning.
2020-05-15WIP amdgcn: use unsigned extend for lshiftrtAndrew Stubbs2-1/+5
This fixes a wrong-code logic error in a previous patch. Detected by gcc.c-torture/execute/pr53645-2.c. 2020-05-15 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
2020-05-15tree-optimization/95133 - avoid abnormal edges in path splittingRichard Biener4-2/+34
When path splitting tries to detect a CFG diamond make sure it is composed of normal (non-EH, not abnormal) edges. Otherwise CFG manipulation later may fail. 2020-05-15 Richard Biener <rguenther@suse.de> PR tree-optimization/95133 * gimple-ssa-split-paths.c (find_block_to_duplicate_for_splitting_paths): Check for normal edges. * gcc.dg/pr95133.c: New testcase.
2020-05-15arm: Add support for interrupt routines to reg_needs_saving_pChristophe Lyon2-7/+27
reg_needs_saving_p is only used when dealing with non-interrupt routines, but it makes sense to extend it to support that context too, and make arm_compute_save_reg0_reg12_mask use it. Save only live registers for non-leaf functions, but assume a callee could clobber any register. 2020-05-15 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm.c (reg_needs_saving_p): Add support for interrupt routines. (arm_compute_save_reg0_reg12_mask): Use reg_needs_saving_p.
2020-05-15[OpenMP] Fix 'omp exit data' for Fortran arrays (PR 94635)Tobias Burnus4-1/+35
gcc/ PR middle-end/94635 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with OMP_TARGET_EXIT_DATA, use 'release:' unless the associated item is 'delete:'. gcc/testsuite PR middle-end/94635 * gfortran.dg/gomp/target-exit-data.f90: New.
2020-05-15Remove gori_computable.Aldy Hernandez1-53/+0
Now that ranger VRP is running, there is no need for this.
2020-05-15i386: Add V2SFmode hadd/hsub instructions [PR95046]Uros Bizjak4-21/+108
PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which implies SSE2. These instructions are only generated via builtins, and since several 3dNow! insns have no corresponding SSE alternative, we can't avoid MMX registers with 3dNow! builtins anyway. Add SSE3/AVX alternatives to the insn pattern, so compiler will be able to use XMM registers when available, but don't prevent MMX registers, since they are needed when SSE3 is not active. Add additional generic insn patterns, used by the combiner to synthesize horizontal V2SFmode add/sub instructions. These patterns are active for TARGET_MMX_WITH_SSE only, and use only XMM registers. gcc/ChangeLog: PR target/95046 * config/i386/i386.md (isa): Add sse3_noavx. (enabled): Handle sse3_noavx. * config/i386/mmx.md (mmx_haddv2sf3): New expander. (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX alternatives. Match commutative vec_select selector operands. (*mmx_haddv2sf3_low): New insn pattern. (*mmx_hsubv2sf3): Add SSE/AVX alternatives. (*mmx_hsubv2sf3_low): New insn pattern. testsuite/ChangeLog: PR target/95046 * gcc.target/i386/pr95046-8.c: New test.
2020-05-15Enabled evrp trapping when IL changes but only iff -frvrp1-changes is set.Aldy Hernandez5-4/+35
Also, implement global -frvrp-changes that overrides the individual pass settings.
2020-05-15i386: Add V2SFmode hadd/hsub instructions [PR95046]Uros Bizjak1-0/+22
PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which implies SSE2. These instructions are only generated via builtins, and since several 3dNow! insns have no corresponding SSE alternative, we can't avoid MMX registers with 3dNow! builtins anyway. Add SSE3/AVX alternatives to the insn pattern, so compiler will be able to use XMM registers when available, but don't prevent MMX registers, since they are needed when SSE3 is not active. Add additional generic insn patterns, used by the combiner to synthesize horizontal V2SFmode add/sub instructions. These patterns are active for TARGET_MMX_WITH_SSE only, and use only XMM registers. gcc/ChangeLog: PR target/95046 * config/i386/i386.md (isa): Add sse3_noavx. (enabled): Handle sse3_noavx. * config/i386/mmx.md (mmx_haddv2sf3): New expander. (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX alternatives. Match commutative vec_select selector operands. (*mmx_haddv2sf3_low): New insn pattern. (*mmx_hsubv2sf3): Add SSE/AVX alternatives. (*mmx_hsubv2sf3_low): New insn pattern. testsuite/ChangeLog: PR target/95046 * gcc.target/i386/pr95046-8.c: New test.
2020-05-15tree-optimization/33315 - common stores during sinkingRichard Biener6-5/+242
This implements commoning of stores to a common successor in a simple ad-hoc way. I've decided to put it into the code sinking pass since, well, it sinks stores. It's still separate since it does not really sink code into less executed places. It's ad-hoc since it does not perform any dataflow or alias analysis but simply only considers trailing stores in a block, iteratively though. If the stores are from different values a PHI node is inserted to merge them. gcc.dg/tree-ssa/split-path-7.c shows that path splitting will eventually undo this very transform, I've decided to not bother with it and simply disable sinking for the particular testcase. Doing this transform is good for code size when the stores are from constants, once we have to insert PHIs the situation becomes less clear but it's a transform we do elsewhere as well (cselim for one), and reversing the transform should be easy. 2020-05-15 Richard Biener <rguenther@suse.de> PR tree-optimization/33315 * tree-ssa-sink.c: Include tree-eh.h. (sink_stats): Add commoned member. (sink_common_stores_to_bb): New function implementing store commoning by sinking to the successor. (sink_code_in_bb): Call it, pass down TODO_cleanup_cfg returned. (pass_sink_code::execute): Likewise. Record commoned stores in statistics. * gcc.dg/tree-ssa/ssa-sink-13.c: New testcase. * gcc.dg/tree-ssa/ssa-sink-14.c: Likewise. * gcc.dg/tree-ssa/split-path-7.c: Disable sinking.
2020-05-15Remove vr_values_tester.Aldy Hernandez4-44/+4
It is no longer needed as we are running rvrp[12] and verifying usage the trap code.
2020-05-15Add loop_ranger::range_of_ssa_name that calls SCEV.Aldy Hernandez2-0/+21
2020-05-15Guard indent calculations in trace_ranger by dumping().Aldy Hernandez1-4/+4
This keeps the indentation from going haywire when GORI dumping is turned on and off during a compilation unit.
2020-05-15Move all branch local machinery into their own files (misc.*).Aldy Hernandez10-238/+607
Move all the classes and support routines that are not meant to be upstreamed, into their own files. Also, add the initial cut of the classes needed to compare and trap when IL changes are noticed in evrp. This is disabled for now.
2020-05-15Turn off simplify_conversion_using_ranges when rvrp1 IL changes are enabled.Aldy Hernandez1-0/+6
This conversion has nothing to do with ranges, and the way it uses global ranges versus local ranges is interfering with our ability to diagnose differences between evrp and rvrp1.
2020-05-15Turn off GORI/ranger dumps while dumping known ranges.Aldy Hernandez1-0/+3
Since the ranger is on-demand, dumping the known range for each SSA use causes us to calculate the ranges ahead of time, and confuse the listing. For now, turn it off, so the range calculation isn't displayed.
2020-05-15Add context stmt for simplify_using_ranges.Aldy Hernandez2-13/+18
This gives better ranges for the simplifier class since it's using the context in which the statement appears.
2020-05-15Return a better range for lshift::op1_range if LHS does not contain a 0.Aldy Hernandez1-6/+10
2020-05-15Run copy propagation before evrp.Aldy Hernandez3-2/+28
2020-05-14Fold (add -1; zero_ext; add +1) operations to zero_ext when not ↵Xionghu Luo4-1/+78
overflow(PR37451, PR61837) This "subtract/extend/add" existed for a long time and still annoying us (PR37451, part of PR61837) when converting from 32bits to 64bits, as the ctr register is used as 64bits on powerpc64, Andraw Pinski had a patch but caused some issue and reverted by Joseph S. Myers(PR37451, PR37782). Andraw: http://gcc.gnu.org/ml/gcc-patches/2008-09/msg01070.html http://gcc.gnu.org/ml/gcc-patches/2008-10/msg01321.html Joseph: https://gcc.gnu.org/legacy-ml/gcc-patches/2011-11/msg02405.html We still can do the simplification from "subtract/zero_ext/add" to "zero_ext" when loop iterations is known to be LT than MODE_MAX (only do simplify when counter+0x1 NOT overflow). Bootstrap and regression tested pass on Power8-LE. gcc/ChangeLog 2020-05-15 Xiong Hu Luo <luoxhu@linux.ibm.com> PR rtl-optimization/37451, part of PR target/61837 * loop-doloop.c (doloop_simplify_count): New function. Simplify (add -1; zero_ext; add +1) to zero_ext when not wrapping. (doloop_modify): Call doloop_simplify_count. gcc/testsuite/ChangeLog 2020-05-15 Xiong Hu Luo <luoxhu@linux.ibm.com> PR rtl-optimization/37451, part of PR target/61837 * gcc.target/powerpc/doloop-2.c: New test.
2020-05-15Daily bump.GCC Administrator1-1/+1
2020-05-14Skip jit tests for targets that don't support -lgccjitH.J. Lu5-0/+35
Since libgccjit.so is linked into jit tests, skip jit tests for targets that don't support -lgccjit. gcc/ PR jit/94778 * doc/sourcebuild.texi: Document effective target lgccjit. gcc/testsuite/ PR jit/94778 * jit.dg/jit.exp: Skip jit tests for targets that don't support -lgccjit. * lib/target-supports.exp (check_effective_target_lgccjit): New.
2020-05-14c++: Fix deferred noexcept on constructor [PR93901].Jason Merrill2-28/+32
My change in r10-4394 to only update clones when we actually instantiate a deferred noexcept-spec broke this because deferred parsing updates the primary function but not the clones. For GCC 10 I just reverted that change; this patch adjusts maybe_instantiate_noexcept to update only the clone passed as the argument. gcc/cp/ChangeLog 2020-05-14 Jason Merrill <jason@redhat.com> PR c++/93901 * pt.c (maybe_instantiate_noexcept): Change clone handling.
2020-05-14libgo: only build syscall test with -static on GNU/LinuxIan Lance Taylor1-1/+1
For PR go/95061 Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/234019
2020-05-14amdgcn: fix vcc clobber in vector load/storeAndrew Stubbs6-51/+217
This switches the code that expands scalar addresses to vectors of addresses from using VCC to using CC_SAVE_REG, for the lo-part to hi-part carry values. These were fine in code expanded in earlier passes, but addresses expanded late, such as for stack spills or reloads, could clobber live VCC values, causing execution failures. This is the first target-specific testcase for GCN, so the new .exp file is included. 2020-05-14 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a define_expand, and rename the original to ... (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand. (add<mode>3_zext_dup_exec): Likewise, with ... (add<mode>3_vcc_zext_dup_exec): ... this. (add<mode>3_zext_dup2): Likewise, with ... (add<mode>3_zext_dup_exec): ... this. (add<mode>3_zext_dup2_exec): Likewise, with ... (add<mode>3_zext_dup2): ... this. * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch addv64di3_zext* calls to use addv64di3_vcc_zext*. gcc/testsuite/ * testsuite/gcc.target/gcn/gcn.exp: New file. * testsuite/gcc.target/gcn/vcc-clobber.c: New file.
2020-05-14i386: Add V2DFmode float trunc/extend functions [PR95046]Uros Bizjak4-0/+69
gcc/ChangeLog: PR target/95046 * config/i386/sse.md (truncv2dfv2df2): New insn pattern. (extendv2sfv2df2): Ditto. testsuite/ChangeLog: PR target/95046 * gcc.target/i386/pr95046-7.c: New test.
2020-05-14Adjust gimple_range_adjustment so it works for imagpart and pointer_diff.Aldy Hernandez2-6/+74
2020-05-14Fix off-by-one error in popcount folding.Aldy Hernandez1-1/+1
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