aboutsummaryrefslogtreecommitdiff
path: root/gcc
AgeCommit message (Collapse)AuthorFilesLines
2025-10-24x86: Optimize copysign (x, const_double)H.J. Lu12-20/+249
After commit 3f176e1adc6bc9cc2c21222d776b51d9f43cb66b Author: Tamar Christina <tamar.christina@arm.com> Date: Thu Nov 9 13:59:39 2023 +0000 middle-end: optimize fneg (fabs (x)) to copysign (x, -1) [PR109154] fneg (fabs (x)) is expanded to copysign (x, -1). Swap constraints for operands[1] and operands[2] in copysign<mode>3 pattern to optimize y = copysign (x, const_double) instead of y = copysign (const_double, x) Simplify y = copysign (x, positive_const_double) to y = ~signbit_mask & x and y = copysign (x, negative_const_double) to y = signbit_mask | x gcc/ PR target/99930 PR target/122323 * config/i386/i386-expand.cc (ix86_expand_copysign): Swap operands[1] with operands[2]. Optimize copysign (x, const_double) instead of copysign (const_double, x). * config/i386/i386.md (copysign<mode>3): Swap constraints for operands[1] and operands[2]. gcc/testsuite/ PR target/99930 PR target/122323 * gcc.target/i386/builtin-copysign-2.c: New test. * gcc.target/i386/builtin-copysign-3.c: Likewise. * gcc.target/i386/builtin-copysign-4.c: Likewise. * gcc.target/i386/builtin-copysign-5.c: Likewise. * gcc.target/i386/builtin-copysign-6.c: Likewise. * gcc.target/i386/builtin-copysign-7.c: Likewise. * gcc.target/i386/builtin-copysign-8a.c: Likewise. * gcc.target/i386/builtin-copysign-8b.c: Likewise. * gcc.target/i386/builtin-fabs-1.c: Likewise. * gcc.target/i386/builtin-fabs-2.c: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com> (cherry picked from commit c3b0ecf04f8c14360cc02c737446c029038a95f7)
2025-10-24Daily bump.GCC Administrator2-1/+9
2025-10-23ChangeLog.omp bumpAndrew Stubbs2-1/+19
2025-10-23Revert "openmp: Add -foffload-memory"Andrew Stubbs3-38/+0
This reverts commit 6c86aec56567424416e52372473c8f0694ce65a9.
2025-10-23Revert "openmp: -foffload-memory=pinned"Andrew Stubbs2-69/+0
This reverts commit e13ab24bf919a7c4dc30dcfc9fafa9c6349a90a7.
2025-10-23testsuite: arm: [MVE] Relax expected code for vbicq_f [PR122223]Christophe Lyon1-2/+2
The original versions of the pr122223.c test only took into account code generated with -mfloat-abi=hard, which uses q0. With -mfloat-abi=softfp, this can be any Q register, so replace q0 with a suitable regex. gcc/testsuite/ChangeLog: PR target/122223 * gcc.target/arm/mve/intrinsics/pr122223.c: Relax expected code. (cherry picked from commit a52888dc71924afb6cd187b0e5f18d2be4c68a07)
2025-10-23Daily bump.GCC Administrator4-1/+24
2025-10-22ChangeLog.omp bumpPaul-Antoine Arras6-1/+187
2025-10-22testsuite: Fix local labels [PR122378]Paul-Antoine Arras2-2/+2
r16-4540-g80af807e52e4f4 exposed a bug in two testcases where the declaration of local labels was wrongly commented out. That caused "duplicate label" errors. Uncommenting declarations fixes it. PR middle-end/122378 gcc/testsuite/ChangeLog: * c-c++-common/gomp/attrs-metadirective-2.c: Uncomment local label declaration. * c-c++-common/gomp/metadirective-2.c: Likewise. (cherry picked from commit f88c3d76fc8820a9f548af460a2b84f879255ed7)
2025-10-22OpenMP: Handle non-executable directives in intervening code [PR120180,PR122306]Paul-Antoine Arras17-170/+510
OpenMP 6 permits non-executable directives in intervening code; this commit adds support for a sensible subset, namely metadirectives, nothing, assume, and 'error at(compilation)'. Also handle the special case where a metadirective can be resolved at parse time to 'omp nothing'. This fixes a build issue that affects 10 out 12 SPECaccel benchmarks. Co-authored by: Tobias Burnus <tburnus@baylibre.com> PR c/120180 PR fortran/122306 gcc/c/ChangeLog: * c-parser.cc (c_parser_pragma): Accept a subset of non-executable OpenMP directives in intervening code. (c_parser_omp_error): Reject 'error at(execution)' in intervening code. (c_parser_omp_metadirective): Return early if only one selector matches and it resolves to 'omp nothing'. gcc/cp/ChangeLog: * parser.cc (cp_parser_omp_metadirective): Return early if only one selector matches and it resolves to 'omp nothing'. (cp_parser_omp_error): Reject 'error at(execution)' in intervening code. (cp_parser_pragma): Accept a subset of non-executable OpenMP directives as intervening code. gcc/fortran/ChangeLog: * gfortran.h (enum gfc_exec_op): Add EXEC_OMP_FIRST_OPENMP_EXEC and EXEC_OMP_LAST_OPENMP_EXEC. * openmp.cc (gfc_match_omp_context_selector): Remove static. Remove checks on score. Add cleanup. Remove checks on trait properties. (gfc_match_omp_context_selector_specification): Remove static. Adjust calls to gfc_match_omp_context_selector. (gfc_match_omp_declare_variant): Adjust call to gfc_match_omp_context_selector_specification. (match_omp_metadirective): Likewise. (icode_code_error_callback): Reject all statements except 'assume' and 'metadirective'. (gfc_resolve_omp_context_selector): New function. (resolve_omp_metadirective): Skip metadirectives which context selectors can be statically resolved to false. Replace metadirective by its body if only 'nothing' remains. (gfc_resolve_omp_declare): Call gfc_resolve_omp_context_selector for each variant. gcc/testsuite/ChangeLog: * c-c++-common/gomp/imperfect1.c: Adjust dg-error. * c-c++-common/gomp/imperfect4.c: Likewise. * c-c++-common/gomp/pr120180.c: Move to... * c-c++-common/gomp/pr120180-1.c: ...here. Remove dg-error. * g++.dg/gomp/attrs-imperfect1.C: Adjust dg-error. * g++.dg/gomp/attrs-imperfect4.C: Likewise. * gfortran.dg/gomp/declare-variant-2.f90: Adjust dg-error. * gfortran.dg/gomp/declare-variant-20.f90: Likewise. * c-c++-common/gomp/pr120180-2.c: New test. * g++.dg/gomp/pr120180-1.C: New test. * gfortran.dg/gomp/pr120180-1.f90: New test. * gfortran.dg/gomp/pr120180-2.f90: New test. * gfortran.dg/gomp/pr122306-1.f90: New file. * gfortran.dg/gomp/pr122306-2.f90: New file. (cherry picked from commit 80af807e52e4f4c480454e5a54aaeb7ce44556fd)
2025-10-22c++: Fix up RAW_DATA_CST handling in braced_list_to_string [PR122302]Jakub Jelinek3-0/+79
The following testcase is miscompiled, because a RAW_DATA_CST tree node is shared by multiple CONSTRUCTORs and when the braced_list_to_string function changes one to extend the RAW_DATA_CST over the single preceding and single succeeding INTEGER_CST, it changes the RAW_DATA_CST in the other CONSTRUCTOR where the elts around it are still present. Fixed by tweaking a copy of it instead, like we handle it in other spots. 2025-10-22 Jakub Jelinek <jakub@redhat.com> PR c++/122302 * c-common.cc (braced_list_to_string): Call copy_node on RAW_DATA_CST before changing RAW_DATA_POINTER and RAW_DATA_LENGTH on it. * g++.dg/cpp0x/pr122302.C: New test. * g++.dg/cpp/embed-27.C: New test. (cherry picked from commit 79b49977b1894a0a5eea3d2125eb6546b9d0cf02)
2025-10-22i386: Correct cpu codename value for unknown model numberHaochen Jiang1-7/+13
There are several changes for features enabled on cpus. r16-1666 disabled CLDEMOTE on clients. r16-2224 removed Key locker since Panther Lake and Clearwater forest. r16-4436 disabled PREFETCHI on Panther Lake. The patches caused the current return guess value not aligned for host_detect_local_cpu meeting the unknown model number. Correct the logic according to the features enabled. This patch will also backport to GCC14 and GCC15. gcc/ChangeLog: * config/i386/driver-i386.cc (host_detect_local_cpu): Correct the logic for unknown model number cpu guess value.
2025-10-22Daily bump.GCC Administrator3-1/+29
2025-10-21arm: [MVE] Fix operands order in vbicq_f [PR122223]Christophe Lyon2-2/+27
The operands of the floating-point version of vbicq were swapped, this patch fixes this. gcc/ChangeLog: PR target/122223 * config/arm/mve.md (@mve_vbicq_f<mode>): Fix operands order. gcc/testsuite/ChangeLog: PR target/122223 * gcc.target/arm/mve/intrinsics/pr122223.c: New test. (cherry picked from commit 81e226440381cc3e033df7e58cc7793c9b4b4e25)
2025-10-21aarch64: Fix ICE when op2 is zero for SVE2 saturating add intrinsics.Jennifer Schmitz2-1/+36
When op2 in SVE2 saturating add intrinsics (svuqadd, svsqadd) is a zero vector and predication is _z, an ICE in vregs occurs, e.g. for svuint8_t foo (svbool_t pg, svuint8_t op1) { return svsqadd_u8_z (pg, op1, svdup_s8 (0)); } The insn failed to match the pattern (aarch64-sve2.md): ;; Predicated binary operations with no reverse form, merging with zero. ;; At present we don't generate these patterns via a cond_* optab, ;; so there's no correctness requirement to handle merging with an ;; independent value. (define_insn_and_rewrite "*cond_<sve_int_op><mode>_z" [(set (match_operand:SVE_FULL_I 0 "register_operand") (unspec:SVE_FULL_I [(match_operand:<VPRED> 1 "register_operand") (unspec:SVE_FULL_I [(match_operand 5) (unspec:SVE_FULL_I [(match_operand:SVE_FULL_I 2 "register_operand") (match_operand:SVE_FULL_I 3 "register_operand")] SVE2_COND_INT_BINARY_NOREV)] UNSPEC_PRED_X) (match_operand:SVE_FULL_I 4 "aarch64_simd_imm_zero")] UNSPEC_SEL))] "TARGET_SVE2" {@ [ cons: =0 , 1 , 2 , 3 ] [ &w , Upl , 0 , w ] movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> [ &w , Upl , w , w ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> } "&& !CONSTANT_P (operands[5])" { operands[5] = CONSTM1_RTX (<VPRED>mode); } [(set_attr "movprfx" "yes")] ) because operands[3] and operands[4] were both expanded into the same register operand containing a zero vector by define_expand "@cond_<sve_int_op><mode>". This patch fixes the ICE by making a case distinction in function_expander::use_cond_insn that uses add_fixed_operand if fallback_arg == CONST0_RTX (mode), and otherwise add_input_operand (which was previously the default and allowed the expansion of the zero-vector fallback_arg to a register operand). The patch was bootstrapped and tested on aarch64-linux-gnu, no regression. OK for trunk? Alex Coplan pointed out in the bugzilla ticket that this ICE goes back to GCC 10. Shall we backport? Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com> Co-authored by: Richard Sandiford <rdsandiford@googlemail.com> gcc/ PR target/121599 * config/aarch64/aarch64-sve-builtins.cc (function_expander::use_cond_insn): Use add_fixed_operand if fallback_arg == CONST0_RTX (mode). gcc/testsuite/ PR target/121599 * gcc.target/aarch64/sve2/pr121599.c: New test.
2025-10-21Daily bump.GCC Administrator4-1/+18
2025-10-20hurd: Add OPTION_GLIBC_P and OPTION_GLIBCSvante Signell1-0/+4
GNU/Hurd uses glibc just like GNU/Linux. This is needed for gcc to notice that glibc supports split stack in finish_options. PR go/104290 gcc/ChangeLog: * config/gnu.h (OPTION_GLIBC_P, OPTION_GLIBC): Define. (cherry picked from commit 29eacf043b6e8560c5c42d67f7f9b11e4e2cb156)
2025-10-20Ada: Fix spurious warning for renaming of component of VFA recordEric Botcazou2-1/+31
This is a regression present on the mainline and all active branches: the compiler gives a spurious "is not referenced" warning for the renaming of a component of a Volatile_Full_Access record. gcc/ada/ PR ada/107536 * exp_ch2.adb (Expand_Renaming): Mark the entity as referenced. gcc/testsuite/ * gnat.dg/renaming18.adb: New test.
2025-10-20Daily bump.GCC Administrator1-1/+1
2025-10-19Daily bump.GCC Administrator1-1/+1
2025-10-18Daily bump.GCC Administrator2-1/+12
2025-10-17x86: Cast stride to __PTRDIFF_TYPE__ for AMX-MOVRS intrinsics. [PR122119]Hu, Lin11-6/+6
On 64-bit windows, long can't be used, because it is 32 bits. Use __PTRDIFF_TYPE__ instead of long. gcc/ChangeLog: PR target/122119 * config/i386/amxmovrsintrin.h (_tile_loaddrs_internal): Use __PTRDIFF_TYPE__ instead of long. (_tile_loaddrst1_internal): Ditto. (_tile_2rpntlvwz0rs_internal): Ditto. (_tile_2rpntlvwz0rst1_internal): Ditto. (_tile_2rpntlvwz1rs_internal): Ditto. (_tile_2rpntlvwz1rst1_internal): Ditto.
2025-10-17Daily bump.GCC Administrator2-1/+11
2025-10-16Error out stack-protector unavailability on AIXAyappan Perumal1-1/+3
stack-protector is not supported in GCC on AIX. This patch is to fail the compilation if -fstack-protector option is passed. gcc/ChangeLog: * config/rs6000/aix.h (SUBTARGET_DRIVER_SELF_SPECS): Error out when stack-protector option is used in AIX as it is not supported on AIX Approved By: Segher Boessenkool <segher@kernel.crashing.org> (cherry picked from commit dfb7e97dd214f7d8ca0fa970d81ad5ba805aaa8d)
2025-10-16Daily bump.GCC Administrator3-1/+26
2025-10-15aarch64: Fix pmsdsfr_el1 encodingAlice Carlotti2-2/+2
The encoding was fixed in Binutils in May 2024, but we didn't copy the fix to GCC at the time. gcc/ChangeLog: * config/aarch64/aarch64-sys-regs.def: Fix pmsdsfr_el1 encoding. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/rwsr-armv8p9.c: Fix pmsdsfr_el1 encoding.
2025-10-15aarch64, testsuite: Add -fchecking to test options [PR121772]Alex Coplan1-0/+1
I noticed while testing a backport of the PR121772 fix to GCC 13 that the test wasn't triggering the ICE as expected with the unpatched compiler. This turned out to be because the ICE is a checking ICE, and we configure by default with --enable-checking=release on the branches. Additionally, I hadn't noticed when doing the backports to 15 and 14 since there we still ICE later on in emit_move_insn even if we don't catch the invalid gimple with checking. I'm not too sure why the 13 branch doesn't see the emit_move_insn ICE, but it's somewhat irrelevant - the important thing is that adding -fchecking to the options makes the test fail as expected with an unpatched compiler (i.e. with a gimple checking failure), even on release branches. I considered applying this patch to just the release branches, but figured that trunk will at some point itself become a release branch, so it seems to make most sense just to apply it everywhere. I've checked that the test still passes with this patch, and still fails if I revert the PR121772 fix. gcc/testsuite/ChangeLog: PR tree-optimization/121772 * gcc.target/aarch64/torture/pr121772.c: Add -fchecking to dg-options. (cherry picked from commit 0c670d38455c788ac0447e3b86ba621521d44bce)
2025-10-15i386: Correct ISA set for Panther Lake and Diamond RapidsHaochen Jiang2-5/+5
In ISE, Panther Lake does not enable PREFETCHI and Diamond Rapids does not enable USER_MSR. Correct them accordingly. I will backport the patch to GCC15/14. For GCC14, only PTL will be backported. gcc/ChangeLog: * config/i386/i386.h (PTA_PANTHERLAKE): Remove PREFETCHI. (PTA_DIAMONDRAPIDS): Remove USER_MSR. * doc/invoke.texi: Correct documentation.
2025-10-15Daily bump.GCC Administrator5-1/+91
2025-10-14c++: pointer to auto member function [PR120757]Jason Merrill2-2/+26
Here r13-1210 correctly changed &A<int>::foo to not be considered type-dependent, but tsubst_expr of the OFFSET_REF got confused trying to tsubst a type that involved auto. Fixed by getting the type from the member rather than tsubst. PR c++/120757 gcc/cp/ChangeLog: * pt.cc (tsubst_expr) [OFFSET_REF]: Don't tsubst the type. gcc/testsuite/ChangeLog: * g++.dg/cpp1y/auto-fn66.C: New test. (cherry picked from commit ea6ef13d0fc4e020d8c405333153dad9eee1f18d)
2025-10-14gimplify: Fix up side-effect handling in 2nd __builtin_c[lt]zg argument ↵Jakub Jelinek2-1/+38
[PR122188] The patch from yesterday made me think about side-effects in the second argument of __builtin_c[lt]zg. When we change __builtin_c[lt]zg (x, y) when y is not INTEGER_CST into x ? __builtin_c[lt]zg (x) : y with evaluating x only once, we omit the side-effects in y unless x is not 0. That looks undesirable, we should evaluate side-effects in y unconditionally. 2025-10-09 Jakub Jelinek <jakub@redhat.com> PR c/122188 * c-gimplify.cc (c_gimplify_expr): Also gimplify the second operand before the COND_EXPR and use in COND_EXPR result of gimplification. * gcc.dg/torture/pr122188.c: New test. (cherry picked from commit 579de8f5295b05573d05f6e4102f1428f35c9f17)
2025-10-14gimplify: Fix up __builtin_c[lt]zg gimplification [PR122188]Jakub Jelinek2-1/+19
The following testcase ICEs during gimplification. The problem is that save_expr sometimes doesn't create a SAVE_EXPR but returns the original complex tree (COND_EXPR) and the code then uses that tree in 2 different spots without unsharing. As this is done during gimplification it wasn't unshared when whole body is unshared and because gimplification is destructive, the first time we gimplify it we destruct it and second time we try to gimplify it we ICE on it. Now, we could replace one a use with unshare_expr (a), but because this is a gimplification hook, I think easier than trying to create a save_expr is just gimplify the argument, then we know it is is_gimple_val and so something without side-effects and can safely use it twice. That argument would be the first thing to gimplify after return GS_OK anyway, so it doesn't change argument sequencing etc. 2025-10-08 Jakub Jelinek <jakub@redhat.com> PR c/122188 * c-gimplify.cc (c_gimplify_expr): Gimplify CALL_EXPR_ARG (*expr_p, 0) instead of calling save_expr on it. * c-c++-common/pr122188.c: New test. (cherry picked from commit bb22f7d4d63446c9095db32ca013a9b2182df7d9)
2025-10-14stmt: Handle %cc[name] in resolve_asm_operand_names [PR122133]Jakub Jelinek2-1/+16
Last year I've extended the asm template syntax in inline asm to support %cc0 etc., apparently the first 2 letter generic operand modifier. As the following testcase shows, I forgot to tweak the [foo] handling for it though. As final.cc will error on any % ISALPHA not followed by digit (with the exception of % c c digit), I think we can safely handle this for any 2 letters in between % and [, instead of hardcoding it for now only for %cc[ and changing it again next time we add something two-letter. 2025-10-06 Jakub Jelinek <jakub@redhat.com> PR middle-end/122133 * stmt.cc (resolve_asm_operand_names): Handle % and 2 letters followed by open square. * c-c++-common/toplevel-asm-9.c: New test. (cherry picked from commit 96c4a32cfec8c4b4c677de114164192cfd8ae54d)
2025-10-14widening_mul: Reset flow sensitive info in maybe_optimize_guarding_check ↵Jakub Jelinek2-0/+13
[PR122104] In PR95852 I've added an optimization where next to just pattern recognizing r = x * y; r / x != y or r = x * y; r / x == y as .MUL_OVERFLOW or negation thereof it also recognizes r = x * y; x && (r / x != y) or r = x * y; !x || (r / x == y) by optimizing the guarding condition to always true/false. The problem with that is that some value ranges recorded for the SSA_NAMEs in the formerly conditional, now unconditional basic block can be invalid. This patch fixes it by calling reset_flow_sensitive_info_in_bb if we optimize the guarding condition. 2025-10-04 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/122104 * tree-ssa-math-opts.cc (maybe_optimize_guarding_check): Call reset_flow_sensitive_info_in_bb on bb when optimizing out the guarding condition. * gcc.target/i386/pr122104.c: New test. (cherry picked from commit 867f777cee9f44027a3724fbad266c5cfb3a311f)
2025-10-14i386: Remove AMX-TRANSPOSE from Diamond RapidsHaochen Jiang2-3/+2
AMX-TRANSPOSE will be removed from Diamond Rapids according to ISE. Backported from trunk AMX-TRANSPOSE removal patch. gcc/ChangeLog: * config/i386/i386.h (PTA_DIAMONDRAPIDS): Remove AMX-TRANSPOSE. * doc/invoke.texi: Correct documentation.
2025-10-14Daily bump.GCC Administrator2-1/+7
2025-10-13match.pd: Do not canonicalize division by power 2 for {ROUND, CEIL}_DIVAvinash Jayakar1-3/+5
Canonicalization of unsigned division by power of 2 only applies to {TRUNC,FLOOR,EXACT}_DIV, therefore remove the same pattern for {CEIL,ROUND}_DIV, which was added in a previous commit. 2025-10-13 Avinash Jayakar <avinashd@linux.ibm.com> gcc/ChangeLog: PR tree-optimization/122213 * match.pd: Canonicalize unsigned pow2 div only for trunk, floor and exact div.
2025-10-13Daily bump.GCC Administrator1-1/+1
2025-10-12Daily bump.GCC Administrator3-1/+18
2025-10-11[PATCH] RISC-V: Detect wrap in shuffle_series_pattern [PR121845].Robin Dapp2-1/+74
Hi, In shuffle_series_pattern we use series_p to determine if the permute mask is a simple series. This didn't take into account that series_p also returns true for e.g. {0, 3, 2, 1} where the step is 3 and the indices form a series modulo 4. We emit vid + vmul in order to synthesize a series. In order to be always correct we would need a vrem afterwards still which does not seem worth it. This patch adds the modulo for VLA permutes and punts if we wrap around for VLS permutes. I'm not really certain whether we'll really see a wrapping VLA series (certainly we haven't so far in the test suite) but as we observed a VLS one here now it appears conservatively correct to module the indices. Regtested on rv64gcv_zvl512b. Regards Robin PR target/121845 gcc/ChangeLog: * config/riscv/riscv-v.cc (shuffle_series_patterns): Modulo indices for VLA and punt when wrapping for VLS. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr121845.c: New test. (cherry picked from commit 62631c39a788161ff2f686adf355d10443e0d899)
2025-10-11Daily bump.GCC Administrator1-1/+1
2025-10-10Daily bump.GCC Administrator2-1/+33
2025-10-09AVR: target/122222 - Add modules for __floatsidf, __floatunsidf.Georg-Johann Lay1-0/+60
PR target/122222 libgcc/config/avr/libf7/ * libf7-asm.sx (D_floatsidf, D_floatunsidf): New modules. * libf7-common.mk (F7_ASM_PARTS): Add D_floatsidf, D_floatunsidf. (F7F, g_dx): Remove floatunsidf, floatsidf. * libf7.c (f7_set_s32): Don't alias to f7_floatsidf. (f7_set_u32): Don't alias to f7_floatunsidf. * f7-renames.h: Rebuild * f7-wraps.h: Rebuild. gcc/testsuite/ * gcc.target/avr/pr122222-sitod.c: New test. (cherry picked from commit 078208cf15bb373dc7931d6b373689cdff70cdc5)
2025-10-09AVR: target/122220 - Let (int32_t) -0x1p31L return INT32_MIN.Georg-Johann Lay1-0/+23
PR target/122220 libgcc/config/avr/libf7/ * libf7-asm.sx (to_integer): Return 0x80... on negative overflow. gcc/testsuite/ * gcc.target/avr/pr122220.c: New test. (cherry picked from commit 3ea09e4d43278aa8d7b088a5f5438d921c48c411)
2025-10-09AVR: target/122210 - Add double -> fixed-point conversions.Georg-Johann Lay1-0/+98
PR target/122210 libgcc/config/avr/libf7/ * libf7-common.mk (F7_ASM_PARTS): Add D2<fx> modules. * libf7-asm.sx: Implement the D2<fx> modules. gcc/testsuite/ * gcc.target/avr/dtofx.c: New test. (cherry picked from commit b0bc615d9374ca6293996cf3afca8cabaca0defd)
2025-10-09AVR: target/122210 - Add fixed-point -> double conversions.Georg-Johann Lay1-0/+115
PR target/122210 libgcc/config/avr/libf7/ * libf7-common.mk (F7_ASM_PARTS): Add <fx>2D modules. * libf7-asm.sx: Implement the <fx>2D modules. gcc/testsuite/ * gcc.target/avr/fxtod.c: New test. (cherry picked from commit 7304e83f1f29c39df7a9de888d9c6d40b58c512a)
2025-10-09Daily bump.GCC Administrator3-1/+19
2025-10-08[PATCH v2] RISC-V: fix __builtin_round NaN handling [PR target/121652]Aurelien Jarno2-15/+28
__builtin_round() fails to correctly generate invalid exceptions for NaN inputs when -ftrapping-math is used (which is the default). According to the specification, an invalid exception should be raised for sNaN, but not for qNaN. Commit f12a27216952 ("RISC-V: fix __builtin_round clobbering FP...") attempted to avoid raising an invalid exception for qNaN by saving and restoring the FP exception flags. However this inadvertently suppressed the invalid exception for sNaN as well. Instead of saving/restoring fflags, this patch uses the same approach than the well tested GLIBC round implementation. When flag_trapping_math is enabled, it first checks whether the input is a NaN using feq.s/d. In that case it adds the input value with itself to possibly convert sNaN into qNaN. With this change, the glibc testsuite passes again. The generated code with -ftrapping-math now looks like: convert_float_to_float_round feq.s a5,fa0,fa0 beqz a5,.L6 auipc a5,0x0 flw fa4,42(a5) fabs.s fa5,fa0 flt.s a5,fa5,fa4 beqz a5,.L5 fcvt.w.s a5,fa0,rmm fcvt.s.w fa5,a5 fsgnj.s fa0,fa5,fa0 ret .L6: fadd.s fa0,fa0,fa0 .L5: ret With -fno-trapping-math, the additional checks are omitted so the resulting code is unchanged. In addition this fixes the following failures: FAIL: gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times frflags\\s+[atx][0-9]+ 32 FAIL: gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times fsflags\\s+[atx][0-9]+ 32 Fixes: f652a35877e3 ("This is almost exclusively Jivan's work....") Fixes: f12a27216952 ("RISC-V: fix __builtin_round clobbering FP...") PR target/121652 gcc/ChangeLog: * config/riscv/riscv.md (round_pattern): special case NaN input instead of saving/restoring fflags. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c: Adjust scan pattern for fewer instances of frflags/fsrflags. (cherry picked from commit 60c6f92fb192352d784ab3153a9e11c19a3216a0)
2025-10-08Daily bump.GCC Administrator3-1/+18
2025-10-07AVR: target/122187 - Don't clobber recog_data.operand[] in insn out.Georg-Johann Lay2-8/+27
avr.cc::avr_out_extr() and avr.cc::avr_out_extr_not() changed xop for output, which spoiled the operand for the next invokation, running into an assertion. This patch makes a local copy of the operands. PR target/122187 gcc/ * config/avr/avr.cc (avr_out_extr, avr_out_extr_not): Make a local copy of the passed rtx[] operands. gcc/testsuite/ * gcc.target/avr/torture/pr122187.c: New test. (cherry picked from commit 3cbd43d640d6384df85c171a0245488f0adc3145)
generated by cgit v1.1 at 2026-01-07 02:41:14 +0000