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2022-12-10Daily bump.GCC Administrator3-1/+28
2022-12-09i386: fix assert (__builtin_cpu_supports ("x86-64") >= 0)Martin Liska3-26/+26
Similar story as PR103661, we again return a negative number for __builtin_cpu_supports: Documentation says: int __builtin_cpu_supports(const char *feature) This function returns a positive integer if the run-time CPU supports feature and returns 0 otherwise. while we return -2147483648. Moreover, I noticed "x86-64" is not a valid option for __builtin_cpu_is, but for __builtin_cpu_supports. PR target/107551 gcc/ChangeLog: * config/i386/i386-builtins.cc (fold_builtin_cpu): Use same path as for PR103661. * doc/extend.texi: Fix "x86-64" use. gcc/testsuite/ChangeLog: * gcc.target/i386/builtin_target.c: Add more checks. (cherry picked from commit d71b20fc30965ba8326ad9363d0aca9d61eb4ed3)
2022-12-09i386: simplify cpu_feature handlingMartin Liska2-62/+67
The patch removes unneeded loops for cpu_features2 and CONVERT_EXPR that can be simplified with NOP_EXPR. gcc/ChangeLog: * common/config/i386/cpuinfo.h (has_cpu_feature): Directly compute index in cpu_features2. (set_cpu_feature): Likewise. * config/i386/i386-builtins.cc (fold_builtin_cpu): Also remove loop for cpu_features2 and use NOP_EXPRs. (cherry picked from commit ef14bba0a6f3836d41d75863e6516d21aef0e936)
2022-12-09Merge branch 'releases/gcc-12' into devel/omp/gcc-12Tobias Burnus8-1/+97
Merge up to r12-8964-g58791f4db575ad9f952025c5eac4cc46e5c27019 (9th Dec 2022)
2022-12-09Daily bump.GCC Administrator1-1/+1
2022-12-08Daily bump.GCC Administrator1-1/+1
2022-12-07Daily bump.GCC Administrator3-1/+21
2022-12-06OpenMP: omp_get_max_teams, omp_set_num_teams, and ↵Marcel Vollweiler8-8/+30
omp_{gs}et_teams_thread_limit on offload devices This patch adds support for omp_get_max_teams, omp_set_num_teams, and omp_{gs}et_teams_thread_limit on offload devices. That includes the usage of device-specific ICV values (specified as environment variables or changed on a device). In order to reuse device-specific ICV values, a copy back mechanism is implemented that copies ICV values back from device to the host. Additionally, a limitation of the number of teams on gcn offload devices is implemented. The number of teams is limited by twice the number of compute units (one team is executed on one compute unit). This avoids queueing unnessecary many teams and a corresponding allocation of large amounts of memory. Without that limitation the memory allocation for a large number of user-specified teams can result in an "memory access fault". A limitation of the number of teams is already also implemented for nvptx devices (see nvptx_adjust_launch_bounds in libgomp/plugin/plugin-nvptx.c). gcc/ChangeLog: * gimplify.cc (optimize_target_teams): Set initial num_teams_upper to "-2" instead of "1" for non-existing num_teams clause in order to disambiguate from the case of an existing num_teams clause with value 1. libgomp/ChangeLog: * config/gcn/icv-device.c (omp_get_teams_thread_limit): Added to allow processing of device-specific values. (omp_set_teams_thread_limit): Likewise. (ialias): Likewise. * config/nvptx/icv-device.c (omp_get_teams_thread_limit): Likewise. (omp_set_teams_thread_limit): Likewise. (ialias): Likewise. * icv-device.c (omp_get_teams_thread_limit): Likewise. (ialias): Likewise. (omp_set_teams_thread_limit): Likewise. * icv.c (omp_set_teams_thread_limit): Removed. (omp_get_teams_thread_limit): Likewise. (ialias): Likewise. * libgomp.texi: Updated documentation for nvptx and gcn corresponding to the limitation of the number of teams. * plugin/plugin-gcn.c (limit_teams): New helper function that limits the number of teams by twice the number of compute units. (parse_target_attributes): Limit the number of teams on gcn offload devices. * target.c (get_gomp_offload_icvs): Added teams_thread_limit_var handling. (gomp_load_image_to_device): Added a size check for the ICVs struct variable. (gomp_copy_back_icvs): New function that is used in GOMP_target_ext to copy back the ICV values from device to host. (GOMP_target_ext): Update the number of teams and threads in the kernel args also considering device-specific values. * testsuite/libgomp.c-c++-common/icv-4.c: Fixed an error in the reading of OMP_TEAMS_THREAD_LIMIT from the environment. * testsuite/libgomp.c-c++-common/icv-5.c: Extended. * testsuite/libgomp.c-c++-common/icv-6.c: Extended. * testsuite/libgomp.c-c++-common/icv-7.c: Extended. * testsuite/libgomp.c-c++-common/icv-9.c: New test. * testsuite/libgomp.fortran/icv-5.f90: New test. * testsuite/libgomp.fortran/icv-6.f90: New test. gcc/testsuite/ChangeLog: * c-c++-common/gomp/target-teams-1.c: Adapt expected values for num_teams from "1" to "-2" in cases without num_teams clause. * g++.dg/gomp/target-teams-1.C: Likewise. * gfortran.dg/gomp/defaultmap-4.f90: Likewise. * gfortran.dg/gomp/defaultmap-5.f90: Likewise. * gfortran.dg/gomp/defaultmap-6.f90: Likewise. (cherry picked from commit 81476bc4f4a20bcf3af7ac2548c2322d48499402)
2022-12-06amdgcn: Add preprocessor builtins for every processor typePaul-Antoine Arras3-14/+45
Provide a specific builtin for each possible value of '-march'. gcc/ChangeLog: * config/gcn/gcn-opts.h (TARGET_FIJI): -march=fiji. (TARGET_VEGA10): -march=gfx900. (TARGET_VEGA20): -march=gfx906. (TARGET_GFX908): -march=gfx908. (TARGET_GFX90a): -march=gfx90a. * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Define a builtin that uniquely maps to '-march'. (cherry picked from commit e41b243302e9964e642924329826448afb21d28e)
2022-12-06aarch64: Specify that FEAT_MOPS sequences clobber CCKyrylo Tkachov4-0/+55
According to the architecture pseudocode the FEAT_MOPS sequences overwrite the NZCV flags as par of their operation, so GCC needs to model that in the relevant RTL patterns. For the testcase: void g(); void foo (int a, size_t N, char *__restrict__ in, char *__restrict__ out) { if (a != 3) __builtin_memcpy (out, in, N); if (a > 3) g (); } we will currently generate: foo: cmp w0, 3 bne .L6 .L1: ret .L6: cpyfp [x3]!, [x2]!, x1! cpyfm [x3]!, [x2]!, x1! cpyfe [x3]!, [x2]!, x1! ble .L1 // Flags reused after CPYF* sequence b g This is wrong as the result of cmp needs to be recalculated after the MOPS sequence. With this patch we'll insert a "cmp w0, 3" before the ble, similar to what clang does. Bootstrapped and tested on aarch64-none-linux-gnu. Pushing to trunk and to the GCC 12 branch after some baking time. gcc/ChangeLog: * config/aarch64/aarch64.md (aarch64_cpymemdi): Specify clobber of CC reg. (*aarch64_cpymemdi): Likewise. (aarch64_movmemdi): Likewise. (aarch64_setmemdi): Likewise. (*aarch64_setmemdi): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/mops_5.c: New test. * gcc.target/aarch64/mops_6.c: Likewise. * gcc.target/aarch64/mops_7.c: Likewise. (cherry picked from commit cbdffae5745327b0e5eb887afc512daf34b049b1)
2022-12-06Daily bump.GCC Administrator2-1/+10
2022-12-05tree-optimization/107956 - ICE with NULL call LHSAndrew Pinski1-0/+2
The following adds a missing check for a NULL call LHS in the vector pattern recognizer. PR tree-optimization/107956 * tree-vect-patterns.cc (vect_recog_mask_conversion_pattern): Check for NULL LHS on masked loads. (cherry picked from commit 5c11d748564c7ce3b096e87ad350fcddd493e45e)
2022-12-05Daily bump.GCC Administrator1-1/+1
2022-12-04Daily bump.GCC Administrator1-1/+1
2022-12-03Daily bump.GCC Administrator1-1/+1
2022-12-02Daily bump.GCC Administrator3-1/+11
2022-12-01Merge branch 'releases/gcc-12' into devel/omp/gcc-12Tobias Burnus61-129/+495
Merge up to r12-8954-gb7306f02da33695bec90f153f6725a51d7c0ac71 (1st Dec 2022)
2022-12-01Fix unrecognizable insn due to illegal immediate_operand (const_int 255) of ↵liuhongt2-1/+9
QImode. For __builtin_ia32_vec_set_v16qi (a, -1, 2) with !flag_signed_char. it's transformed to __builtin_ia32_vec_set_v16qi (_4, 255, 2) in the gimple, and expanded to (const_int 255) in the rtl. But for immediate_operand, it expects (const_int 255) to be signed extended to (const_int -1). The mismatch caused an unrecognizable insn error. The patch converts (const_int 255) to (const_int -1) in the backend expander. gcc/ChangeLog: PR target/107863 * config/i386/i386-expand.cc (ix86_expand_vec_set_builtin): Convert op1 to target mode whenever mode mismatch. gcc/testsuite/ChangeLog: * gcc.target/i386/pr107863.c: New test.
2022-12-01Daily bump.GCC Administrator4-1/+124
2022-11-30d: Include tm.h in all D target platform sources, remove memmodel.hIain Buclaw7-2/+5
The tm.h header would pull in config/elfos.h, which defines TARGET_D_MINFO_SECTION needed for the D module support in the front-end to emit data to the correct section for the run-time library to pick up. The removal of it in r13-2385 caused a stage2 bootstrap failure on all Solaris targets. The memmodel header has also been removed as it is no longer required now tm_p.h is no longer used by these sources. gcc/ChangeLog: * config/darwin-d.cc: Include tm.h. * config/dragonfly-d.cc: Likewise. * config/freebsd-d.cc: Remove memmodel.h. * config/glibc-d.cc: Likewise. * config/netbsd-d.cc: Include tm.h. * config/openbsd-d.cc: Likewise. * config/sol2-d.cc: Likewise. (cherry picked from commit a7852bd30a19d29ff7986869453786d460d17877)
2022-11-30d: Fix ICE on named continue label in an unrolled loop [PR107592]Iain Buclaw2-2/+37
Continue labels in an unrolled loop require a unique label per iteration. Previously this used the Statement body node for each unrolled iteration to generate a new entry in the label hash table. This does not work when the continue label has an identifier, as said named label is pointing to the outer UnrolledLoopStatement node. What would happen is that during the lowering of `continue label', an automatic label associated with the unrolled loop would be generated, and a jump to that label inserted, but because it was never pushed by the visitor for the loop itself, it subsequently never gets emitted. To fix, correctly use the UnrolledLoopStatement as the key to look up and store the break/continue label pair, but remove the continue label from the value entry after every loop to force a new label to be generated by the next call to `push_continue_label' PR d/107592 gcc/d/ChangeLog: * toir.cc (IRVisitor::push_unrolled_continue_label): New method. (IRVisitor::pop_unrolled_continue_label): New method. (IRVisitor::visit (UnrolledLoopStatement *)): Use them instead of push_continue_label and pop_continue_label. gcc/testsuite/ChangeLog: * gdc.dg/pr107592.d: New test. (cherry picked from commit 031d3f095520f0e1ee03e29b7ad5067c2a3f96e0)
2022-11-30d: Fix #error You must define PREFERRED_DEBUGGING_TYPE if DWARF is not supportedIain Buclaw46-106/+247
This moves all D front-end specific target definitions out of the main target headers, and into its own header that is included by tm_d.h instead of pulling in the same headers as tm_p.h. This fixes the build on target configurations that pull in the default D language target hooks, and subsequently trigger an error because the definition of PREFERRED_DEBUGGING_TYPE is behind tm.h, the one header that is avoided from being included in default-d.cc. PR d/105659 gcc/ChangeLog: * config.gcc: Set tm_d_file to ${cpu_type}/${cpu_type}-d.h. * config/aarch64/aarch64-d.cc: Include tm_d.h. * config/aarch64/aarch64-protos.h (aarch64_d_target_versions): Move to config/aarch64/aarch64-d.h. (aarch64_d_register_target_info): Likewise. * config/aarch64/aarch64.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. * config/arm/arm-d.cc: Include tm_d.h and arm-protos.h instead of tm_p.h. * config/arm/arm-protos.h (arm_d_target_versions): Move to config/arm/arm-d.h. (arm_d_register_target_info): Likewise. * config/arm/arm.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. * config/default-d.cc: Remove memmodel.h include. * config/freebsd-d.cc: Include tm_d.h instead of tm_p.h. * config/glibc-d.cc: Likewise. * config/i386/i386-d.cc: Include tm_d.h. * config/i386/i386-protos.h (ix86_d_target_versions): Move to config/i386/i386-d.h. (ix86_d_register_target_info): Likewise. (ix86_d_has_stdcall_convention): Likewise. * config/i386/i386.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. (TARGET_D_HAS_STDCALL_CONVENTION): Likewise. * config/i386/winnt-d.cc: Include tm_d.h instead of tm_p.h. * config/mips/mips-d.cc: Include tm_d.h. * config/mips/mips-protos.h (mips_d_target_versions): Move to config/mips/mips-d.h. (mips_d_register_target_info): Likewise. * config/mips/mips.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. * config/netbsd-d.cc: Include tm_d.h instead of tm.h and memmodel.h. * config/openbsd-d.cc: Likewise. * config/pa/pa-d.cc: Include tm_d.h. * config/pa/pa-protos.h (pa_d_target_versions): Move to config/pa/pa-d.h. (pa_d_register_target_info): Likewise. * config/pa/pa.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. * config/riscv/riscv-d.cc: Include tm_d.h. * config/riscv/riscv-protos.h (riscv_d_target_versions): Move to config/riscv/riscv-d.h. (riscv_d_register_target_info): Likewise. * config/riscv/riscv.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. * config/rs6000/rs6000-d.cc: Include tm_d.h. * config/rs6000/rs6000-protos.h (rs6000_d_target_versions): Move to config/rs6000/rs6000-d.h. (rs6000_d_register_target_info): Likewise. * config/rs6000/rs6000.h (TARGET_D_CPU_VERSIONS) Likewise.: (TARGET_D_REGISTER_CPU_TARGET_INFO) Likewise.: * config/s390/s390-d.cc: Include tm_d.h. * config/s390/s390-protos.h (s390_d_target_versions): Move to config/s390/s390-d.h. (s390_d_register_target_info): Likewise. * config/s390/s390.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. * config/sol2-d.cc: Include tm_d.h instead of tm.h and memmodel.h. * config/sparc/sparc-d.cc: Include tm_d.h. * config/sparc/sparc-protos.h (sparc_d_target_versions): Move to config/sparc/sparc-d.h. (sparc_d_register_target_info): Likewise. * config/sparc/sparc.h (TARGET_D_CPU_VERSIONS): Likewise. (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. * configure: Regenerate. * configure.ac (tm_d_file): Remove defaults.h. (tm_d_include_list): Remove options.h and insn-constants.h. * config/aarch64/aarch64-d.h: New file. * config/arm/arm-d.h: New file. * config/i386/i386-d.h: New file. * config/mips/mips-d.h: New file. * config/pa/pa-d.h: New file. * config/riscv/riscv-d.h: New file. * config/rs6000/rs6000-d.h: New file. * config/s390/s390-d.h: New file. * config/sparc/sparc-d.h: New file. (cherry picked from commit d5ad6f8415171798adaff5787400505ce9882144)
2022-11-30Fix addvdi3 and subvdi3 patternsJohn David Anglin1-18/+22
While most PA 2.0 instructions support both 32 and 64-bit traps and conditions, the addi and subi instructions only support 32-bit traps and conditions. Thus, we need to force immediate operands to register operands on the 64-bit target and use the add/sub instructions which can trap on 64-bit signed overflow. 2022-11-30 John David Anglin <danglin@gcc.gnu.org> gcc/ChangeLog: * config/pa/pa.md (addvdi3): Force operand 2 to a register. Remove "addi,tsv,*" instruction from unamed pattern. (subvdi3): Force operand 1 to a register. Remove "subi,tsv" instruction from from unamed pattern.
2022-11-30amdgcn: Support AMD-specific 'isa' traits in OpenMP context selectorsPaul-Antoine Arras3-2/+10
Add support for gfx803 as an alias for fiji. Add test cases for all supported 'isa' values. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_omp_device_kind_arch_isa): Add gfx803. * config/gcn/t-omp-device: Add gfx803. libgomp/ChangeLog: * testsuite/libgomp.c/declare-variant-4-fiji.c: New test. * testsuite/libgomp.c/declare-variant-4-gfx803.c: New test. * testsuite/libgomp.c/declare-variant-4-gfx900.c: New test. * testsuite/libgomp.c/declare-variant-4-gfx906.c: New test. * testsuite/libgomp.c/declare-variant-4-gfx908.c: New test. * testsuite/libgomp.c/declare-variant-4-gfx90a.c: New test. * testsuite/libgomp.c/declare-variant-4.h: New header file. (cherry picked from commit 1fd508744eccda9ad9c6d6fcce5b2ea9c568818d)
2022-11-30Daily bump.GCC Administrator2-1/+10
2022-11-28gcc: fix PR rtl-optimization/107482Max Filippov1-2/+2
gcc/ PR rtl-optimization/107482 * ira-color.cc (assign_hard_reg): Only call update_costs_from_copies when retry_p is false. (cherry picked from commit e581490f0cfa80c58d2b648d71a44a597fbe3008)
2022-11-29Daily bump.GCC Administrator1-1/+1
2022-11-28gcn: Fix __builtin_gcn_first_call_this_thread_pTobias Burnus3-21/+17
Contrary naive expectation, unspec_volatile (via prologue_use) did not prevent the cprop pass (at -O2) to remove the access to the s[0:1] (PRIVATE_SEGMENT_BUFFER_ARG) register as the volatile got just put on the preceeding pseudoregister. Solution: Use gen_rtx_USE instead. Additionally, this patch removes (gen_)prologue_use_di as it is then no longer used. Finally, as we already do bit manipulation, instead of using the full 64bit side - and then just keeping the value of 's0', just move directly to use only s1 of s[0:1] and do the bit manipulations there, generating more readable assembly code and better matching the '#else' branch. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_expand_builtin_1): Work on s1 instead of s[0:1] and use USE to prevent removal of setting that register. * config/gcn/gcn.md (prologue_use_di): Remove. (cherry picked from commit 9fa67f1c1228a852e23943a41e68b664172c654c)
2022-11-28OpenMP/Fortran: Permit end-clause on directiveTobias Burnus12-193/+892
gcc/fortran/ChangeLog: * openmp.cc (OMP_DO_CLAUSES, OMP_SCOPE_CLAUSES, OMP_SECTIONS_CLAUSES): Add 'nowait'. (OMP_SINGLE_CLAUSES): Add 'nowait' and 'copyprivate'. (gfc_match_omp_distribute_parallel_do, gfc_match_omp_distribute_parallel_do_simd, gfc_match_omp_parallel_do, gfc_match_omp_parallel_do_simd, gfc_match_omp_parallel_sections, gfc_match_omp_teams_distribute_parallel_do, gfc_match_omp_teams_distribute_parallel_do_simd): Disallow 'nowait'. (gfc_match_omp_workshare): Match 'nowait' clause. (gfc_match_omp_end_single): Use clause matcher for 'nowait'. (resolve_omp_clauses): Reject 'nowait' + 'copyprivate'. * parse.cc (decode_omp_directive): Break too long line. (parse_omp_do, parse_omp_structured_block): Diagnose duplicated 'nowait' clause. libgomp/ChangeLog: * libgomp.texi (OpenMP 5.2): Mark end-directive as Y. gcc/testsuite/ChangeLog: * gfortran.dg/gomp/copyprivate-1.f90: New test. * gfortran.dg/gomp/copyprivate-2.f90: New test. * gfortran.dg/gomp/nowait-2.f90: Move dg-error tests ... * gfortran.dg/gomp/nowait-4.f90: ... to this new file. * gfortran.dg/gomp/nowait-5.f90: New test. * gfortran.dg/gomp/nowait-6.f90: New test. * gfortran.dg/gomp/nowait-7.f90: New test. * gfortran.dg/gomp/nowait-8.f90: New test. (cherry picked from commit 091b6dbc48177fa3ef15d62ea280ef6cb61c05b2)
2022-11-28Daily bump.GCC Administrator1-1/+1
2022-11-27Daily bump.GCC Administrator1-1/+1
2022-11-26OpenMP: Generate SIMD clones for functions with "declare target"Sandra Loosemore23-52/+810
This patch causes the IPA simdclone pass to generate clones for functions with the "omp declare target" attribute as if they had "omp declare simd", provided the function appears to be suitable for SIMD execution. The filter is conservative, rejecting functions that write memory or that call other functions not known to be safe. A new option -fopenmp-target-simd-clone is added to control this transformation; it's enabled for offload processing at -O2 and higher. Backport of mainline commit 309e2d95e3b930c6f15c8a5346b913158404c76d. gcc/ChangeLog: * common.opt (fopenmp-target-simd-clone): New option. (target_simd_clone_device): New enum to go with it. * doc/invoke.texi (-fopenmp-target-simd-clone): Document. * flag-types.h (enum omp_target_simd_clone_device_kind): New. * omp-simd-clone.cc (auto_simd_fail): New function. (auto_simd_check_stmt): New function. (plausible_type_for_simd_clone): New function. (ok_for_auto_simd_clone): New function. (simd_clone_create): Add force_local argument, make the symbol have internal linkage if it is true. (expand_simd_clones): Also check for cloneable functions with "omp declare target". Pass explicit_p argument to simd_clone.compute_vecsize_and_simdlen target hook. * opts.cc (default_options_table): Add -fopenmp-target-simd-clone. * target.def (TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN): Add bool explicit_p argument. * doc/tm.texi: Regenerated. * config/aarch64/aarch64.cc (aarch64_simd_clone_compute_vecsize_and_simdlen): Update. * config/gcn/gcn.cc (gcn_simd_clone_compute_vecsize_and_simdlen): Update. * config/i386/i386.cc (ix86_simd_clone_compute_vecsize_and_simdlen): Update. gcc/testsuite/ChangeLog: * g++.dg/gomp/target-simd-clone-1.C: New. * g++.dg/gomp/target-simd-clone-2.C: New. * gcc.dg/gomp/target-simd-clone-1.c: New. * gcc.dg/gomp/target-simd-clone-2.c: New. * gcc.dg/gomp/target-simd-clone-3.c: New. * gcc.dg/gomp/target-simd-clone-4.c: New. * gcc.dg/gomp/target-simd-clone-5.c: New. * gcc.dg/gomp/target-simd-clone-6.c: New. * gcc.dg/gomp/target-simd-clone-7.c: New. * gcc.dg/gomp/target-simd-clone-8.c: New. * lib/scanoffloadipa.exp: New. libgomp/ChangeLog: * testsuite/lib/libgomp.exp: Load scanoffloadipa.exp library. * testsuite/libgomp.c/target-simd-clone-1.c: New. * testsuite/libgomp.c/target-simd-clone-2.c: New. * testsuite/libgomp.c/target-simd-clone-3.c: New.
2022-11-26Revert "OpenMP: Generate SIMD clones for functions with "declare target""Sandra Loosemore15-362/+52
This reverts commit f01e3b9dfd81973498c0a71a266e530aeb6f0c97.
2022-11-26Daily bump.GCC Administrator3-1/+18
2022-11-25Fortran: reject NULL actual argument without explicit interface [PR107576]Harald Anlauf2-0/+26
gcc/fortran/ChangeLog: PR fortran/107576 * interface.cc (gfc_procedure_use): Reject NULL as actual argument when there is no explicit procedure interface. gcc/testsuite/ChangeLog: PR fortran/107576 * gfortran.dg/null_actual_3.f90: New test. (cherry picked from commit 820c25c83561085f54268bd536f9d216d03c3e18)
2022-11-25Merge branch 'releases/gcc-12' into devel/omp/gcc-12Tobias Burnus9-2/+117
Merge up to r12-8941-ged8d7ecac11d587687986a0895050955c09d2f43 (25th Nov 2022)
2022-11-25Daily bump.GCC Administrator3-1/+19
2022-11-25Fix thinko in operator_bitwise_xor::op1_rangeEric Botcazou4-0/+56
There is a thinko in the op1_range method of ranger's operator_bitwise_xor class in a boolean context: if the result is known to be true, it may infer that a specific operand is false without any basis. gcc/ * range-op.cc (operator_bitwise_xor::op1_range): Fix thinko. gcc/testsuite/ * gnat.dg/opt100.adb: New test. * gnat.dg/opt100_pkg.adb, gnat.dg/opt100_pkg.ads: New helper.
2022-11-25Fix wrong array type conversion with different storage ordeEric Botcazou2-1/+27
When two arrays of scalars have a different storage order in Ada, the front-end makes sure that the conversion is performed component-wise so that each component can be reversed. So it's a little bit counter productive that the ldist pass performs the opposite transformation and synthesizes a memcpy/memmove in this case. gcc/ * tree-loop-distribution.cc (loop_distribution::classify_builtin_ldst): Bail out if source and destination do not have the same storage order. gcc/testsuite/ * gnat.dg/sso18.adb: New test.
2022-11-24Daily bump.GCC Administrator1-1/+1
2022-11-23gcn: Add __builtin_gcn_{get_stack_limit,first_call_this_thread_p}Tobias Burnus4-2/+100
The new builtins have been added for newlib to reduce dependency on compiler-internal implementation choices of GCC in newlibs' getreent.c. gcc/ChangeLog: * config/gcn/gcn-builtins.def (FIRST_CALL_THIS_THREAD_P, GET_STACK_LIMIT): Add new builtins. * config/gcn/gcn.cc (gcn_expand_builtin_1): Expand them. * config/gcn/gcn.md (prologue_use): Add "register_operand" as arg to match_operand. (prologue_use_di): New; DI insn_and_split variant of the former. Co-Authored-By: Andrew Stubbs <ams@codesourcery.com> (cherry picked from commit d6bbca7b78745915d98bb1324d79de6a1e6dc801)
2022-11-23Daily bump.GCC Administrator1-1/+1
2022-11-22Daily bump.GCC Administrator2-1/+16
2022-11-21Merge branch 'releases/gcc-12' into devel/omp/gcc-12Tobias Burnus17-77/+299
Merge up to r12-8924-ga6b1f6126de5e45777610699b6d634605c17711c (21st Nov 2022)
2022-11-21i386: Uglify some local identifiers in *intrin.h [PR107748]Jakub Jelinek4-48/+49
While reporting PR107748 (where is a problem with non-uglified names, but I've left it out because it needs fixing anyway), I've noticed various spots where identifiers in *intrin.h headers weren't uglified. The following patch fixed those that are related to unions (I've grepped for [a-zA-Z]\.[a-zA-Z] spots). The reason we need those to be uglified is the same as why the arguments of the inlines are __ prefixed and most of automatic vars in the inlines - say a, v or u aren't part of implementation namespace and so users could #define u whatever->something #include <x86intrin.h> and it should still work, as long as u is not e.g. one of the names of the functions/macros the header provides (_mm* etc.). 2022-11-21 Jakub Jelinek <jakub@redhat.com> PR target/107748 * config/i386/avx512fp16intrin.h (_mm512_castph512_ph128, _mm512_castph512_ph256, _mm512_castph128_ph512, _mm512_castph256_ph512, _mm512_set1_pch): Uglify names of local variables and union members. * config/i386/avx512fp16vlintrin.h (_mm256_castph256_ph128, _mm256_castph128_ph256, _mm256_set1_pch, _mm_set1_pch): Likewise. * config/i386/smmintrin.h (_mm_extract_ps): Likewise. * config/i386/avx512bf16intrin.h (_mm_cvtsbh_ss): Likewise. (cherry picked from commit ec8ec09f9414be871e322fecf4ebf53e3687bd22)
2022-11-21Daily bump.GCC Administrator4-1/+67
2022-11-20reg-stack: Fix a -fcompare-debug bug in reg-stack [PR107183]Jakub Jelinek2-21/+77
As the following testcase shows, the swap_rtx_condition function in reg-stack can result in different code generation between -g and -g0. The function is doing the changes as it goes, so does analysis and changes together, which makes it harder to deal with DEBUG_INSNs, where normally analysis phase ignores them and the later phase doesn't. swap_rtx_condition walks instructions two different ways, one is using next_flags_user function which stops on non-call instructions that mention the flags register, and the other is a loop on fnstsw where it stops on instructions mentioning it and tries to find sahf instruction that uses it (in both cases calls stop it and so does end of basic block). Now both of these currently stop on DEBUG_INSNs that mention the flags register resp. the fnstsw result register. On success the function recurses on next flags user instruction if still live and if the recursion failed, reverts the changes it did too and fails. If it were just for the next_flags_user case, the fix could be just not doing INSN_CODE (insn) = -1; if (recog_memoized (insn) == -1) fail = 1; on DEBUG_INSNs (assuming all changes to those are fine), swap_rtx_condition_1 just changes one comparison to a different one. But due to the possibility of fnstsw result being used in theory before sahf in some DEBUG_INSNs, this patch takes a different approach. swap_rtx_condition has now a new argument and two modes. The first mode is when debug_seen is >= 0, in this case both next_flags_user and the loop for fnstsw -> sahf will ignore but note DEBUG_INSNs (that mention flags register or fnstsw result). If no such DEBUG_INSN is found during the whole call including recursive invocations (so e.g. for -g0 but probably most often for -g as well), it behaves as before, if it returns true all the changes are done and nothing further needs to be done later. If any DEBUG_INSNs are seen along the way, even when returning success all the changes are reverted, so it just reports that the function would be successful if DEBUG_INSNs were ignored. In this case, compare_for_stack_reg needs to call it again in debug_seen = -1 mode, which tells the function to update everything including DEBUG_INSNs. For the fnstsw -> sahf case which I hope will be very rare I just reset the DEBUG_INSNs, I don't really know how to express it easily otherwise. For the rest swap_rtx_condition_1 is done even on the DEBUG_INSNs. 2022-11-20 Jakub Jelinek <jakub@redhat.com> PR target/107183 * reg-stack.cc (next_flags_user): Add DEBUG_SEEN argument. If >= 0 and a DEBUG_INSN would be otherwise returned, set DEBUG_SEEN to 1 and ignore it. (swap_rtx_condition): Add DEBUG_SEEN argument. In >= 0 mode only set DEBUG_SEEN to 1 if problematic DEBUG_ISNSs were seen and revert all changes on success in that case. Don't try to recog_memoized DEBUG_INSNs. (compare_for_stack_reg): Adjust swap_rtx_condition caller. If it returns true and debug_seen is 1, call swap_rtx_condition again with debug_seen -1. * gcc.dg/ubsan/pr107183.c: New test. (cherry picked from commit 6b5c98c1c0003bd470a4428bede6c862637a94b8)
2022-11-20c++: Fix a typo in function nameJakub Jelinek3-4/+4
I've noticed I've made a typo in the name of the function. Fixed thusly. 2022-11-15 Jakub Jelinek <jakub@redhat.com> * cp-tree.h (next_common_initial_seqence): Rename to ... (next_common_initial_sequence): ... this. * typeck.cc (next_common_initial_seqence): Rename to ... (next_common_initial_sequence): ... this. (layout_compatible_type_p): Call next_common_initial_sequence rather than next_common_initial_seqence. * semantics.cc (is_corresponding_member_aggr): Likewise. (cherry picked from commit 87c4057b3fc7fe2c2f8914d2755024ca890a3bc1)
2022-11-19nvptx: In 'STARTFILE_SPEC', fix 'crt0.o' for '-mmainkernel'Thomas Schwinge1-1/+1
A recent nvptx-tools change: commit 886a95faf66bf66a82fc0fe7d2a9fd9e9fec2820 "ld: Don't search for input files in '-L'directories" (of <https://github.com/MentorEmbedded/nvptx-tools/pull/38> "Match standard 'ld' "search" behavior") in GCC/nvptx target testing generally causes linking to fail with: error opening crt0.o collect2: error: ld returned 1 exit status compiler exited with status 1 Indeed per GCC '-v' output, there is an undecorated 'crt0.o' on the linker ('collect2') command line: [...]/build-gcc/./gcc/collect2 -o [...] crt0.o [...] This is due to: gcc/config/nvptx/nvptx.h:#define STARTFILE_SPEC "%{mmainkernel:crt0.o}" ..., and the fix, as used by numerous other GCC targets, is to instead use 'crt0.o%s'; for '%s' means, per 'gcc/gcc.cc', "The Specs Language": %s current argument is the name of a library or startup file of some sort. Search for that file in a standard list of directories and substitute the full name found. With that, we get the expected path to 'crt0.o'. gcc/ * config/nvptx/nvptx.h (STARTFILE_SPEC): Fix 'crt0.o' for '-mmainkernel'. (cherry picked from commit dda43e1ef0c9f6c32ad022d3a08ce7651e42a129)
2022-11-19LoongArch: Fix atomic_exchange expanding [PR107713]Jinyang He3-2/+84
We used to expand atomic_exchange_n(ptr, new, mem_order) for subword types into something like: { __typeof__(*ptr) t = atomic_load_n(ptr, mem_order); atomic_compare_exchange_n(ptr, &t, new, true, mem_order, mem_order); return t; } It's incorrect because another thread may store a different value into *ptr after atomic_load_n. Then atomic_compare_exchange_n will not store into *ptr, but atomic_exchange_n should always perform the store. gcc/ChangeLog: PR target/107713 * config/loongarch/sync.md (atomic_cas_value_exchange_7_<mode>): New define_insn. (atomic_exchange): Use atomic_cas_value_exchange_7_si instead of atomic_cas_value_cmp_and_7_si. gcc/testsuite/ChangeLog: PR target/107713 * gcc.target/loongarch/pr107713-1.c: New test. * gcc.target/loongarch/pr107713-2.c: New test. (cherry picked from commit f0024bfb228f94e60e06dc32a4983e40a9b90be5)
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