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Addresses #2883.
contrib/
* gcc_update (files_and_dependencies): Update for
'libformat_parser' in libgrust.
gcc/rust/
* Make-lang.in (LIBFORMAT_PARSER): Point to 'libformat_parser'
build in libgrust.
(%.toml:, $(LIBFORMAT_PARSER):): Remove.
libgrust/
* libformat_parser/Makefile.am: New.
* Makefile.am [!TARGET_LIBRARY] (SUBDIRS): Add 'libformat_parser'.
* configure.ac: Handle it.
(TARGET_LIBRARY): New 'AM_CONDITIONAL'.
* libformat_parser/Makefile.in: Generate.
* Makefile.in: Regenerate.
* configure: Likewise.
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Fixes #2883.
gcc/rust/ChangeLog:
* Make-lang.in (LIBFORMAT_PARSER): Point to the GCC build
directory.
* ($(LIBFORMAT_PARSER)): Build in the GCC build directory.
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gcc/rust/
* Make-lang.in (LIBFORMAT_PARSER): Point to the actual build artifact.
($(LIBFORMAT_PARSER)): Don't cache it.
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... to avoid verbatim repetition.
gcc/rust/
* Make-lang.in (LIBPROC_MACRO_INTERNAL): New.
(RUST_LIBDEPS, crab1$(exeext), rust/libformat_parser.a): Use it.
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Compile libformat_parser and link to it.
gcc/rust/ChangeLog:
* Make-lang.in: Compile libformat_parser.
* ast/rust-fmt.cc: New FFI definitions.
* ast/rust-fmt.h: Likewise.
* expand/rust-macro-builtins.cc (MacroBuiltin::format_args_handler): Call
into libformat_parser.
* expand/rust-macro-builtins.h: Define format_args!() handler proper.
libgrust/ChangeLog:
* libformat_parser/Cargo.lock: New file.
* libformat_parser/Cargo.toml: New file.
* libformat_parser/generic_format_parser/Cargo.toml: New file.
* libformat_parser/generic_format_parser/src/lib.rs: New file.
* libformat_parser/src/bin.rs: New file.
* libformat_parser/src/lib.rs: New file.
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This commit adds a base class for parsing the various constructs of a
Rust format string, according to the grammar in the reference:
https://doc.rust-lang.org/std/fmt/index.html#syntax
gcc/rust/ChangeLog:
* Make-lang.in: Compile rust-fmt object
* ast/rust-fmt.cc: New file.
* ast/rust-fmt.h: New file.
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gcc/rust/ChangeLog:
* rust-lang.cc (grs_langhook_type_for_mode): simplify code for
xImode. Add missing long_double_type_node.
Signed-off-by: Marc Poulhiès <dkm@kataplop.net>
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gcc/rust/ChangeLog:
* hir/rust-ast-lower-pattern.cc
(ASTLoweringPattern::visit):
Reset is_let_top_level while visiting GroupedPattern.
gcc/testsuite/ChangeLog:
* rust/compile/let_alt.rs: Check for false positive.
Signed-off-by: Owen Avery <powerboat9.gamer@gmail.com>
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'gcc/tree.h':
#define main_identifier_node global_trees[TI_MAIN_IDENTIFIER]
#define MAIN_NAME_P(NODE) \
(IDENTIFIER_NODE_CHECK (NODE) == main_identifier_node)
..., which is not initialized by default, but has to be set up by every front
end individually. 'MAIN_NAME_P' enables certain code optimizations, but is
especially also relevant for back ends that emit additional program entry setup
code for 'main'.
gcc/rust/
* backend/rust-compile-base.cc (HIRCompileBase::compile_function):
For 'main', initialize 'main_identifier_node'.
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The following addresses another case where x87 FP loads mangle the
bit representation and thus are not suitable for a representative
in other types. VN was value-numbering a later integer load of 'x'
as the same as a former float load of 'x'.
We can use the new TARGET_MODE_CAN_TRANSFER_BITS hook to identify
problematic modes and enforce strict compatibility for those in
the reference comparison, improving the handling of modes with
padding in visit_reference_op_load.
PR tree-optimization/114659
* tree-ssa-sccvn.cc (visit_reference_op_load): Do not
prevent punning from modes with padding here, but ...
(vn_reference_eq): ... ensure this here, also honoring
types with modes that cannot act as bit container.
* gcc.target/i386/pr114659.c: New testcase.
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The following implements the hook, excluding x87 modes for scalar
and complex float modes.
* config/i386/i386.cc (TARGET_MODE_CAN_TRANSFER_BITS): Define.
(ix86_mode_can_transfer_bits): New function.
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The following adds a target hook to specify whether regs of MODE can be
used to transfer bits. The hook is supposed to be used for value-numbering
to decide whether a value loaded in such mode can be punned to another
mode instead of re-loading the value in the other mode and for SRA to
decide whether MODE is suitable as container holding a value to be
used in different modes.
* target.def (mode_can_transfer_bits): New target hook.
* target.h (mode_can_transfer_bits): New function wrapping the
hook and providing default behavior.
* doc/tm.texi.in: Update.
* doc/tm.texi: Re-generate.
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u16 >= 256 can be performed by testing the hi8 part against 0.
u32 >= 65536 can be performed by testing the high word against 0.
The optimization is performed in split2 after register allocation
because the register allocator likely spills for subregs.
gcc/
* config/avr/avr.md (cbranch<mode>4_insn): Split to a test of the
high part against 0 if possible.
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When comparing a 16-bit or 32-bit integer against a constant in
the range 0...0xff, constraint M is used because no scratch reg
is needed in that case. Same can be done for fixed-point compares.
gcc/
* config/avr/constraints.md (YMM): New constraint.
* config/avr/avr.md (cmp<mode>3, *cmp<mode>3)
(cbranch<mode>4_insn): Allow YMM where M is allowed.
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The r14-537 change started canonicalizing VEC_MERGE operands based on
swap_commutative_operands_p or if they have the same precedence least
significant bit of the third operand.
The *<extract_type>_vinsert<shuffletype><extract_suf>_0 pattern was
added for combine matching and no longer triggers after that change,
as it used the reg_or_0_operand as the first operand and VEC_DUPLICATE
as the second.
Now, reg_or_0_operand could be a REG, SUBREG of object or CONST_VECTOR.
REG has commutative_operand_precedence -1 or -2, SUBREG of object -3,
CONST_VECTOR -4, while VEC_DUPLICATE has 0, so VEC_DUPLICATE will always
go first and REG, SUBREG or CONST_VECTOR second.
This patch swaps the operands so that it matches again.
2024-08-01 Jakub Jelinek <jakub@redhat.com>
PR target/115981
* config/i386/sse.md
(*<extract_type>_vinsert<shuffletype><extract_suf>_0): Swap the
first two VEC_MERGE operands, renumber match_operands and test
for 0xF or 0x3 rather than 0xFFF0 or 0xFC immediate.
* gcc.target/i386/avx512dq-pr90991-1.c: Add tests for no separate
zero extension instructions.
* gcc.target/i386/avx512dq-pr90991-2.c: Likewise.
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As the PR and included testcase shows, replacing 'arr2' by its value expression
'*arr2$13$linkptr' failed for
MEM <uint128_t> [(c_char * {ref-all})&arr2]
which left 'arr2' in the code as unknown symbol. Now expand the value expression
already in pass_omp_target_link::execute's process_link_var_op walk_gimple_stmt
walk - and don't rely on gimple_regimplify_operands.
PR middle-end/115637
gcc/ChangeLog:
* gimplify.cc (gimplify_body): Fix macro name in the comment.
* omp-offload.cc (find_link_var_op): Rename to ...
(process_link_var_op): ... this. Replace value expr.
(pass_omp_target_link::execute): Update walk_gimple_stmt call.
libgomp/ChangeLog:
* testsuite/libgomp.fortran/declare-target-link.f90: Uncomment
now working code.
Co-authored-by: Richard Biener <rguenther@suse.de
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*add<mode>_4 and *adddi_4 are for shorter opcode from cmp to
inc/dec or add $128. But NDD code is longer than the cmp code,
so there is no need to support ndd.
gcc/ChangeLog:
PR target/113744
* config/i386/i386.md (*add<mode>_4): Remove ndd support.
(*adddi_4): Ditto.
Co-Authored-By: Hu, Lin1 <lin1.hu@intel.com>
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gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr105314-rtl.c: Skip zicond.
* gcc.target/riscv/pr105314-rtl32.c: Ditto.
* gcc.target/riscv/pr105314.c: Ditto.
Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
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Empty structs result in empty LF_FIELDLIST types, which are valid, but
we weren't accounting for this and assuming they had to contain
subtypes.
gcc/
* dwarf2codeview.cc (get_type_num_struct): Fix NULL pointer dereference.
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I want to reuse some of the support for valgrind in jit.exp
in my upcoming testsuite for https://gcc.gnu.org/wiki/libdiagnostics
so this patch splits that out into a valgrind.exp.
No functional change intended.
gcc/testsuite/ChangeLog:
* jit.dg/jit.exp: Add load_lib valgrind.exp.
(proc report_leak): Move to valgrind.exp, and add argument
leak_report_function rather than hardcoding xfail.
(parse_valgrind_logfile): Likewise.
(fixed_host_execute): Pass xfail to parse_valgrind_logfile.
* lib/valgrind.exp: New file, based on the above.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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gcc/ChangeLog:
* diagnostic-path.cc
(thread_event_printer::print_swimlane_for_event_range): Gracefully
handle logical_location::get_name_for_path_output returning null.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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No functional change intended.
gcc/testsuite/ChangeLog:
* gcc.dg/sarif-output/sarif.py: Drop unused import of gzip.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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This patch extends
* the work done in r15-2291-gd7a688fc960f78 to capture labels
on location ranges in rich_locations in SARIF form as
"annotations" (§3.28.6)
* the work done in r15-2354-g4d1f71d49e396c to support
related locations (§3.27.22 and §3.34)
so that all location ranges in a rich_location now get captured in
the SARIF output:
- those with a label are handled as before as "annotations" (§3.28.6),
per r15-2291-gd7a688fc960f78
- those without a label now get captured, in the result's
"relatedLocations" (§3.27.22)
For example, given:
int missing_semicolon (void)
{
return 42
}
for which the textual output looks like this:
PATH/missing-semicolon.c: In function 'missing_semicolon':
PATH/missing-semicolon.c:9:12: error: expected ';' before '}' token
9 | return 42
| ^
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10 | }
| ~
with this patch the SARIF output now has this for the result's location:
"relationships": [{"target": 0,
"kinds": ["relevant"]}]}],
where the result gains a related location :
"relatedLocations": [{"physicalLocation": {"artifactLocation": { [...snip...] },
"region": {"startLine": 10,
"startColumn": 1,
"endColumn": 2},
"contextRegion": {"startLine": 10,
"snippet": {"text": "}\n"}}},
"id": 0}]}]}]}
i.e. that the error also has the secondary location at the trailing
close brace which has the relationship "relevant" to the primary
location (at the suggested insertion point).
The patch also adds test coverage for the SARIF encoding of the fix-it hint.
gcc/ChangeLog:
* diagnostic-format-sarif.cc
(sarif_location_manager::worklist_item::unlabelled_secondary_location):
New enum value.
(sarif_location_manager::m_unlabelled_secondary_locations): New
field.
(sarif_location_manager::process_worklist_item): Handle unlabelled
secondary locations.
(sarif_builder::make_location_object): Generalize code to handle
ranges within a rich_location so as well as using annotations for
those with labels, we now add related locations for those without
labels.
gcc/testsuite/ChangeLog:
* gcc.dg/sarif-output/missing-semicolon.c: New test.
* gcc.dg/sarif-output/sarif.py (get_location_physical_region): New.
(get_location_snippet_text): New.
* gcc.dg/sarif-output/test-missing-semicolon.py: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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No functional change intended.
gcc/ChangeLog:
* diagnostic-format-sarif.cc (sarif_builder::sarif_builder): Assert
that m_line_maps is nonnull.
(diagnostic_output_format_init_sarif_stderr): Add "line_maps"
param and pass to format ctor.
(diagnostic_output_format_init_sarif_file): Likewise.
(diagnostic_output_format_init_sarif_stream): Likewise.
* diagnostic.cc (diagnostic_output_format_init): Pass "line_table"
as line_maps param to the above.
* diagnostic.h (diagnostic_output_format_init_sarif_stderr): Add
"line_maps" param.
(diagnostic_output_format_init_sarif_file): Likewise.
(diagnostic_output_format_init_sarif_stream): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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gcc/ChangeLog:
* diagnostic-format-sarif.cc: Tweak ASCII art in comment
to show edges for both directions in the digraph.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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gcc/testsuite/ChangeLog:
PR libfortran/105361
* gfortran.dg/pr105361.f90: Add newline character to test
input to provide more compliant test.
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The problem here is that in generic types of comparisons don't need
to be boolean types (or vector boolean types). And fixes that by making
sure the types of the conditions match before doing the optimization.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR middle-end/116134
gcc/ChangeLog:
* match.pd (`(a ? x : y) eq/ne (b ? x : y)`): Check that
a and b types match.
(`(a ? x : y) eq/ne (b ? y : x)`): Likewise.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr116134-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
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More enable-rtl-checking fixes for ext-dce. Very similar to the one recently
posted, this time covering more of the shift ops.
I checked all instances of CONSTANT_P guarding [U]INTVAL and fixed all that
looked wrong. I also created a dummy assembler/linker so that I could run the
GCC testsuite on gcn and verified that wasn't tripping any rtl-checking bugs in
ext-dce anymore.
Obviously this has also gone through x86 bootstrap and regression tested.
Pushing to the trunk.
pr target/116104
gcc/
* ext-dce.cc (carry_backpropagate): Change more guards of [U]INTVAL to
test CONST_INT_P rather than CONSTANT_P, fixing rtl-checking failures.
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Loading an arbitrary constant address in a register is expensive for
PRU. So enable section anchoring by default to utilize the unsigned
byte constant offset operand of load/store instructions.
gcc/ChangeLog:
* common/config/pru/pru-common.cc
(TARGET_OPTION_OPTIMIZATION_TABLE): New definition.
* config/pru/pru.cc (TARGET_MIN_ANCHOR_OFFSET): Set minimal
anchor offset.
(TARGET_MAX_ANCHOR_OFFSET): Set maximum anchor offset.
gcc/testsuite/ChangeLog:
* gcc.target/pru/section-anchors-1.c: New test.
* gcc.target/pru/section-anchors-2.c: New test.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
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PRU and other simulator targets do not pass any argv arguments
to main. Instead of erroneously relying on argc==0, use a volatile
variable instead.
I reverted the fix for PR67947 in r6-3891-g8a18fcf4aa1d5c, and made sure
that the updated test case still fails for x86_64:
$ make check-gcc-c RUNTESTFLAGS="dg-torture.exp=pr67947.c"
...
FAIL: gcc.dg/torture/pr67947.c -O1 execution test
...
# of expected passes 8
# of unexpected failures 8
Fix was suggested by Andrew Pinski in PR116154. Committed as obvious.
PR testsuite/116154
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr67947.c: Use volatile variable instead of
argc.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
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This fixes a testsuite regression seen on m68k after some of the recent ext-dce
changes. Ultimately Richard S and I have concluded the bug was a latent issue
in subreg simplification.
Essentially when simplifying something like
(set (target:M1) (subreg:M1 (subreg:M2 (reg:M1) 0) 0))
Where M1 > M2. We'd simplify to:
(set (target:M1) (reg:M1))
The problem is on a big endian target that's wrong. Consider if M1 is DI and
M2 is SI. The original should extract bits 32..63 from the source register
and store them into bits 0..31 of the target register. In the simplified form
it's just a copy, so bits 0..63 of the source end up bits 0..63 of the target.
This shows up as the following regressions on the m68k:
> Tests that now fail, but worked before (3 tests):
>
> gcc: gcc.c-torture/execute/960416-1.c -O2 execution test
> gcc: gcc.c-torture/execute/960416-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none execution test
> gcc: gcc.c-torture/execute/960416-1.c -Os execution test
The fix is pretty trivial, instead of hardcoding "0" as the byte offset in the
test for the simplification, instead we need to use the subreg_lowpart_offset.
Anyway, bootstrapped and regression tested on m68k and x86_64 and tested on the
other embedded targets as well without regressions. Naturally it fixes the
regression noted above. I haven't see other testsuite improvements when I spot
checked some of the big endian crosses.
PR rtl-optimization/116136
gcc/
* simplify-rtx.cc (simplify_context::simplify_subreg): Check
that we're working with the lowpart offset rather than byte 0.
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Per gccint, 'dg-require-*' must come before any
'dg-additional-sources' directives. Fix a handful of deviant cases.
* gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c: Fix dg-require-profiling
directive order.
* gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c: Likewise.
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Per gccint, 'dg-require-effective-target' must come before any
'dg-additional-sources' directives. Fix a handful of deviant cases.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/aapcs64/func-ret-3.c: Fix dg-require-effective-target directive order.
* gcc.target/aarch64/aapcs64/func-ret-4.c: Likewise.
* gfortran.dg/PR100914.f90: Likewise.
libgomp/ChangeLog:
* testsuite/libgomp.c++/pr24455.C: Fix dg-require-effective-target directive order.
* testsuite/libgomp.c/pr24455.c: Likewise.
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We want 'dg-do preprocess', not 'dg-do-preprocess'. Fix that.
PR target/106828
* g++.target/loongarch/pr106828.C: Fix 'dg-do compile' typo.
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We want 'dg-do compile', not 'dg-do-compile'. Fix that.
PR target/69194
PR c++/92024
PR c++/110057
* c-c++-common/Wshadow-1.c: Fix 'dg-do compile' typo.
* g++.dg/tree-ssa/devirt-array-destructor-1.C: Likewise.
* g++.dg/tree-ssa/devirt-array-destructor-2.C: Likewise.
* gcc.target/arm/pr69194.c: Likewise.
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The ACLE declares several helper types and functions to facilitate construction
of `fpm` arguments. These are available when one of the arm_neon.h, arm_sve.h,
or arm_sme.h headers is included. These helpers don't map to specific FP8
instructions and there's no expectation that they will produce a given code
sequence, they're just an abstraction and an aid to the programmer. Thus they are
implemented in a new header file arm_private_fp8.h
Users are not expected to include this file, as it is a mere implementation detail,
subject to change. A check is included to guard against direct inclusion.
gcc/ChangeLog:
* config.gcc (extra_headers): Install arm_private_fp8.h.
* config/aarch64/arm_neon.h: Include arm_private_fp8.h.
* config/aarch64/arm_sve.h: Likewise.
* config/aarch64/arm_private_fp8.h: New file
(fpm_t): New type representing fpmr values.
(enum __ARM_FPM_FORMAT): New enum representing valid fp8 formats.
(enum __ARM_FPM_OVERFLOW): New enum representing how some fp8
calculations work.
(__arm_fpm_init): New.
(__arm_set_fpm_src1_format): Likewise.
(__arm_set_fpm_src2_format): Likewise.
(__arm_set_fpm_dst_format): Likewise.
(__arm_set_fpm_overflow_cvt): Likewise.
(__arm_set_fpm_overflow_mul): Likewise.
(__arm_set_fpm_lscale): Likewise.
(__arm_set_fpm_lscale2): Likewise.
(__arm_set_fpm_nscale): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/fp8-helpers-neon.c: New test of fpmr helper
functions.
* gcc.target/aarch64/acle/fp8-helpers-sve.c: New test of fpmr helper
functions presence.
* gcc.target/aarch64/acle/fp8-helpers-sme.c: New test of fpmr helper
functions presence.
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Unlike most system registers, fpmr can be heavily written to in code that
exercises the fp8 functionality. That is because every fp8 instrinsic call
can potentially change the value of fpmr.
Rather than just use an unspec, we treat the fpmr system register like
all other registers and use a move operation to read and write to it.
We introduce a new class of moveable system registers that, currently,
only accepts fpmr and a new constraint, Umv, that allows us to
selectively use mrs and msr instructions when expanding rtl for them.
Given that there is code that depends on "real" registers coming before
"fake" ones, we introduce a new constant FPM_REGNUM that uses an
existing value and renumber registers below that.
This requires us to update the bitmaps that describe which registers
belong to each register class.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_hard_regno_nregs): Add
support for MOVEABLE_SYSREGS class.
(aarch64_hard_regno_mode_ok): Allow reads and writes to fpmr.
(aarch64_regno_regclass): Support MOVEABLE_SYSREGS class.
(aarch64_class_max_nregs): Likewise.
* config/aarch64/aarch64.h (FIXED_REGISTERS): add fpmr.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REGISTER_NAMES): Likewise.
(enum reg_class): Add MOVEABLE_SYSREGS class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Update class bitmaps to deal with fpmr,
the new MOVEABLE_REGS class and renumbering of registers.
* config/aarch64/aarch64.md: (FPM_REGNUM): added new register
number, reusing old value.
(FFR_REGNUM): Renumber.
(FFRT_REGNUM): Likewise.
(LOWERING_REGNUM): Likewise.
(TPIDR2_BLOCK_REGNUM): Likewise.
(SME_STATE_REGNUM): Likewise.
(TPIDR2_SETUP_REGNUM): Likewise.
(ZA_FREE_REGNUM): Likewise.
(ZA_SAVED_REGNUM): Likewise.
(ZA_REGNUM): Likewise.
(ZT0_REGNUM): Likewise.
(*mov<mode>_aarch64): Add support for moveable sysregs.
(*movsi_aarch64): Likewise.
(*movdi_aarch64): Likewise.
* config/aarch64/constraints.md (MOVEABLE_SYSREGS): New constraint.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/fp8.c: New tests.
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This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (fp8): New.
* config/aarch64/aarch64.h (TARGET_FP8): Likewise.
* doc/invoke.texi (AArch64 Options): Document new -march flags
and extensions.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/fp8.c: New test.
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Unfortunately, my r15-1946 fix broke the attached testcase; the
constexpr evaluation reported an error about not being able to
evaluate the code emitted by build_vec_init. Jason figured out
it's because we were wrongly setting try_const to false, where
in fact it should have been true. Value-initialization of scalars
is constexpr, so we should check that alongside of
type_has_constexpr_default_constructor.
PR c++/115645
gcc/cp/ChangeLog:
* init.cc (build_vec_init): When initializing a scalar type, try to
create a constant initializer.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/constexpr-new23.C: New test.
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32bit x86 CPUs won't natively support the FFS operation on a 64 bit
type. Therefore, I'm setting the long long int part of the
switch-exp-transform-3.c test to only execute with 64bit targets.
gcc/testsuite/ChangeLog:
* gcc.target/i386/switch-exp-transform-3.c: Set the long long
int test to only execute with 64bit targets.
Signed-off-by: Filip Kastl <fkastl@suse.cz>
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Per a gcc-help thread we are generating sub-optimal code for
__builtin_bswap{32,64}. To fix it:
- Use a single revb.d instruction for bswapdi2.
- Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT,
revb.2h + rotri.w for !TARGET_64BIT.
- Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single
revb.2w instruction for bswapdi2 (x) r>> 32.
Unfortunately I cannot figure out a way to make the compiler generate
revb.4h or revh.{2w,d} instructions.
gcc/ChangeLog:
* config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H,
UNSPEC_REVH_D): Remove UNSPECs.
(revb_4h, revh_d): Remove define_insn.
(revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of
an UNSPEC.
(revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn.
(bswapsi2): Change to define_expand. Only expand to revb.2h +
rotri.w if !TARGET_64BIT.
(bswapdi2): Change to define_insn of which the output is just a
revb.d instruction.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/revb.c: New test.
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In r15-1207 I was too stupid to realize we just need to relax
ins_zero_bitmask_operand to allow using bstrins for aligning, instead of
adding a new split. And, "> 12" in ins_zero_bitmask_operand also makes
no sense: it rejects bstrins for things like "x & ~4l" with no good
reason.
So fix my errors now.
gcc/ChangeLog:
* config/loongarch/predicates.md (ins_zero_bitmask_operand):
Cover more cases that bstrins can benefit.
(high_bitmask_operand): Remove.
* config/loongarch/constraints.md (Yy): Remove.
* config/loongarch/loongarch.md (and<mode>3_align): Remove.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/bstrins-4.c: New test.
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When we gimplify &MEM[0B + 4] we are re-folding the address in case
types are not canonical which ends up with a constant address that
recompute_tree_invariant_for_addr_expr ICEs on. Properly guard
that call.
PR middle-end/101478
* gimplify.cc (gimplify_addr_expr): Check we still have an
ADDR_EXPR before calling recompute_tree_invariant_for_addr_expr.
* gcc.dg/pr101478.c: New testcase.
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[PR116065]
When introducing munroll-only-small-loops, the option was marked as
Target Save and added to -O2 default which makes attribute(optimize)
resets target option and causing error when cmdline has O1 and
funciton attribute has O2 and other target options. Mark this option
as Optimization to fix.
gcc/ChangeLog
PR target/116065
* config/i386/i386.opt (munroll-only-small-loops): Mark as
Optimization instead of Save.
gcc/testsuite/ChangeLog
PR target/116065
* gcc.target/i386/pr116065.c: New test.
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In g:9d20529d94b23275885f380d155fe8671ab5353a, I'd extended
insn_propagation to handle simple cases of hard-reg mode punning.
The punned "to" value was created using simplify_subreg rather
than simplify_gen_subreg, on the basis that hard-coded subregs
aren't generally useful after RA (where hard-reg propagation is
expected to happen).
This PR is about a case where the subreg gets pushed into the
operands of a plus, but the subreg on one of the operands
cannot be simplified. Specifically, we have to generate
(subreg:SI (reg:DI sp) 0) rather than (reg:SI sp), since all
references to the stack pointer must be via stack_pointer_rtx.
However, code in x86 (reasonably) expects no subregs of registers
to appear after RA, except for special cases like strict_low_part.
This leads to an awkward situation where we can't ban subregs of sp
(because of the strict_low_part use), can't allow direct references
to sp in other modes (because of the stack_pointer_rtx requirement),
and can't allow rvalue uses of the subreg (because of the "no subregs
after RA" assumption). It all seems a bit of a mess...
I sat on this for a while in the hope that a clean solution might
become apparent, but in the end, I think we'll just have to check
manually for nested subregs and punt on them.
gcc/
PR rtl-optimization/115881
* recog.cc: Include rtl-iter.h.
(insn_propagation::apply_to_rvalue_1): Check that the result
of simplify_subreg does not include nested subregs.
gcc/testsuite/
PR rtl-optimization/115881
* gcc.c-torture/compile/pr115881.c: New test.
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As PR105359 shows, we disable some FLOAT128 expanders for
64-bit long double, but in fact IEEE float128 types like
__ieee128 are only guarded with TARGET_FLOAT128_TYPE and
TARGET_LONG_DOUBLE_128 is only checked when determining if
we can reuse long_double_type_node. So this patch is to
relax all affected FLOAT128 expander conditions for
FLOAT128_IEEE_P. By the way, currently IBM double double
type __ibm128 is guarded by TARGET_LONG_DOUBLE_128, so we
have to use TARGET_LONG_DOUBLE_128 for it. IMHO, it's not
necessary and can be enhanced later.
Btw, for all test cases mentioned in PR105359, I removed
the xfails and tested them with explicit -mlong-double-64,
both pr79004.c and float128-hw.c are tested well and
float128-hw4.c isn't tested (unsupported due to 64 bit
long double conflicts with -mabi=ieeelongdouble).
PR target/105359
gcc/ChangeLog:
* config/rs6000/rs6000.md (@extenddf<FLOAT128:mode>2): Don't check
TARGET_LONG_DOUBLE_128 for FLOAT128_IEEE_P modes.
(extendsf<FLOAT128:mode>2): Likewise.
(trunc<FLOAT128:mode>df2): Likewise.
(trunc<FLOAT128:mode>sf2): Likewise.
(floatsi<FLOAT128:mode>2): Likewise.
(fix_trunc<FLOAT128:mode>si2): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr79004.c: Remove xfails.
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r14-1832 adds recognition pattern, ifn and optab for ABD
(ABsolute Difference), we have some vector absolute
difference unsigned instructions since ISA 3.0, as the
associated test cases shown, they are not exploited well
as we don't define it (them) with a standard name. So this
patch is to rename it with standard name first. And it
merges both define_expand and define_insn as a separated
define_expand isn't needed. Besides, it adjusts the RTL
pattern by using generic umax and umin rather than
UNSPEC_VADU, it's more meaningful and can catch umin/umax
opportunity.
gcc/ChangeLog:
* config/rs6000/altivec.md (p9_vadu<mode>3): Rename to ...
(uabd<mode>3): ... this. Update RTL pattern with umin and umax rather
than UNSPEC_VADU.
(vadu<mode>3): Remove.
(UNSPEC_VADU): Remove.
(usadv16qi): Replace gen_p9_vaduv16qi3 with gen_uabdv16qi3.
(usadv8hi): Replace gen_p9_vaduv8hi3 with gen_uabdv8hi3.
* config/rs6000/rs6000-builtins.def (__builtin_altivec_vadub): Replace
expander with uabdv16qi3.
(__builtin_altivec_vaduh): Adjust expander with uabdv8hi3.
(__builtin_altivec_vaduw): Adjust expander with uabdv4si3.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/abd-vectorize-1.c: New test.
* gcc.target/powerpc/abd-vectorize-2.c: New test.
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if TARGET_64BIT
We already had "si3_extend" insns and we hoped the fwprop or combine
passes can use them to remove unnecessary sign extensions. But this
does not always work: for cases like x << 1 | y, the compiler
tends to do
(sign_extend:DI
(ior:SI (ashift:SI (reg:SI $r4)
(const_int 1))
(reg:SI $r5)))
instead of
(ior:DI (sign_extend:DI (ashift:SI (reg:SI $r4) (const_int 1)))
(sign_extend:DI (reg:SI $r5)))
So we cannot match the ashlsi3_extend instruction here and we get:
slli.w $r4,$r4,1
or $r4,$r5,$r4
slli.w $r4,$r4,0 # <= redundant
jr $r1
To eliminate this redundant extension we need to turn SImode shift etc.
to DImode "si3_extend" operations earlier, when we expand the SImode
operation. We are already doing this for addition, now do it for
shifts, rotates, substract, multiplication, division, and modulo as
well.
The bytepick.w definition for TARGET_64BIT needs to be adjusted so it
won't be undone by the shift expanding.
gcc/ChangeLog:
* config/loongarch/loongarch.md (optab): Add (rotatert "rotr").
(<optab:any_shift><mode>3, <optab:any_div><mode>3,
sub<mode>3, rotr<mode>3, mul<mode>3): Add a "*" to the insn name
so we can redefine the names with define_expand.
(*<optab:any_shift>si3_extend): Remove "*" so we can use them
in expanders.
(*subsi3_extended, *mulsi3_extended): Likewise, also remove the
trailing "ed" for consistency.
(*<optab:any_div>si3_extended): Add mode for sign_extend to
prevent an ICE using it in expanders.
(shift_w, arith_w): New define_code_iterator.
(<optab:any_w><mode>3): New define_expand. Expand with
<optab:any_w>si3_extend for SImode if TARGET_64BIT.
(<optab:arith_w><mode>3): Likewise.
(mul<mode>3): Expand to mulsi3_extended for SImode if
TARGET_64BIT and ISA_HAS_DIV32.
(<optab:any_div><mode>3): Expand to <optab:any_div>si3_extended
for SImode if TARGET_64BIT.
(rotl<mode>3): Expand to rotrsi3_extend for SImode if
TARGET_64BIT.
(bytepick_w_<bytepick_imm>): Add mode for lshiftrt and ashift.
(bitsize, bytepick_imm, bytepick_w_ashift_amount): New
define_mode_attr.
(bytepick_w_<bytepick_imm>_extend): Adjust for the RTL change
caused by 32-bit shift expanding. Now bytepick_imm only covers
2 and 3, separate one remaining case to ...
(bytepick_w_1_extend): ... here, new define_insn.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/bitwise_extend.c: New test.
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