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2022-11-29ipa/107897 - avoid property verification ICE after errorRichard Biener1-1/+2
The target clone pass is the only small IPA pass that doesn't disable itself after errors but has properties whose verification can fail because we cut off build SSA passes after errors. PR ipa/107897 * multiple_target.cc (pass_target_clone::gate): Disable after errors.
2022-11-29re-run configureMartin Liska1-3/+4
gcc/ChangeLog: * configure: Regenerate.
2022-11-29gcc/configure.ac: fix AC_DEFINE ENABLE_MULTIARCHYunQiang Su1-1/+1
Description section was missing in AC_DEFINE(ENABLE_MULTIARCH, 1). It makes autoheader fail. Thanks Lulu Cheng points it out. gcc/ChangeLog: * configure.ac: add description for AC_DEFINE(ENABLE_MULTIARCH, 1)
2022-11-29Daily bump.GCC Administrator6-1/+1364
2022-11-28c++: simple-requirement starting with 'typename' [PR101733]Jason Merrill2-1/+25
Usually a requirement starting with 'typename' is a type-requirement, but it might be a simple-requirement such as a functional cast to a typename-type. PR c++/101733 gcc/cp/ChangeLog: * parser.cc (cp_parser_requirement): Parse tentatively for the 'typename' case. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-requires32.C: New test.
2022-11-28c++: be more strict about 'concept bool'Jason Merrill1-4/+4
Some clang folks mailed me asking about being less permissive about 'concept bool', so let's bump it up from pedwarn to permerror. gcc/cp/ChangeLog: * parser.cc (cp_parser_decl_specifier_seq): Change 'concept bool' diagnostic from pedwarn to permerror.
2022-11-28Fix comment for (A / (1 << B)) -> (A >> B).Andrew Pinski1-1/+1
There was a small typo where Also was done twice. The second also should have been handled. This fixes that. Committed as obvious after a build. gcc/ChangeLog: * match.pd ((A / (1 << B)) -> (A >> B).): Fix comment.
2022-11-28riscv: improve cost model for loading 64bit constant in rv32Sinan2-0/+64
The motivation of this patch is to correct the wrong estimation of the number of instructions needed for loading a 64bit constant in rv32 in the current cost model(riscv_interger_cost). According to the current implementation, if a constant requires more than 3 instructions(riscv_const_insn and riscv_legitimate_constant_p), then the constant will be put into constant pool when expanding gimple to rtl(legitimate_constant_p hook and emit_move_insn). So the inaccurate cost model leads to the suboptimal codegen in rv32 and the wrong estimation part could be corrected through this fix. e.g. the current codegen for loading 0x839290001 in rv32 lui a5,%hi(.LC0) lw a0,%lo(.LC0)(a5) lw a1,%lo(.LC0+4)(a5) .LC0: .word 958988289 .word 8 output after this patch li a0,958988288 addi a0,a0,1 li a1,8 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer): Improve some cases of loading 64bit constants for rv32. gcc/testsuite/ChangeLog: * gcc.target/riscv/rv32-load-64bit-constant.c: New test.
2022-11-28RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEUMaciej W. Rozycki5-2/+50
We produce inefficient code for some synthesized SImode conditional set operations (i.e. ones that are not directly implemented in hardware) on RV64. For example a piece of C code like this: int sleu (unsigned int x, unsigned int y) { return x <= y; } gets compiled (at `-O2') to this: sleu: sgtu a0,a0,a1 # 9 [c=4 l=4] *sgtu_disi xori a0,a0,1 # 10 [c=4 l=4] *xorsi3_internal/1 andi a0,a0,1 # 16 [c=4 l=4] anddi3/1 ret # 25 [c=0 l=4] simple_return or (at `-O1') to this: sleu: sgtu a0,a0,a1 # 9 [c=4 l=4] *sgtu_disi xori a0,a0,1 # 10 [c=4 l=4] *xorsi3_internal/1 sext.w a0,a0 # 16 [c=4 l=4] extendsidi2/0 ret # 24 [c=0 l=4] simple_return This is because the middle end expands a SLEU operation missing from RISC-V hardware into a sequence of a SImode SGTU operation followed by an explicit SImode XORI operation with immediate 1. And while the SGTU machine instruction (alias SLTU with the input operands swapped) gives a properly sign-extended 32-bit result which is valid both as a SImode or a DImode operand the middle end does not see that through a SImode XORI operation, because we tell the middle end that the RISC-V target (unlike MIPS) may hold values in DImode integer registers that are valid for SImode operations even if not properly sign-extended. However the RISC-V psABI requires that 32-bit function arguments and results passed in 64-bit integer registers be properly sign-extended, so this is explicitly done at the conclusion of the function. Fix this by making the backend use a sequence of a DImode SGTU operation followed by a SImode SEQZ operation instead. The latter operation is known by the middle end to produce a properly sign-extended 32-bit result and therefore combine gets rid of the sign-extension operation that follows and actually folds it into the very same XORI machine operation resulting in: sleu: sgtu a0,a0,a1 # 9 [c=4 l=4] *sgtu_didi xori a0,a0,1 # 16 [c=4 l=4] xordi3/1 ret # 25 [c=0 l=4] simple_return instead (although the SEQZ alias SLTIU against immediate 1 machine instruction would equally do and is actually retained at `-O0'). This is handled analogously for the remaining synthesized operations of this kind, i.e. `SLE', `SGEU', and `SGE'. gcc/ * config/riscv/riscv.cc (riscv_emit_int_order_test): Use EQ 0 rather that XOR 1 for LE and LEU operations. gcc/testsuite/ * gcc.target/riscv/sge.c: New test. * gcc.target/riscv/sgeu.c: New test. * gcc.target/riscv/sle.c: New test. * gcc.target/riscv/sleu.c: New test.
2022-11-28Fortran: ICE with elemental and dummy argument with VALUE attribute [PR107819]Harald Anlauf2-0/+29
gcc/fortran/ChangeLog: PR fortran/107819 * trans-stmt.cc (gfc_conv_elemental_dependencies): In checking for elemental dependencies, treat dummy argument with VALUE attribute as implicitly having intent(in). gcc/testsuite/ChangeLog: PR fortran/107819 * gfortran.dg/elemental_dependency_7.f90: New test.
2022-11-28tree-optimization/107896 - allow v2si to dimode unpacksRichard Biener1-2/+5
The following avoids ICEing for V2SI -> DImode vec_unpacks_lo. PR tree-optimization/107896 * tree-vect-stmts.cc (supportable_widening_operation): Handle non-vector mode intermediate mode.
2022-11-28Support %b, %B for -Wformat-overflow (sprintf, snprintf)Frolov Daniil2-16/+53
gcc/ChangeLog: * gimple-ssa-sprintf.cc (fmtresult::type_max_digits): Handle base == 2. (tree_digits): Likewise. (format_integer): Likewise. (parse_directive): Add cases for %b and %B directives. gcc/testsuite/ChangeLog: * gcc.dg/Wformat-overflow1.c: New test.
2022-11-28RISC-V: fix stack access before allocation.Fei Gao4-4/+29
In current riscv stack frame allocation, 2 steps are used. The first step allocates memories at least for callee saved GPRs and FPRs, and the second step allocates the rest if stack size is greater than signed 12-bit range. But it's observed in some cases, like gcc.target/riscv/stack_frame.c in my patch, callee saved FPRs fail to be included in the first step allocation, so we get generated instructions like this: li t0,-16384 addi sp,sp,-48 addi t0,t0,752 ... fsw fs4,-4(sp) #issue here of accessing before allocation ... add sp,sp,t0 "fsw fs4,-4(sp)" has issue here of accessing stack before allocation. Although "add sp,sp,t0" reserves later the memory for fs4, it exposes a risk when an interrupt comes in between "fsw fs4,-4(sp)" and "add sp,sp,t0", resulting in a corruption in the stack storing fs4 after interrupt context saving and a failure to get the correct value of fs4 later. This patch fixes issue above, adapts testcases identified in regression tests, and add a new testcase for the change. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_first_stack_step): Fix computation of MIN_FIRST_STEP to cover FP save area too. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr93304.c: Adapt testcase for the change, constrain match to assembly instructions only. * gcc.target/riscv/rvv/base/spill-11.c: Adapt testcase for the change. * gcc.target/riscv/stack_frame.c: New test.
2022-11-28c++: Allow module name to be a single letter on WindowsTorbjörn SVENSSON1-1/+9
On Windows, the ':' character is special and when the module name is a single character, like 'A', then the flatname would be (for example) 'A:Foo'. On Windows, 'A:Foo' is treated as an absolute path by the module loader and is likely not found. Without this patch, the test case pr98944_c.C fails with: In module imported at /src/gcc/testsuite/g++.dg/modules/pr98944_b.C:7:1, of module A:Foo, imported at /src/gcc/testsuite/g++.dg/modules/pr98944_c.C:7: A:Internals: error: header module expected, module 'A:Internals' found A:Internals: error: failed to read compiled module: Bad file data A:Internals: note: compiled module file is 'gcm.cache/A-Internals.gcm' In module imported at /src/gcc/testsuite/g++.dg/modules/pr98944_c.C:7:8: A:Foo: error: failed to read compiled module: Bad import dependency A:Foo: note: compiled module file is 'gcm.cache/A-Foo.gcm' A:Foo: fatal error: returning to the gate for a mechanical issue compilation terminated. gcc/cp/ChangeLog: * module.cc: On Windows, 'A:Foo' is supposed to be a module and not a path. Co-Authored-By: Yvan ROUX <yvan.roux@foss.st.com> Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
2022-11-28ada: Adjust runtime library and User's Guide to PIE default on LinuxEric Botcazou4-64/+98
gcc/ada/ * libgnat/g-traceb.ads: Minor tweaks in the commentary. (Executable_Load_Address): New function. * doc/gnat_ugn/gnat_and_program_execution.rst (Non-Symbolic Traceback): Adjust to PIE default on Linux. (Symbolic Traceback): Likewise. * doc/gnat_ugn/gnat_utility_programs.rst (gnatsymbolize): Likewise. * gnat_ugn.texi: Regenerate.
2022-11-28ada: doc/share/conf.py: Switch the HTML documentation to using the RTD themeJoel Brobecker1-2/+2
This commit adjust the sphinx configuration to use the "Read The Docs" theme, which has the advantage of allowing the navigation bar (containing among other things a search bar, and the TOC) to stay fixed while scrolling the contents of the page being read. This is particularly useful to allow access to those features while reading a long page, for instance. gcc/ada/ * doc/share/conf.py (extensions): Add 'sphinx_rtd_theme'. (html_theme): Set to 'sphinx_rtd_theme'.
2022-11-28ada: Annotate GNAT.Source_Info with an abstract stateClaire Dross1-1/+19
So it can be used safely from SPARK code. The abstract state represents the source code information that is accessed by the functions defined in Source_Info. It is volatile as it is updated asyncronously when moving in the code. gcc/ada/ * libgnat/g-souinf.ads (Source_Code_Information): Add a new volatile abstract state and add it in the global contract of all functions defined in Source_Info.
2022-11-28ada: Fix internal error on conversion as in/out actual with -gnatVaEric Botcazou1-18/+43
The problem is that the regular expansion of the conversion around the call to the subprogram is disabled by the expansion of the validity check around the same call, as documented in Expand_Actuals: -- This case is given higher priority because the subsequent check -- for type conversion may add an extra copy of the variable and -- prevent proper value propagation back in the original object. Now the two mechanisms need to cooperate in order for the code to compile. gcc/ada/ * exp_ch6.adb (Expand_Actuals.Add_Call_By_Copy_Code): Deal with a reference to a validation variable in the actual. (Expand_Actuals.Add_Validation_Call_By_Copy_Code): Minor tweak. (Expand_Actuals): Call Add_Validation_Call_By_Copy_Code directly only if Add_Call_By_Copy_Code is not to be invoked.
2022-11-28ada: Add PIE support to backtraces on LinuxEric Botcazou1-3/+3
gcc/ada/ * adaint.c [Linux]: Include <link.h>. (__gnat_get_executable_load_address) [Linux]: Enable.
2022-11-28ada: Implement change to SPARK RM rule on state refinementYannick Moy4-10/+33
SPARK RM 7.1.4(4) does not mandate anymore that a package with abstract states has a completing body, unless the package state is mentioned in Part_Of specifications. Implement that change. gcc/ada/ * sem_prag.adb (Check_Part_Of_Abstract_State): Add verification related to use of Part_Of, so that constituents in private childs that refer to state in a sibling or parent unit force that unit to have a body. * sem_util.adb (Check_State_Refinements): Drop the requirement to have always a package body for state refinement, when the package state is mentioned in no Part_Of specification. * sem_ch3.adb (Analyze_Declarations): Refresh SPARK refs in comment. * sem_ch7.adb (Analyze_Package_Declaration): Likewise.
2022-11-28tree-optimization/107493 - SCEV analysis with conversionsRichard Biener2-2/+21
This shows another case where trying to validate conversions during the CHREC SCC analysis fails because said analysis assumes we are converting a complete SCC. Like the constraint on the initial conversion seen restrict all conversions handled to sign-changes. PR tree-optimization/107493 * tree-scalar-evolution.cc (scev_dfs::follow_ssa_edge_expr): Only handle no-op and sign-changing conversions. * gcc.dg/torture/pr107493.c: New testcase.
2022-11-28gcn: Fix __builtin_gcn_first_call_this_thread_pTobias Burnus2-21/+8
Contrary naive expectation, unspec_volatile (via prologue_use) did not prevent the cprop pass (at -O2) to remove the access to the s[0:1] (PRIVATE_SEGMENT_BUFFER_ARG) register as the volatile got just put on the preceeding pseudoregister. Solution: Use gen_rtx_USE instead. Additionally, this patch removes (gen_)prologue_use_di as it is then no longer used. Finally, as we already do bit manipulation, instead of using the full 64bit side - and then just keeping the value of 's0', just move directly to use only s1 of s[0:1] and do the bit manipulations there, generating more readable assembly code and better matching the '#else' branch. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_expand_builtin_1): Work on s1 instead of s[0:1] and use USE to prevent removal of setting that register. * config/gcn/gcn.md (prologue_use_di): Remove.
2022-11-28OpenMP/Fortran: Permit end-clause on directiveTobias Burnus10-193/+856
gcc/fortran/ChangeLog: * openmp.cc (OMP_DO_CLAUSES, OMP_SCOPE_CLAUSES, OMP_SECTIONS_CLAUSES): Add 'nowait'. (OMP_SINGLE_CLAUSES): Add 'nowait' and 'copyprivate'. (gfc_match_omp_distribute_parallel_do, gfc_match_omp_distribute_parallel_do_simd, gfc_match_omp_parallel_do, gfc_match_omp_parallel_do_simd, gfc_match_omp_parallel_sections, gfc_match_omp_teams_distribute_parallel_do, gfc_match_omp_teams_distribute_parallel_do_simd): Disallow 'nowait'. (gfc_match_omp_workshare): Match 'nowait' clause. (gfc_match_omp_end_single): Use clause matcher for 'nowait'. (resolve_omp_clauses): Reject 'nowait' + 'copyprivate'. * parse.cc (decode_omp_directive): Break too long line. (parse_omp_do, parse_omp_structured_block): Diagnose duplicated 'nowait' clause. libgomp/ChangeLog: * libgomp.texi (OpenMP 5.2): Mark end-directive as Y. gcc/testsuite/ChangeLog: * gfortran.dg/gomp/copyprivate-1.f90: New test. * gfortran.dg/gomp/copyprivate-2.f90: New test. * gfortran.dg/gomp/nowait-2.f90: Move dg-error tests ... * gfortran.dg/gomp/nowait-4.f90: ... to this new file. * gfortran.dg/gomp/nowait-5.f90: New test. * gfortran.dg/gomp/nowait-6.f90: New test. * gfortran.dg/gomp/nowait-7.f90: New test. * gfortran.dg/gomp/nowait-8.f90: New test.
2022-11-28asan: fix unsafe optimization of Asan checks.Yuri Gribov2-9/+56
PR sanitizer/106558 gcc/ * sanopt.cc: Do not optimize out checks for non-SSA addresses. gcc/testsuite/ * c-c++-common/asan/pr106558.c: New test.
2022-11-28i386: Fix up ix86_abi handling [PR106875]Jakub Jelinek3-4/+7
The following testcase fails since my changes to make also opts_set saved/restored upon function target/optimization changes (before it has been acting as "has this option be ever explicit anywhere?"). The problem is that for ix86_abi we depend on the opts_set value for it in ix86_option_override_internal: SET_OPTION_IF_UNSET (opts, opts_set, ix86_abi, DEFAULT_ABI); but as it is a TargetSave, the backend code is required to save/restore it manually (it does that) and since gcc 11 also to save/restore the opts_set bit for it (which isn't done). We don't do that for various other TargetSave which ix86_function_specific_{save,restore} saves/restores, but as long as we never test opts_set for it, it doesn't really matter. One possible fix would be to introduce some new TargetSave into which ix86_function_specific_{save,restore} would save/restore a bitmask of the opts_set bits. The following patch uses an easier fix, by making it a TargetVariable instead the saving/restoring is handled by the generated code. The differences in options.h are just slight movements on where *ix86_abi stuff appears in it, ditto for options.cc, the real differences are just in options-save.cc, where cl_target_option_save gets: + ptr->x_ix86_abi = opts->x_ix86_abi; ... + if (opts_set->x_ix86_abi) mask |= HOST_WIDE_INT_1U << 3; (plus adjustments of following TargetVariables mask related stuff), cl_target_option_restore gets: + opts->x_ix86_abi = ptr->x_ix86_abi; ... + opts_set->x_ix86_abi = static_cast<enum calling_abi>((mask & 1) != 0); + mask >>= 1; plus the movements in other functions too. So, by it being a TargetVariable, the only thing that changed is that we don't need to handle it manually in ix86_function_specific_{save,restore} because it is handled automatically including the opts_set stuff. 2022-11-28 Jakub Jelinek <jakub@redhat.com> PR target/106875 * config/i386/i386.opt (x_ix86_abi): Remove TargetSave. (ix86_abi): Replace it with TargetVariable. * config/i386/i386-options.cc (ix86_function_specific_save, ix86_function_specific_restore): Don't save and restore x_ix86_abi. * g++.target/i386/pr106875.C: New test.
2022-11-28arm: improve tests for vsetq_lane*Andrea Corallo10-34/+284
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
2022-11-28arm: improve tests for vrshlq*Andrea Corallo30-84/+564
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
2022-11-28arm: improve tests and fix vrmlaldavhaq*Andrea Corallo3-6/+62
gcc/ChangeLog: * config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si, mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
2022-11-28arm: improve tests for vqsubq*Andrea Corallo24-72/+516
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: * gcc.target/arm/mve/intrinsics/vqsubq_u8.c:
2022-11-28arm: improve tests for vqrdmlashq_m*Andrea Corallo3-24/+78
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c:
2022-11-28arm: improve tests for vqrdmlahq*Andrea Corallo6-42/+132
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
2022-11-28arm: improve tests for vqdmul*Andrea Corallo28-84/+504
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
2022-11-28arm: improve tests for vqdmlahq_m*Andrea Corallo12-84/+264
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
2022-11-28arm: improve tests for vqaddq_m*Andrea Corallo24-72/+516
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
2022-11-28arm: improve tests for vmlasq*Andrea Corallo12-84/+348
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
2022-11-28arm: improve tests and fix vmlaldavaxq*Andrea Corallo5-27/+91
gcc/ChangeLog: * config/arm/mve.md (mve_vmlaldavaq_<supf><mode>) (mve_vmlaldavaxq_s<mode>, mve_vmlaldavaxq_p_<supf><mode>): Fix spacing vs tabs. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
2022-11-28arm: improve tests for vmladavaq*Andrea Corallo12-81/+336
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
2022-11-28arm: improve tests for viwdupq*Andrea Corallo18-106/+658
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Improve tests. * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
2022-11-28arm: improve tests for vhsubq_m*Andrea Corallo36-114/+828
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
2022-11-28arm: improve tests for vhaddq_m*Andrea Corallo36-114/+828
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
2022-11-28arm: improve tests for vfmasq_m*Andrea Corallo2-16/+84
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
2022-11-28arm: improve tests and fix vsubq*Andrea Corallo49-145/+1261
gcc/ChangeLog: * config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
2022-11-28arm: improve tests for vmulq*Andrea Corallo48-160/+1148
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
2022-11-28arm: improve tests and fix vadd*Andrea Corallo81-252/+1864
gcc/ChangeLog: * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si) (mve_vaddq_n_<supf><mode>, mve_vaddvaq_<supf><mode>) (mve_vaddlvaq_<supf>v4si, mve_vaddq_n_f<mode>) (mve_vaddlvaq_p_<supf>v4si, mve_vaddq<mode>, mve_vaddq_f<mode>): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Improve test. * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
2022-11-28arm: Add integer vector overloading of vsubq_x instrinsicStam Markianos-Wright1-0/+28
In the past we had only defined the vsubq_x generic overload of the vsubq_x_* intrinsics for float vector types. This would cause them to fall back to the `__ARM_undef` failure state if they was called through the generic version. This patch simply adds these overloads. gcc/ChangeLog: * config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads. (__arm_vsubq_x Integer): New.
2022-11-28arm: Explicitly specify other float types for _Generic overloading [PR107515]Stam Markianos-Wright1-0/+3
This patch adds explicit references to other float types to __ARM_mve_typeid in arm_mve.h. Resolves PR 107515: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107515 gcc/ChangeLog: PR target/107515 * config/arm/arm_mve.h (__ARM_mve_typeid): Add float types.
2022-11-28arm: propagate fixed overloading of MVE intrinsic scalar parametersStam Markianos-Wright1-553/+553
This is a mechanical patch that propagates the change proposed in my previous patch for vaddq[_m]_n across all other polymorphic MVE intrinsic overloads of scalar types. The find and Replace patterns used were: s/__ARM_mve_coerce\(__p(\d+), [u]?int(8|16|32|64)_t\) /__ARM_mve_coerce3(p$1, int)/g s/__ARM_mve_coerce2\(__p(\d+), double\) /__ARM_mve_coerce2(p$1, double)/g gcc/ChangeLog: PR target/96795 * config/arm/arm_mve.h (__arm_vaddq): Fix Overloading. (__arm_vmulq): Likewise. (__arm_vcmpeqq): Likewise. (__arm_vcmpneq): Likewise. (__arm_vmaxnmavq): Likewise. (__arm_vmaxnmvq): Likewise. (__arm_vminnmavq): Likewise. (__arm_vsubq): Likewise. (__arm_vminnmvq): Likewise. (__arm_vrshlq): Likewise. (__arm_vqsubq): Likewise. (__arm_vqdmulltq): Likewise. (__arm_vqdmullbq): Likewise. (__arm_vqdmulhq): Likewise. (__arm_vqaddq): Likewise. (__arm_vhaddq): Likewise. (__arm_vhsubq): Likewise. (__arm_vqdmlashq): Likewise. (__arm_vqrdmlahq): Likewise. (__arm_vmlasq): Likewise. (__arm_vqdmlahq): Likewise. (__arm_vmaxnmavq_p): Likewise. (__arm_vmaxnmvq_p): Likewise. (__arm_vminnmavq_p): Likewise. (__arm_vminnmvq_p): Likewise. (__arm_vfmasq_m): Likewise. (__arm_vsetq_lane): Likewise. (__arm_vcmpneq_m): Likewise. (__arm_vhaddq_x): Likewise. (__arm_vhsubq_x): Likewise. (__arm_vqrdmlashq_m): Likewise. (__arm_vqdmlashq_m): Likewise. (__arm_vmlaldavaxq_p): Likewise. (__arm_vmlasq_m): Likewise. (__arm_vqdmulhq_m): Likewise. (__arm_vqdmulltq_m): Likewise. (__arm_viwdupq_m): Likewise. (__arm_viwdupq_u16): Likewise. (__arm_viwdupq_u32): Likewise. (__arm_viwdupq_u8): Likewise. (__arm_vdwdupq_m): Likewise. (__arm_vdwdupq_u16): Likewise. (__arm_vdwdupq_u32): Likewise. (__arm_vdwdupq_u8): Likewise. (__arm_vaddlvaq): Likewise. (__arm_vaddlvaq_p): Likewise. (__arm_vaddvaq): Likewise. (__arm_vaddvaq_p): Likewise. (__arm_vcmphiq_m): Likewise. (__arm_vmladavaq_p): Likewise. (__arm_vmladavaxq): Likewise. (__arm_vmlaldavaxq): Likewise. (__arm_vrmlaldavhaq_p): Likewise.
2022-11-28arm: further fix overloading of MVE vaddq[_m]_n intrinsicStam Markianos-Wright1-38/+40
It was observed that in tests `vaddq_m_n_[s/u][8/16/32].c`, the _Generic resolution would fall back to the `__ARM_undef` failure state. This is a regression since `dc39db873670bea8d8e655444387ceaa53a01a79` and `6bd4ce64eb48a72eca300cb52773e6101d646004`, but it previously wasn't identified, because the tests were not checking for this kind of failure. The above commits changed the definitions of the intrinsics from using `[u]int[8/16/32]_t` types for the scalar argument to using `int`. This allowed `int` to be supported in user code through the overloaded `#defines`, but seems to have broken the `[u]int[8/16/32]_t` types The solution implemented by this patch is to explicitly use a new _Generic mapping from all the `[u]int[8/16/32]_t` types for int. With this change, both `int` and `[u]int[8/16/32]_t` parameters are supported from user code and are handled by the overloading mechanism correctly. Note that in these scalar cases it is safe to pass the raw p<n>, rather than the typeof-ed __p<n>, because we are not at risk of the _Generics being exponentially expanded on the `n` scalar argument to an `_n` intrinsic. Using p<n> instead will give a more accurate error message to the user, should something be wrong with that argument. gcc/ChangeLog: PR target/96795 * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types. (__arm_vaddq_m_n_s32): Likewise. (__arm_vaddq_m_n_s16): Likewise. (__arm_vaddq_m_n_u8): Likewise. (__arm_vaddq_m_n_u32): Likewise. (__arm_vaddq_m_n_u16): Likewise. (__arm_vaddq_m): Fix Overloading. (__ARM_mve_coerce3): New.
2022-11-28arm: improve tests and fix vabsq*Andrea Corallo16-43/+309
gcc/ChangeLog: * config/arm/mve.md (mve_vabsq_f<mode>): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
2022-11-28arm: improve tests for vabdq*Andrea Corallo24-73/+464
gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
generated by cgit v1.1 at 2025-07-15 16:36:36 +0000