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2023-06-01Fortran: force error on bad KIND specifier [PR88552]Harald Anlauf2-0/+10
gcc/fortran/ChangeLog: PR fortran/88552 * decl.cc (gfc_match_kind_spec): Use error path on missing right parenthesis. (gfc_match_decl_type_spec): Use error return when an error occurred during matching a KIND specifier. gcc/testsuite/ChangeLog: PR fortran/88552 * gfortran.dg/pr88552.f90: New test.
2023-06-01testsuite: print any leaking torture options for debuggingVineet Gupta1-3/+3
This was helpful when debugging the recent multilib testsuite failure. gcc/testsuite: * lib/torture-options.exp: print the value of non-empty options: torture_without_loops, torture_with_loops, LTO_TORTURE_OPTIONS. Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
2023-06-01testsuite: Unbork multilib setups using -march flags (RISC-V)Vineet Gupta1-7/+7
RISC-V multilib testing is currently busted with follow splat all over: | Schedule of variations: | riscv-sim/-march=rv64imafdc/-mabi=lp64d/-mcmodel=medlow | riscv-sim/-march=rv32imafdc/-mabi=ilp32d/-mcmodel=medlow | riscv-sim/-march=rv32imac/-mabi=ilp32/-mcmodel=medlow | riscv-sim/-march=rv64imac/-mabi=lp64/-mcmodel=medlow ... ... | ERROR: tcl error code NONE | ERROR: torture-init: torture_without_loops is not empty as expected causing insane amount of false failures. | ========= Summary of gcc testsuite ========= | | # of unexpected case / # of unique unexpected case | | gcc | g++ | gfortran | | rv64imafdc/ lp64d/ medlow | 5421 / 4 | 1 / 1 | 6 / 1 | | rv32imafdc/ ilp32d/ medlow | 5422 / 5 | 3 / 2 | 6 / 1 | | rv32imac/ ilp32/ medlow | 391 / 5 | 3 / 2 | 43 / 8 | | rv64imac/ lp64/ medlow | 5422 / 5 | 1 / 1 | 43 / 8 | The error splat itself is from recent test harness improvements for stricter checks for torture-{init,finish} pairing. But the real issue is a latent bug from 2009: commit 3dd1415dc88, ("i386-prefetch.exp: Skip tests when multilib flags contain -march") which added an "early exit" condition to i386-prefetch.exp which could potentially cause an unpaired torture-{init,finish}. The early exit only happens in a multlib setup using -march in flags which is what RISC-V happens to use, hence the reason this was only seen on RISC-V multilib testing. Moving the early exit outside of torture-{init,finish} bracket reinstates RISC-V testing. | rv64imafdc/ lp64d/ medlow | 3 / 2 | 1 / 1 | 6 / 1 | | rv32imafdc/ ilp32d/ medlow | 4 / 3 | 3 / 2 | 6 / 1 | | rv32imac/ ilp32/ medlow | 3 / 2 | 3 / 2 | 43 / 8 | | rv64imac/ lp64/ medlow | 5 / 4 | 1 / 1 | 43 / 8 | gcc/testsuite: * gcc.misc-tests/i386-prefetch.exp: Move early return outside the torture-{init,finish} Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
2023-06-01doc: improve docs for -pedantic{,-errors}Jason Merrill1-18/+80
Recent discussion of -Wimplicit led me to want to clarify this section of the documentation, and mark which diagnostics other than -Wpedantic are affected by -pedantic-errors. gcc/ChangeLog: * doc/invoke.texi (-Wpedantic): Improve clarity.
2023-06-01testsuite: Skip powerpc tests on AIX.David Edelsohn2-1/+2
AIX does not support -mstrict-align. pr109566.c had skip directive in wrong order for DejaGNU. * gcc.target/powerpc/pr100106-sa.c: Skip on AIX. * gcc.target/powerpc/pr109566.c: Skip on AIX. Signed-off-by: David Edelsohn <dje.gcc@gmail.com>
2023-06-01cse: Change return type of predicate functions from int to boolUros Bizjak2-83/+77
Also change some function arguments to bool and remove one instance of always zero function argument. gcc/ChangeLog: * rtl.h (exp_equiv_p): Change return type from int to bool. * cse.cc (mention_regs): Change return type from int to bool and adjust function body accordingly. (exp_equiv_p): Ditto. (insert_regs): Ditto. Change "modified" function argument to bool and update usage accordingly. (record_jump_cond): Remove always zero "reversed_nonequality" function argument and update usage accordingly. (fold_rtx): Change "changed" variable to bool. (record_jump_equiv): Remove unneeded "reversed_nonequality" variable. (is_dead_reg): Change return type from int to bool.
2023-06-01xtensa: Add 'adddi3' and 'subdi3' insn patternsTakayuki 'January June' Suwa1-0/+52
More optimized than the default RTL generation. gcc/ChangeLog: * config/xtensa/xtensa.md (adddi3, subdi3): New RTL generation patterns implemented according to the instruc- tion idioms described in the Xtensa ISA reference manual (p. 600).
2023-06-01PR target/109973: CCZmode and CCCmode variants of [v]ptest on x86.Roger Sayle8-28/+102
This is my proposed minimal fix for PR target/109973 (hopefully suitable for backporting) that follows Jakub Jelinek's suggestion that we introduce CCZmode and CCCmode variants of ptest and vptest, so that the i386 backend treats [v]ptest instructions similarly to testl instructions; using different CCmodes to indicate which condition flags are desired, and then relying on the RTL cmpelim pass to eliminate redundant tests. This conveniently matches Intel's intrinsics, that provide different functions for retrieving different flags, _mm_testz_si128 tests the Z flag, _mm_testc_si128 tests the carry flag. Currently we use the same instruction (pattern) for both, and unfortunately the *ptest<mode>_and optimization is only valid when the ptest/vptest instruction is used to set/test the Z flag. The downside, as predicted by Jakub, is that GCC's cmpelim pass is currently COMPARE-centric and not able to merge the ptests from expressions such as _mm256_testc_si256 (a, b) + _mm256_testz_si256 (a, b), which is a known issue, PR target/80040. 2023-06-01 Roger Sayle <roger@nextmovesoftware.com> Uros Bizjak <ubizjak@gmail.com> gcc/ChangeLog PR target/109973 * config/i386/i386-builtin.def (__builtin_ia32_ptestz128): Use new CODE_for_sse4_1_ptestzv2di. (__builtin_ia32_ptestc128): Use new CODE_for_sse4_1_ptestcv2di. (__builtin_ia32_ptestz256): Use new CODE_for_avx_ptestzv4di. (__builtin_ia32_ptestc256): Use new CODE_for_avx_ptestcv4di. * config/i386/i386-expand.cc (ix86_expand_branch): Use CCZmode when expanding UNSPEC_PTEST to compare against zero. * config/i386/i386-features.cc (scalar_chain::convert_compare): Likewise generate CCZmode UNSPEC_PTESTs when converting comparisons. (general_scalar_chain::convert_insn): Use CCZmode for COMPARE result. (timode_scalar_chain::convert_insn): Use CCZmode for COMPARE result. * config/i386/i386-protos.h (ix86_match_ptest_ccmode): Prototype. * config/i386/i386.cc (ix86_match_ptest_ccmode): New predicate to check for suitable matching modes for the UNSPEC_PTEST pattern. * config/i386/sse.md (define_split): When splitting UNSPEC_MOVMSK to UNSPEC_PTEST, preserve the FLAG_REG mode as CCZ. (*<sse4_1>_ptest<mode>): Add asterisk to hide define_insn. Remove ":CC" mode of FLAGS_REG, instead use ix86_match_ptest_ccmode. (<sse4_1>_ptestz<mode>): New define_expand to specify CCZ. (<sse4_1>_ptestc<mode>): New define_expand to specify CCC. (<sse4_1>_ptest<mode>): A define_expand using CC to preserve the current behavior. (*ptest<mode>_and): Specify CCZ to only perform this optimization when only the Z flag is required. gcc/testsuite/ChangeLog PR target/109973 * gcc.target/i386/pr109973-1.c: New test case. * gcc.target/i386/pr109973-2.c: Likewise.
2023-06-01doc: Fix description of x86 -m32 option [PR109954]Jonathan Wakely1-1/+1
This option does not imply -march=i386 so it's incorrect to say it generates code that will run on "any i386 system". gcc/ChangeLog: PR target/109954 * doc/invoke.texi (x86 Options): Fix description of -m32 option.
2023-06-01aarch64: Add =r,m and =m,r alternatives to 64-bit vector move patternsKyrylo Tkachov2-17/+65
We can use the X registers to load and store 64-bit vector modes, we just need to add the alternatives to the mov patterns. This straightforward patch does that and for the pair variants too. For the testcase in the code we now generate the optimal assembly without any superfluous GP<->SIMD moves. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>): Add =r,m and =r,m alternatives. (load_pair<DREG:mode><DREG2:mode>): Likewise. (vec_store_pair<DREG:mode><DREG2:mode>): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/xreg-vec-modes_1.c: New test.
2023-06-01OpenMP/Fortran: Permit pure directives inside PURETobias Burnus8-29/+276
Update permitted directives for directives marked in OpenMP's 5.2 as pure. To ensure that list is updated, unimplemented directives are placed into pure-2.f90 such the test FAILs once a known to be pure directive is implemented without handling its pureness. gcc/fortran/ChangeLog: * parse.cc (decode_omp_directive): Accept all pure directives inside a PURE procedures; handle 'error at(execution). libgomp/ChangeLog: * libgomp.texi (OpenMP 5.2): Mark pure-directive handling as 'Y'. gcc/testsuite/ChangeLog: * gfortran.dg/gomp/nothing-2.f90: Remove one dg-error. * gfortran.dg/gomp/pr79154-2.f90: Update expected dg-error wording. * gfortran.dg/gomp/pr79154-simd.f90: Likewise. * gfortran.dg/gomp/pure-1.f90: New test. * gfortran.dg/gomp/pure-2.f90: New test. * gfortran.dg/gomp/pure-3.f90: New test. * gfortran.dg/gomp/pure-4.f90: New test.
2023-06-01RISC-V: Introduce vfloat16m{f}*_t and their machine mode.Pan Li7-10/+49
This patch would like to introduce the built-in type vfloat16m{f}*_t, as well as their machine mode VNx*HF. They depend on architecture zvfhmin or zvfh. When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will be true. The underlying PATCH will implement the zvfhmin extension based on this. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin and zvfh. * config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16. (main): Disable FP16 tuple. * config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro. (TARGET_VECTOR_ELEN_FP_16): Ditto. * config/riscv/riscv-vector-builtins.cc (check_required_extensions): Add FP16. * config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type. (vfloat16mf2_t): Ditto. (vfloat16m1_t): Ditto. (vfloat16m2_t): Ditto. (vfloat16m4_t): Ditto. (vfloat16m8_t): Ditto. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16): New macro. * config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16 machine mode based on TARGET_VECTOR_ELEN_FP_16.
2023-05-31c++: make -fpermissive avoid -Werror=narrowingJason Merrill1-1/+2
Currently we make -Wnarrowing an error by default by forcing pedantic_errors on, but for consistency -fpermissive should prevent that. In general I'm inclined to move away from using permerror in favor of this kind of model, with specific flags for each diagnostic. gcc/cp/ChangeLog: * typeck2.cc (check_narrowing): Check flag_permissive.
2023-06-01Daily bump.GCC Administrator3-1/+316
2023-06-01RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscsJuzhe-Zhong3-0/+61
gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (register_frm): New function. (DEF_RVV_FRM_ENUM): New macro. (handle_pragma_vector): Add FRM enum * config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro. (RNE): Ditto. (RTZ): Ditto. (RDN): Ditto. (RUP): Ditto. (RMM): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/frm-1.c: New test.
2023-05-31Refactor wi::bswap as a function (instead of a method).Roger Sayle5-24/+36
This patch implements Richard Sandiford's suggestion from https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618215.html that wi::bswap (and a new wi::bitreverse) should be functions, and ideally only accessors are member functions. This patch implements the first step, moving/refactoring wi::bswap. 2023-05-31 Roger Sayle <roger@nextmovesoftware.com> Richard Sandiford <richard.sandiford@arm.com> gcc/ChangeLog * fold-const-call.cc (fold_const_call_ss) <CFN_BUILT_IN_BSWAP*>: Update call to wi::bswap. * simplify-rtx.cc (simplify_const_unary_operation) <case BSWAP>: Update call to wi::bswap. * tree-ssa-ccp.cc (evaluate_stmt) <case BUILT_IN_BSWAP*>: Update calls to wi::bswap. * wide-int.cc (wide_int_storage::bswap): Remove/rename to... (wi::bswap_large): New function, with revised API. * wide-int.h (wi::bswap): New (template) function prototype. (wide_int_storage::bswap): Remove method. (sext_large, zext_large): Consistent indentation/line wrapping. (bswap_large): Prototype helper function containing implementation. (wi::bswap): New template wrapper around bswap_large.
2023-05-31testsuite: rename force_conventional_outputBernhard Reutner-Fischer4-15/+15
The procedure force_conventional_output_for is a bit misnomed, what it primarily does is to set the required options for the corresponding test. So rename the proc to set_required_options_for and also rename the participating variable accordingly. gcc/testsuite/ChangeLog: * lib/gcc-dg.exp: Rename gcc_force_conventional_output to gcc_set_required_options. * lib/target-supports.exp: Rename force_conventional_output_for to set_required_options_for. * lib/scanasm.exp: Adjust callers. * lib/scanrtl.exp: Same.
2023-05-31aarch64: PR target/99195 Annotate dot-product patterns for vec-concat-zeroKyrylo Tkachov2-5/+43
This straightforward patch annotates the dotproduct instructions, including the i8mm ones. Tests included. Nothing unexpected here. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (<sur>dot_prod<vsi2qi>): Rename to... (<sur>dot_prod<vsi2qi><vczle><vczbe>): ... This. (usdot_prod<vsi2qi>): Rename to... (usdot_prod<vsi2qi><vczle><vczbe>): ... This. (aarch64_<sur>dot_lane<vsi2qi>): Rename to... (aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>): ... This. (aarch64_<sur>dot_laneq<vsi2qi>): Rename to... (aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>): ... This. (aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi>): Rename to... (aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_11.c: New test.
2023-05-31aarch64: PR target/99195 Annotate saturating mult patterns for vec-concat-zeroKyrylo Tkachov3-11/+54
This patch goes through the various alphabet soup saturating multiplication patterns, including those in TARGET_RDMA and annotates them with <vczle><vczbe>. Many other patterns are widening and always write the full 128-bit vectors so this annotation doesn't apply to them. Nothing out of the ordinary in this patch. Bootstrapped and tested on aarch64-none-linux and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh<mode>): Rename to... (aarch64_sq<r>dmulh<mode><vczle><vczbe>): ... This. (aarch64_sq<r>dmulh_n<mode>): Rename to... (aarch64_sq<r>dmulh_n<mode><vczle><vczbe>): ... This. (aarch64_sq<r>dmulh_lane<mode>): Rename to... (aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>): ... This. (aarch64_sq<r>dmulh_laneq<mode>): Rename to... (aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>): ... This. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): Rename to... (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode><vczle><vczbe>): ... This. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Rename to... (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>): ... This. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Rename to... (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add tests for qdmulh, qrdmulh. * gcc.target/aarch64/simd/pr99195_10.c: New test.
2023-05-31btf: improve -dA comments for testsuiteDavid Faust17-69/+224
Many BTF type kinds refer to other types via index to the final types list. However, the order of the final types list is not guaranteed to remain the same for the same source program between different runs of the compiler, making it difficult to test inter-type references. This patch updates the assembler comments output when writing a given BTF record to include minimal information about the referenced type, if any. This allows for the regular expressions used in the gcc testsuite to do some basic integrity checks on inter-type references. For example, for the type unsigned int * Assembly comments like the following are written with -dA: .4byte 0 ; TYPE 2 BTF_KIND_PTR '' .4byte 0x2000000 ; btt_info: kind=2, kflag=0, vlen=0 .4byte 0x1 ; btt_type: (BTF_KIND_INT 'unsigned int') Several BTF tests which can immediately be made more robust with this change are updated. It will also be useful in new tests for the upcoming btf_type_tag support. gcc/ * btfout.cc (btf_kind_names): New. (btf_kind_name): New. (btf_absolute_var_id): New utility function. (btf_relative_var_id): Likewise. (btf_relative_func_id): Likewise. (btf_absolute_datasec_id): Likewise. (btf_asm_type_ref): New. (btf_asm_type): Update asm comments and use btf_asm_type_ref (). (btf_asm_array): Likewise. Accept ctf_container_ref parameter. (btf_asm_varent): Likewise. (btf_asm_func_arg): Likewise. (btf_asm_datasec_entry): Likewise. (btf_asm_datasec_type): Likewise. (btf_asm_func_type): Likewise. Add index parameter. (btf_asm_enum_const): Likewise. (btf_asm_sou_member): Likewise. (output_btf_vars): Update btf_asm_* call accordingly. (output_asm_btf_sou_fields): Likewise. (output_asm_btf_enum_list): Likewise. (output_asm_btf_func_args_list): Likewise. (output_asm_btf_vlen_bytes): Likewise. (output_btf_func_types): Add ctf_container_ref parameter. Pass it to btf_asm_func_type. (output_btf_datasec_types): Update btf_asm_datsec_type call similarly. (btf_output): Update output_btf_func_types call similarly. gcc/testsuite/ * gcc.dg/debug/btf/btf-array-1.c: Use new BTF asm comments in scan-assembler expressions where useful. * gcc.dg/debug/btf/btf-anonymous-struct-1.c: Likewise. * gcc.dg/debug/btf/btf-anonymous-union-1.c: Likewise. * gcc.dg/debug/btf/btf-bitfields-2.c: Likewise. * gcc.dg/debug/btf/btf-bitfields-3.c: Likewise. * gcc.dg/debug/btf/btf-datasec-2.c: Likewise. * gcc.dg/debug/btf/btf-enum-1.c: Likewise. * gcc.dg/debug/btf/btf-function-6.c: Likewise. * gcc.dg/debug/btf/btf-pointers-1.c: Likewise. * gcc.dg/debug/btf/btf-struct-1.c: Likewise. * gcc.dg/debug/btf/btf-struct-2.c: Likewise. * gcc.dg/debug/btf/btf-typedef-1.c: Likewise. * gcc.dg/debug/btf/btf-union-1.c: Likewise. * gcc.dg/debug/btf/btf-variables-1.c: Likewise. * gcc.dg/debug/btf/btf-variables-2.c: Likewise. Update outdated comment. * gcc.dg/debug/btf/btf-function-3.c: Update outdated comment.
2023-05-31btf: be clear when record size/type is not usedDavid Faust1-0/+6
All BTF type records have a 4-byte field used to encode a size or link to another type, depending on the type kind. But BTF_KIND_ARRAY and BTF_KIND_FWD do not use this field at all, and should write zero. GCC already correctly writes zero in this field for these type kinds, but the process is not straightforward and results in the -dA comment claiming the field is a reference to another type. This patch makes the behavior explicit and updates the assembler comment to state clearly that the field is unused. gcc/ * btfout.cc (btf_asm_type): Add dedicated cases for BTF_KIND_ARRAY and BTF_KIND_FWD which do not use the size/type field at all.
2023-05-31emit-rtl: Change return type of predicate functions from int to boolUros Bizjak3-36/+32
Also fix some stalled comments. gcc/ChangeLog: * rtl.h (subreg_lowpart_p): Change return type from int to bool. (active_insn_p): Ditto. (in_sequence_p): Ditto. (unshare_all_rtl): Change return type from int to void. * emit-rtl.h (mem_expr_equal_p): Change return type from int to bool. * emit-rtl.cc (subreg_lowpart_p): Change return type from int to bool and adjust function body accordingly. (mem_expr_equal_p): Ditto. (unshare_all_rtl): Change return type from int to void and adjust function body accordingly. (verify_rtx_sharing): Remove unneeded return. (active_insn_p): Change return type from int to bool and adjust function body accordingly. (in_sequence_p): Ditto.
2023-05-31alias: Change return type of predicate functions from int to boolUros Bizjak3-135/+122
Also remove a bunch of unneeded forward declarations. gcc/ChangeLog: * rtl.h (true_dependence): Change return type from int to bool. (canon_true_dependence): Ditto. (read_dependence): Ditto. (anti_dependence): Ditto. (canon_anti_dependence): Ditto. (output_dependence): Ditto. (canon_output_dependence): Ditto. (may_alias_p): Ditto. * alias.h (alias_sets_conflict_p): Ditto. (alias_sets_must_conflict_p): Ditto. (objects_must_conflict_p): Ditto. (nonoverlapping_memrefs_p): Ditto. * alias.cc (rtx_equal_for_memref_p): Remove forward declaration. (record_set): Ditto. (base_alias_check): Ditto. (find_base_value): Ditto. (mems_in_disjoint_alias_sets_p): Ditto. (get_alias_set_entry): Ditto. (decl_for_component_ref): Ditto. (write_dependence_p): Ditto. (memory_modified_1): Ditto. (mems_in_disjoint_alias_set_p): Change return type from int to bool and adjust function body accordingly. (alias_sets_conflict_p): Ditto. (alias_sets_must_conflict_p): Ditto. (objects_must_conflict_p): Ditto. (rtx_equal_for_memref_p): Ditto. (base_alias_check): Ditto. (read_dependence): Ditto. (nonoverlapping_memrefs_p): Ditto. (true_dependence_1): Ditto. (true_dependence): Ditto. (canon_true_dependence): Ditto. (write_dependence_p): Ditto. (anti_dependence): Ditto. (canon_anti_dependence): Ditto. (output_dependence): Ditto. (canon_output_dependence): Ditto. (may_alias_p): Ditto. (init_alias_analysis): Change "changed" variable to bool.
2023-05-31RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for ↵Juzhe-Zhong10-4/+262
RVV auto-vectorization Base on V1 patch, adding comment: ;; Use define_insn_and_split to define vsext.vf2/vzext.vf2 will help combine PASS ;; to combine instructions as below: ;; vsext.vf2 + vsext.vf2 + vadd.vv ==> vwadd.vv gcc/ChangeLog: * config/riscv/autovec.md (<optab><v_double_trunc><mode>2): Change expand into define_insn_and_split. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: * gcc.target/riscv/rvv/autovec/widen/widen-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-3.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-4.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: New test.
2023-05-31RISC-V: Add testcase for vrsub.vi auto-vectorizationJuzhe-Zhong4-1/+59
Apparently, we are missing vrsub.vi tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto. Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
2023-05-31RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)Juzhe-Zhong1-3/+1
Base on the discussion here: https://github.com/riscv/riscv-v-spec/issues/884 vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening ↵Juzhe-Zhong1-3/+1
conversion) Base on the discussion here: https://github.com/riscv/riscv-v-spec/issues/884 vfwcvt.f.x<u>.v doesn't depend on FRM. So remove FRM preparing for mode switching support. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31RISC-V: Remove FRM for vfncvt.rod instructionJuzhe-Zhong1-3/+1
Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31aarch64: Add pattern for bswap + rotate [PR 110039]Christophe Lyon1-0/+10
After commit g:d8545fb2c71683f407bfd96706103297d4d6e27b, we missed a pattern to match the new GIMPLE form. With this patch, gcc.target/aarch64/rev16_2.c passes again. 2023-05-31 Christophe Lyon <christophe.lyon@linaro.org> PR target/110039 gcc/ * config/aarch64/aarch64.md (aarch64_rev16si2_alt3): New pattern.
2023-05-31ipa/109983 - (IPA) PTA speedupRichard Biener1-72/+46
This improves the edge avoidance heuristic by re-ordering the topological sort of the graph to make sure the component with the ESCAPED node is processed first. This improves the number of created edges which directly correlates with the number of bitmap_ior_into calls from 141447426 to 239596 and the compile-time from 1083s to 3s. It also improves the compile-time for the related PR109143 from 81s to 27s. I've modernized the topological sorting API on the way as well. PR ipa/109983 PR tree-optimization/109143 * tree-ssa-structalias.cc (struct topo_info): Remove. (init_topo_info): Likewise. (free_topo_info): Likewise. (compute_topo_order): Simplify API, put the component with ESCAPED last so it's processed first. (topo_visit): Adjust. (solve_graph): Likewise.
2023-05-31IPA PTA stats enhancement and non-details dump slimmingRichard Biener1-2/+8
The following keeps track of the number of edges we avoid to create because they redundandly feed ESCAPED. It also avoids printing a header for -details when not using -details. * tree-ssa-structalias.cc (constraint_stats::num_avoided_edges): New. (add_graph_edge): Count redundant edges we avoid to create. (dump_sa_stats): Dump them. (ipa_pta_execute): Do not dump generating constraints when we are not dumping them.
2023-05-31aarch64: Simplify output template emission code for a few patternsKyrylo Tkachov2-99/+40
If the output code for a define_insn just does a switch (which_alternative) with no other computation we can almost always replace it with more compact MD syntax for each alternative in a mult-alternative '@' block. This patch cleans up some such patterns in the aarch64 backend, making them shorter and more concise. No behavioural change intended. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>): Rewrite output template to avoid explicit switch on which_alternative. (*aarch64_simd_mov<VQMOV:mode>): Likewise. (and<mode>3): Likewise. (ior<mode>3): Likewise. * config/aarch64/aarch64.md (*mov<mode>_aarch64): Likewise.
2023-05-31xtensa: Improve "*shlrd_reg" insn pattern and its variantTakayuki 'January June' Suwa2-26/+58
The insn "*shlrd_reg" shifts two registers with a funnel shifter by the third register to get a single word result: reg0 = (reg1 SHIFT_OP0 reg3) BIT_JOIN_OP (reg2 SHIFT_OP1 (32 - reg3)) where the funnel left shift is SHIFT_OP0 := ASHIFT, SHIFT_OP1 := LSHIFTRT and its right shift is SHIFT_OP0 := LSHIFTRT, SHIFT_OP1 := ASHIFT, respectively. And also, BIT_JOIN_OP can be either PLUS or IOR in either shift direction. [(set (match_operand:SI 0 "register_operand" "=a") (match_operator:SI 6 "xtensa_bit_join_operator" [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 3 "register_operand" "r")]) (match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 2 "register_operand" "r") (neg:SI (match_dup 3))])]))] Although the RTL matching template can express it as above, there is no way of direcing that the operator (operands[6]) that combines the two individual shifts is commutative. Thus, if multiple insn sequences matching the above pattern appear adjacently, the combiner may accidentally mix them up and get partial results. This patch adds a new insn-and-split pattern with the two sides swapped representation of the bit-combining operation that was lacking and described above. And also changes the other "*shlrd" variants from previously describing the arbitraryness of bit-combining operations with code iterators to a combination of the match_operator and the predicate above. gcc/ChangeLog: * config/xtensa/predicates.md (xtensa_bit_join_operator): New predicate. * config/xtensa/xtensa.md (ior_op): Remove. (*shlrd_reg): Rename from "*shlrd_reg_<code>", and add the insn_and_split pattern of the same name to express and capture the bit-combining operation with both sides swapped. In addition, replace use of code iterator with new operator predicate. (*shlrd_const, *shlrd_per_byte): Likewise regarding the code iterator.
2023-05-31Fix ICE in rewrite_expr_tree_parallelCui, Lili3-1/+15
1. Limit the value of tree-reassoc-width to IntegerRange(0, 256). 2. Add width limit in rewrite_expr_tree_parallel. gcc/ChangeLog: PR tree-optimization/110038 * params.opt: Add a limit on tree-reassoc-width. * tree-ssa-reassoc.cc (rewrite_expr_tree_parallel): Add width limit. gcc/testsuite/ChangeLog: PR tree-optimization/110038 * gcc.dg/pr110038.c: New test.
2023-05-31RISC-V: Add ZVFH extension to the -march= optionPan Li4-0/+66
This patch would like to add new sub extension (aka ZVFH) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFH. The Zvfh extension depends on the Zve32f and Zfhmin extensions. You can locate more information about ZVFH from below spec doc. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh-vector-extension-for-half-precision-floating-point Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfh item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZVFH): New macro. (TARGET_ZVFH): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-21.c: New test. * gcc.target/riscv/predef-27.c: New test.
2023-05-31RISC-V: Fix unreachable test code for init repeat sequence.Pan Li1-1/+0
This patch fix one unreachable test code, which is for debugging purpose without cleanup before commit. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Remove debug code. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31Daily bump.GCC Administrator6-1/+554
2023-05-31Enhance NARROW FLOAT_EXPR vectorization by truncating integer to lower ↵liuhongt4-32/+121
precision. Similar like WIDEN FLOAT_EXPR, when direct_optab is not existed, try intermediate integer type whenever gimple ranger can tell it's safe. .i.e. When there's no direct optab for vector long long -> vector float, but the value range of integer can be represented as int, try vector int -> vector float if availble. gcc/ChangeLog: PR tree-optimization/108804 * tree-vect-patterns.cc (vect_get_range_info): Remove static. * tree-vect-stmts.cc (vect_create_vectorized_demotion_stmts): Add new parameter narrow_src_p. (vectorizable_conversion): Enhance NARROW FLOAT_EXPR vectorization by truncating to lower precision. * tree-vectorizer.h (vect_get_range_info): New declare. gcc/testsuite/ChangeLog: * gcc.target/i386/pr108804.c: New test.
2023-05-30testsuite: add verify-sarif-file to some testcases that were missing itDavid Malcolm2-0/+3
gcc/testsuite/ChangeLog: * gcc.dg/analyzer/malloc-sarif-1.c: Add missing verify-sarif-file directive. * gcc.dg/analyzer/sarif-pr107366.c: Likewise. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-05-30testsuite/52641: Fix more of implicit int=32 assumption fallout.Georg-Johann Lay7-3/+13
gcc/testsuite/ PR testsuite/52641 * gcc.dg/torture/pr107451.c: Require int32plus. * gcc.dg/torture/pr108574-3.c: Use __INT32_TYPE__ instead of int. * gcc.dg/torture/pr109940.c: Use __INTPTR_TYPE__ instead of long. * gcc.dg/torture/pr95248.c: Require size24plus. * gcc.dg/torture/pr95295-3.c: Use var_* with at least 32 bits int. * gcc.dg/torture/pr98640.c: Cast to __INT32_TYPE__ instead of int. * gcc.dg/tree-ssa/pr103771.c: Use int with at least 32 bits.
2023-05-30LRA: Update insn sp offset if its input reload changes SPVladimir N. Makarov3-4/+36
The patch fixes a bug when there is input reload changing SP. The bug was triggered by switching H8300 target to LRA. The insn in question is (insn 21 20 22 2 (set (mem/f:SI (pre_dec:SI (reg/f:SI 7 sp)) [3 S4 A32]) (reg/f:SI 31)) "j.c":10:3 19 {*movsi} (expr_list:REG_DEAD (reg/f:SI 31) (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) (nil)))) The memory address is reloaded but the SP offset for the original insn was not updated. gcc/ChangeLog: * lra-int.h (lra_update_sp_offset): Add the prototype. * lra.cc (setup_sp_offset): Change the return type. Use lra_update_sp_offset. * lra-eliminations.cc (lra_update_sp_offset): New function. (lra_process_new_insns): Push the current insn to reprocess if the input reload changes sp offset.
2023-05-30i386: Fix misleading identation in i386-expand.cc [PR110041]Uros Bizjak1-12/+12
gcc/ChangeLog: PR target/110041 * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Fix misleading identation.
2023-05-30jump: Change return type of predicate functions from int to boolUros Bizjak2-107/+107
gcc/ChangeLog: * rtl.h (comparison_dominates_p): Change return type from int to bool. (condjump_p): Ditto. (any_condjump_p): Ditto. (any_uncondjump_p): Ditto. (simplejump_p): Ditto. (returnjump_p): Ditto. (eh_returnjump_p): Ditto. (onlyjump_p): Ditto. (invert_jump_1): Ditto. (invert_jump): Ditto. (rtx_renumbered_equal_p): Ditto. (redirect_jump_1): Ditto. (redirect_jump): Ditto. (condjump_in_parallel_p): Ditto. * jump.cc (invert_exp_1): Adjust forward declaration. (comparison_dominates_p): Change return type from int to bool and adjust function body accordingly. (simplejump_p): Ditto. (condjump_p): Ditto. (condjump_in_parallel_p): Ditto. (any_uncondjump_p): Ditto. (any_condjump_p): Ditto. (returnjump_p): Ditto. (eh_returnjump_p): Ditto. (onlyjump_p): Ditto. (redirect_jump_1): Ditto. (redirect_jump): Ditto. (invert_exp_1): Ditto. (invert_jump_1): Ditto. (invert_jump): Ditto. (rtx_renumbered_equal_p): Ditto.
2023-05-30testsuite: make mve_intrinsic_type_overloads-int.c libc-agnosticChristophe Lyon1-13/+15
Glibc defines int32_t as 'int' while newlib defines it as 'long int'. Although these correspond to the same size, g++ complains when using the 'wrong' version: invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive] or invalid conversion from 'int*' to 'int32_t*' {aka 'long int*'} [-fpermissive] when calling vst1q(int32*, int32x4_t) with a first parameter of type 'long int *' (resp. 'int *') To make this test pass with any type of toolchain, this patch defines 'word_type' according to which libc is in use. 2023-05-23 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Support both definitions of int32_t.
2023-05-30Add a != MIN/MAX_VALUE_CST ? CST-+1 : a to minmax_from_comparisonAndrew Pinski3-2/+40
This patch adds the support for match that was implemented for PR 87913 in phiopt. It implements it by adding support to minmax_from_comparison for the check. It uses the range information if available which allows to produce MIN/MAX expression when comparing against the lower/upper bound of the range instead of lower/upper of the type. minmax-20.c is the new testcase which tests the ranges part. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * fold-const.cc (minmax_from_comparison): Add support for NE_EXPR. * match.pd ((cond (cmp (convert1? x) c1) (convert2? x) c2) pattern): Add ne as a possible cmp. ((a CMP b) ? minmax<a, c> : minmax<b, c> pattern): Likewise. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/minmax-22.c: New test.
2023-05-30MATCH: Move `a <= CST1 ? MAX<a, CST2> : a` optimization to matchAndrew Pinski5-2/+68
This moves the `a <= CST1 ? MAX<a, CST2> : a` optimization from phiopt to match. It just adds a new pattern to match.pd. There is one more change needed before being able to remove minmax_replacement from phiopt. A few notes on the testsuite changes: * phi-opt-5.c is now able to optimize at phiopt1 so remove the xfail. * pr66726-4.c can be optimized during fold before phiopt1 so need to change the scanning. * pr66726-5.c needs two phiopt passes currently to optimize to the right thing, it needed 2 phiopt passes before, the cast from int to unsigned char is the reason. * pr66726-6.c is what the original pr66726-4.c was testing before the fold was able to optimize it. OK? Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * match.pd (`(a CMP CST1) ? max<a,CST2> : a`): New pattern. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/phi-opt-5.c: Remove last xfail. * gcc.dg/tree-ssa/pr66726-4.c: Change how scanning works. * gcc.dg/tree-ssa/pr66726-5.c: New test. * gcc.dg/tree-ssa/pr66726-6.c: New test.
2023-05-30Fix ACLE data-intrinsics testcasesChristophe Lyon2-1/+2
data-intrinsics-assembly.c forces -march=armv6 using dg-add-options arm_arch_v6, which implicitly adds -mfloat-abi=softfp. However, for a toolchain configured for arm-linux-gnueabihf and --with-arch=armv7-a, the testcase will fail when including arm_acle.h (which includes stdint.h, which will fail to include the non-existing gnu/stubs-soft.h). Other effective-targets related to arm_acle.h would also pass because they first try without -mfloat-abi=softfp, so it seems the simplest/safest is to add { dg-require-effective-target arm_softfp_ok } to make sure arm_arch_v6_ok's assumption is valid. The patch also fixes what seems to be an oversight in data-intrinsics-armv6.c: it requires arm_arch_v6_ok, but uses arm_arch_v6t2: the patch makes it require arm_arch_v6t2_ok. 2023-05-30 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/arm/acle/data-intrinsics-armv6.c: Fix typo. * gcc.target/arm/acle/data-intrinsics-assembly.c: Require arm_softfp_ok.
2023-05-30Replace a HWI_COMPUTABLE_MODE_P with wide-int in simplify-rtx.cc.Roger Sayle1-7/+8
This patch enhances one of the optimizations in simplify_binary_operation_1 to allow it to simplify RTL expressions in modes wider than HOST_WIDE_INT by replacing a use of HWI_COMPUTABLE_MODE_P and UINTVAL with wide_int. The motivating example is a pending x86_64 backend patch that produces the following RTL in combine: (and:TI (zero_extend:TI (reg:DI 89)) (const_wide_int 0x0ffffffffffffffff)) where the AND is redundant, as the mask, ~0LL, is DImode's MODE_MASK. There's already an optimization that catches this for narrower modes, transforming (and:HI (zero_extend:HI (reg:QI x)) (const_int 0xff)) into (zero_extend:HI (reg:QI x)), but this currently only handles CONST_INT not CONST_WIDE_INT. Fixed by upgrading this transformation to use wide_int, specifically rtx_mode_t and wi::mask. 2023-05-30 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * simplify-rtx.cc (simplify_binary_operation_1) <AND>: Use wide-int instead of HWI_COMPUTABLE_MODE_P and UINTVAL in transformation of (and (extend X) C) as (zero_extend (and X C)), to also optimize modes wider than HOST_WIDE_INT.
2023-05-30PR target/107172: Avoid "unusual" MODE_CC comparisons in simplify-rtx.ccRoger Sayle1-0/+6
I believe that a better (or supplementary) fix to PR target/107172 is to avoid producing incorrect (but valid) RTL in simplify_const_relational_operation when presented with questionable (obviously invalid) expressions, such as those produced during combine. Just as with the "first do no harm" clause with the Hippocratic Oath, simplify-rtx (probably) shouldn't unintentionally transform invalid RTL expressions, into incorrect (non-equivalent) but valid RTL that may be inappropriately recognized by recog. In this specific case, many GCC backends represent their flags register via MODE_CC, whose representation is intentionally "opaque" to the middle-end. The only use of MODE_CC comprehensible to the middle-end's RTL optimizers is relational comparisons between the result of a COMPARE rtx (op0) and zero (op1). Any other uses of MODE_CC should be left alone, and some might argue indicate representational issues in the backend. In practice, CPUs occasionally have numerous instructions that affect the flags register(s) other than comparisons [AVR's setc, powerpc's mtcrf, x86's clc, stc and cmc and x86_64's ptest that sets C and Z flags in non-obvious ways, c.f. PR target/109973]. Currently care has to be taken, wrapping these in UNSPEC, to avoid combine inappropriately merging flags setters with flags consumers (such as conditional jumps). It's safer to teach simplify_const_relational_operation not to modify expressions that it doesn't understand/recognize. 2023-05-30 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog PR target/107172 * simplify-rtx.cc (simplify_const_relational_operation): Return early if we have a MODE_CC comparison that isn't a COMPARE against const0_rtx.
2023-05-30OpenMP: Improve C/C++ parsing error message [PR109999]Tobias Burnus8-16/+16
Replace error: expected '#pragma omp' clause before ... by the the more readable/clearer error: expected an OpenMP clause before ... (And likewise for '#pragma acc' and OpenACC.) PR c/109999 gcc/c/ChangeLog: * c-parser.cc (c_parser_oacc_all_clauses, c_parser_omp_all_clauses): Improve error wording. gcc/cp/ChangeLog: * parser.cc (cp_parser_oacc_all_clauses, cp_parser_omp_all_clauses): Improve error wording. gcc/testsuite/ChangeLog: * c-c++-common/goacc/asyncwait-1.c: Update dg-error. * c-c++-common/goacc/clauses-fail.c: Likewise. * c-c++-common/goacc/data-2.c: Likewise. * c-c++-common/gomp/declare-target-2.c: Likewise. * c-c++-common/gomp/directive-1.c: Likewise. * g++.dg/goacc/data-1.C: Likewise.
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