aboutsummaryrefslogtreecommitdiff
path: root/gcc
AgeCommit message (Expand)AuthorFilesLines
2023-06-12Move operator_addr_expr to the unified range-op table.Andrew MacLeod2-18/+18
2023-06-12PR modula2/110126 variables are reported as unused when referenced by ASM fixGaius Mulley3-25/+73
2023-06-12RISC-V: Fix one potential test failure for RVV vsetvlPan Li1-1/+1
2023-06-12RISC-V: Support RVV FP16 MISC vget/vset intrinsic APIPan Li3-10/+40
2023-06-12Fix disambiguation against .MASK_STORERichard Biener1-0/+3
2023-06-12Remove DEFAULT_MATCHPD_PARTITIONS macroTamar Christina3-15/+2
2023-06-12RISC-V: Add RVV narrow shift right lowering auto-vectorizationJuzhe-Zhong8-14/+311
2023-06-12simplify-rtx: Implement constant folding of SS_TRUNCATE, US_TRUNCATEKyrylo Tkachov1-0/+14
2023-06-12RISC-V: Add ZVFHMIN block autovec testcaseJuzhe-Zhong1-0/+35
2023-06-12Fix oversight in latest changeEric Botcazou1-1/+1
2023-06-12Regenerate config.inTamar Christina1-2/+7
2023-06-12vect: Don't pass subtype to vect_widened_op_tree where not needed [PR 110142]Andre Vieira2-23/+13
2023-06-12Add missing vec_pack/unpacks patterns for _Float16 <-> int/float conversion.liuhongt4-9/+258
2023-06-12middle-end/110200 - genmatch force-leaf and convert interactionRichard Biener1-2/+4
2023-06-12c++: build initializer_list<string> in a loop [PR105838]Jason Merrill5-8/+48
2023-06-12rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]Kewen Lin3-7/+39
2023-06-12rs6000: Don't use TFmode for 128 bits fp constant in toc [PR110011]Kewen Lin2-1/+43
2023-06-12RISC-V: Add test cases for RVV FP16 undefined and vlmul truncPan Li2-16/+78
2023-06-12RISC-V: Support RVV FP16 MISC vlmul ext intrinsic APIPan Li3-8/+79
2023-06-11aix: Debugging does not require a stack frame.David Edelsohn1-3/+0
2023-06-12Daily bump.GCC Administrator4-1/+100
2023-06-11c++: unsynthesized defaulted constexpr fn [PR110122]Patrick Palka2-4/+33
2023-06-11c++: extend lookup_template_class shortcut [PR110122]Patrick Palka3-4/+60
2023-06-11Use canonical form for reversed single-bit insertions after reload.Georg-Johann Lay3-111/+41
2023-06-11target/19907: Overhaul bit extractions.Georg-Johann Lay8-114/+1064
2023-06-11RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASSJuzhe-Zhong8-153/+370
2023-06-11Daily bump.GCC Administrator6-1/+392
2023-06-10Convert ipcp_vr_lattice to type agnostic framework.Aldy Hernandez4-88/+101
2023-06-10c++: Adjust conversion deduction [PR61663][DR976]Nathan Sidwell2-5/+69
2023-06-10target/109650: Fix wrong code after cc0 -> CCmode transition.Georg-Johann Lay9-777/+1460
2023-06-10Fortran: add Fortran 2018 IEEE_{MIN,MAX} functionsFrancois-Xavier Coudert7-0/+1073
2023-06-10testsuite: Add more allocation size tests for conjured svalues [PR110014]Tim Lange1-0/+25
2023-06-10analyzer: Fix allocation size false positive on conjured svalue [PR109577]Tim Lange5-58/+194
2023-06-10RISC-V: Add test cases for RVV FP16 vreinterpretPan Li2-2/+50
2023-06-10RISC-V: Enable select_vl for RVV auto-vectorizationJuzhe-Zhong6-2/+55
2023-06-09Unify MULT_EXPR range operatorAndrew MacLeod4-236/+227
2023-06-09Unify NEGATE_EXPR range operatorAndrew MacLeod3-61/+63
2023-06-09Unify MINUS_EXPR range operatorAndrew MacLeod3-81/+93
2023-06-09Unify ABS_EXPR range operatorAndrew MacLeod3-36/+29
2023-06-09Unify PLUS_EXPR range operatorAndrew MacLeod3-80/+90
2023-06-09Unify operator_cast range operatorAndrew MacLeod2-30/+28
2023-06-09Unify operator_cst range operatorAndrew MacLeod3-13/+22
2023-06-09Unify Identity range operatorAndrew MacLeod3-49/+44
2023-06-09Unify GE_EXPR range operatorAndrew MacLeod4-74/+55
2023-06-09Unify GT_EXPR range operatorAndrew MacLeod4-70/+54
2023-06-09Unify LE_EXPR range operatorAndrew MacLeod4-69/+56
2023-06-09Unify LT_EXPR range operatorAndrew MacLeod4-69/+53
2023-06-09Unify NE_EXPR range operatorAndrew MacLeod4-59/+48
2023-06-09Unify EQ_EXPR range operatorAndrew MacLeod4-62/+62
2023-06-09Provide a unified range-op table.Andrew MacLeod4-100/+185