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2023-05-10Daily bump.GCC Administrator6-1/+1487
2023-05-09Update gcc hr.poJoseph Myers1-3/+3
* hr.po: Update.
2023-05-09c++: error-recovery ICE with unstable satisfaction [PR109752]Patrick Palka2-3/+36
After diagnosing and recovering from unstable satisfaction, it's possible to evaluate an atom for the first time noisily rather than quietly. The satisfaction cache tries to handle this situation gracefully, but apparently not gracefully enough: we inserted an empty slot into the cache, and left it empty, which later makes hash_table::check_complete_insertion unhappy. This patch fixes this by removing the empty slot in this case. PR c++/109752 gcc/cp/ChangeLog: * constraint.cc (satisfaction_cache::satisfaction_cache): In the unexpected case of evaluating an atom for the first time noisily, remove the cache slot that we inserted. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-pr109752.C: New test.
2023-05-09c++: noexcept-spec from nested class confusion [PR109761]Patrick Palka2-7/+22
When late processing a noexcept-spec from a nested class after completion of the outer class (since it's a complete-class context), we pass the wrong class context to noexcept_override_late_checks -- the outer class type instead of the nested class type -- which leads to bogus errors in the below test. This patch fixes this by making noexcept_override_late_checks obtain the class context directly via DECL_CONTEXT instead of via an additional parameter. PR c++/109761 gcc/cp/ChangeLog: * parser.cc (cp_parser_class_specifier): Don't pass a class context to noexcept_override_late_checks. (noexcept_override_late_checks): Remove 'type' parameter and use DECL_CONTEXT of 'fndecl' instead. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/noexcept78.C: New test.
2023-05-09arm: [MVE intrinsics] rework vmaxaq vminaqChristophe Lyon5-240/+8
Implement vmaxaq and vminaq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmaxaq, vminaq): New. * config/arm/arm-mve-builtins-base.def (vmaxaq, vminaq): New. * config/arm/arm-mve-builtins-base.h (vmaxaq, vminaq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmaxaq and vminaq. * config/arm/arm_mve.h (vminaq): Remove. (vmaxaq): Remove. (vminaq_m): Remove. (vmaxaq_m): Remove. (vminaq_s8): Remove. (vmaxaq_s8): Remove. (vminaq_s16): Remove. (vmaxaq_s16): Remove. (vminaq_s32): Remove. (vmaxaq_s32): Remove. (vminaq_m_s8): Remove. (vmaxaq_m_s8): Remove. (vminaq_m_s16): Remove. (vmaxaq_m_s16): Remove. (vminaq_m_s32): Remove. (vmaxaq_m_s32): Remove. (__arm_vminaq_s8): Remove. (__arm_vmaxaq_s8): Remove. (__arm_vminaq_s16): Remove. (__arm_vmaxaq_s16): Remove. (__arm_vminaq_s32): Remove. (__arm_vmaxaq_s32): Remove. (__arm_vminaq_m_s8): Remove. (__arm_vmaxaq_m_s8): Remove. (__arm_vminaq_m_s16): Remove. (__arm_vmaxaq_m_s16): Remove. (__arm_vminaq_m_s32): Remove. (__arm_vmaxaq_m_s32): Remove. (__arm_vminaq): Remove. (__arm_vmaxaq): Remove. (__arm_vminaq_m): Remove. (__arm_vmaxaq_m): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxaq vminaqChristophe Lyon2-39/+28
Factorize vmaxaq vminaq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M): New. (mve_insn): Add vmaxa, vmina. (supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S. * config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics] add binary_maxamina shapeChristophe Lyon2-0/+41
This patch adds the binary_maxamina shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_maxamina): New. * config/arm/arm-mve-builtins-shapes.h (binary_maxamina): New.
2023-05-09arm: [MVE intrinsics] rework vmaxnmaq vminnmaqChristophe Lyon5-148/+8
Implement vmaxnmaq and vminnmaq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmaxnmaq, vminnmaq): New. * config/arm/arm-mve-builtins-base.def (vmaxnmaq, vminnmaq): New. * config/arm/arm-mve-builtins-base.h (vmaxnmaq, vminnmaq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmaxnmaq and vminnmaq. * config/arm/arm_mve.h (vminnmaq): Remove. (vmaxnmaq): Remove. (vmaxnmaq_m): Remove. (vminnmaq_m): Remove. (vminnmaq_f16): Remove. (vmaxnmaq_f16): Remove. (vminnmaq_f32): Remove. (vmaxnmaq_f32): Remove. (vmaxnmaq_m_f16): Remove. (vminnmaq_m_f16): Remove. (vmaxnmaq_m_f32): Remove. (vminnmaq_m_f32): Remove. (__arm_vminnmaq_f16): Remove. (__arm_vmaxnmaq_f16): Remove. (__arm_vminnmaq_f32): Remove. (__arm_vmaxnmaq_f32): Remove. (__arm_vmaxnmaq_m_f16): Remove. (__arm_vminnmaq_m_f16): Remove. (__arm_vmaxnmaq_m_f32): Remove. (__arm_vminnmaq_m_f32): Remove. (__arm_vminnmaq): Remove. (__arm_vmaxnmaq): Remove. (__arm_vmaxnmaq_m): Remove. (__arm_vminnmaq_m): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxnmaq vminnmaqChristophe Lyon2-39/+24
Factorize vmaxnmaq and vminnmaq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ) (MVE_VMAXNMA_VMINNMAQ_M): New. (mve_insn): Add vmaxnma, vminnma. * config/arm/mve.md (mve_vmaxnmaq_f<mode>, mve_vminnmaq_f<mode>): Merge into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vmaxnmaq_m_f<mode>, mve_vminnmaq_m_f<mode>): Merge into ... (@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09arm: [MVE intrinsics] rework vmaxnmavq vmaxnmvq vminnmavq vminnmvqChristophe Lyon4-314/+18
Implement vmaxnmavq vmaxnmvq vminnmavq vminnmvq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_F): New. (vmaxnmavq, vmaxnmvq, vminnmavq, vminnmvq): New. * config/arm/arm-mve-builtins-base.def (vmaxnmavq, vmaxnmvq) (vminnmavq, vminnmvq): New. * config/arm/arm-mve-builtins-base.h (vmaxnmavq, vmaxnmvq) (vminnmavq, vminnmvq): New. * config/arm/arm_mve.h (vminnmvq): Remove. (vminnmavq): Remove. (vmaxnmvq): Remove. (vmaxnmavq): Remove. (vmaxnmavq_p): Remove. (vmaxnmvq_p): Remove. (vminnmavq_p): Remove. (vminnmvq_p): Remove. (vminnmvq_f16): Remove. (vminnmavq_f16): Remove. (vmaxnmvq_f16): Remove. (vmaxnmavq_f16): Remove. (vminnmvq_f32): Remove. (vminnmavq_f32): Remove. (vmaxnmvq_f32): Remove. (vmaxnmavq_f32): Remove. (vmaxnmavq_p_f16): Remove. (vmaxnmvq_p_f16): Remove. (vminnmavq_p_f16): Remove. (vminnmvq_p_f16): Remove. (vmaxnmavq_p_f32): Remove. (vmaxnmvq_p_f32): Remove. (vminnmavq_p_f32): Remove. (vminnmvq_p_f32): Remove. (__arm_vminnmvq_f16): Remove. (__arm_vminnmavq_f16): Remove. (__arm_vmaxnmvq_f16): Remove. (__arm_vmaxnmavq_f16): Remove. (__arm_vminnmvq_f32): Remove. (__arm_vminnmavq_f32): Remove. (__arm_vmaxnmvq_f32): Remove. (__arm_vmaxnmavq_f32): Remove. (__arm_vmaxnmavq_p_f16): Remove. (__arm_vmaxnmvq_p_f16): Remove. (__arm_vminnmavq_p_f16): Remove. (__arm_vminnmvq_p_f16): Remove. (__arm_vmaxnmavq_p_f32): Remove. (__arm_vmaxnmvq_p_f32): Remove. (__arm_vminnmavq_p_f32): Remove. (__arm_vminnmvq_p_f32): Remove. (__arm_vminnmvq): Remove. (__arm_vminnmavq): Remove. (__arm_vmaxnmvq): Remove. (__arm_vmaxnmavq): Remove. (__arm_vmaxnmavq_p): Remove. (__arm_vmaxnmvq_p): Remove. (__arm_vminnmavq_p): Remove. (__arm_vminnmvq_p): Remove. (__arm_vmaxnmavq_m): Remove. (__arm_vmaxnmvq_m): Remove.
2023-05-09arm: [MVE intrinsics] add support for mve_q_p_fChristophe Lyon1-1/+1
We can call code_for_mve_q_p_f only once this function exists, which is the case after we factorized vmaxnmavq, vmaxnmvq, vminnmavq and vminnmvq in a previous patch. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-functions.h (unspec_mve_function_exact_insn_pred_p): Use code_for_mve_q_p_f.
2023-05-09arm: [MVE intrinsics] factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvqChristophe Lyon2-99/+37
Factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXNMxV_MINNMxVQ) (MVE_VMAXNMxV_MINNMxVQ_P): New. (mve_insn): Add vmaxnmav, vmaxnmv, vminnmav, vminnmv. * config/arm/mve.md (mve_vmaxnmavq_f<mode>, mve_vmaxnmvq_f<mode>) (mve_vminnmavq_f<mode>, mve_vminnmvq_f<mode>): Merge into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vmaxnmavq_p_f<mode>, mve_vmaxnmvq_p_f<mode>) (mve_vminnmavq_p_f<mode>, mve_vminnmvq_p_f<mode>): Merge into ... (@mve_<mve_insn>q_p_f<mode>): ... this.
2023-05-09arm: [MVE intrinsics] rework vmaxnmq vminnmqChristophe Lyon4-224/+6
Implement vmaxnmq and vminnmq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmaxnmq, vminnmq): New. * config/arm/arm-mve-builtins-base.def (vmaxnmq, vminnmq): New. * config/arm/arm-mve-builtins-base.h (vmaxnmq, vminnmq): New. * config/arm/arm_mve.h (vminnmq): Remove. (vmaxnmq): Remove. (vmaxnmq_m): Remove. (vminnmq_m): Remove. (vminnmq_x): Remove. (vmaxnmq_x): Remove. (vminnmq_f16): Remove. (vmaxnmq_f16): Remove. (vminnmq_f32): Remove. (vmaxnmq_f32): Remove. (vmaxnmq_m_f32): Remove. (vmaxnmq_m_f16): Remove. (vminnmq_m_f32): Remove. (vminnmq_m_f16): Remove. (vminnmq_x_f16): Remove. (vminnmq_x_f32): Remove. (vmaxnmq_x_f16): Remove. (vmaxnmq_x_f32): Remove. (__arm_vminnmq_f16): Remove. (__arm_vmaxnmq_f16): Remove. (__arm_vminnmq_f32): Remove. (__arm_vmaxnmq_f32): Remove. (__arm_vmaxnmq_m_f32): Remove. (__arm_vmaxnmq_m_f16): Remove. (__arm_vminnmq_m_f32): Remove. (__arm_vminnmq_m_f16): Remove. (__arm_vminnmq_x_f16): Remove. (__arm_vminnmq_x_f32): Remove. (__arm_vmaxnmq_x_f16): Remove. (__arm_vmaxnmq_x_f32): Remove. (__arm_vminnmq): Remove. (__arm_vmaxnmq): Remove. (__arm_vmaxnmq_m): Remove. (__arm_vminnmq_m): Remove. (__arm_vminnmq_x): Remove. (__arm_vmaxnmq_x): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxnmq vminnmqChristophe Lyon2-54/+19
Factorize vmaxnmq and vminnmq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MAX_MIN_F): New. (MVE_FP_M_BINARY): Add VMAXNMQ_M_F, VMINNMQ_M_F. (mve_insn): Add vmaxnm, vminnm. (max_min_f_str): New. * config/arm/mve.md (mve_vmaxnmq_f<mode>, mve_vminnmq_f<mode>): Merge into ... (@mve_<max_min_f_str>q_f<mode>): ... this. (mve_vmaxnmq_m_f<mode>, mve_vminnmq_m_f<mode>): Merge into ... (@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09arm: add smax/smin expanders for v*hfChristophe Lyon1-6/+6
This patch adds the missing expanders for smax/smin for v*hf modes, by using the VDQWH iterator instead of VALLW. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/vec-common.md (smin<mode>3): Use VDQWH iterator. (smax<mode>3): Likewise.
2023-05-09arm: [MVE intrinsics] rework vmaxvq vminvq vmaxavq vminavqChristophe Lyon4-616/+25
Implement vmaxvq, vminvq, vmaxavq, vminavq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_S_U) (FUNCTION_PRED_P_S): New. (vmaxavq, vminavq, vmaxvq, vminvq): New. * config/arm/arm-mve-builtins-base.def (vmaxavq, vminavq, vmaxvq) (vminvq): New. * config/arm/arm-mve-builtins-base.h (vmaxavq, vminavq, vmaxvq) (vminvq): New. * config/arm/arm_mve.h (vminvq): Remove. (vmaxvq): Remove. (vminvq_p): Remove. (vmaxvq_p): Remove. (vminvq_u8): Remove. (vmaxvq_u8): Remove. (vminvq_s8): Remove. (vmaxvq_s8): Remove. (vminvq_u16): Remove. (vmaxvq_u16): Remove. (vminvq_s16): Remove. (vmaxvq_s16): Remove. (vminvq_u32): Remove. (vmaxvq_u32): Remove. (vminvq_s32): Remove. (vmaxvq_s32): Remove. (vminvq_p_u8): Remove. (vmaxvq_p_u8): Remove. (vminvq_p_s8): Remove. (vmaxvq_p_s8): Remove. (vminvq_p_u16): Remove. (vmaxvq_p_u16): Remove. (vminvq_p_s16): Remove. (vmaxvq_p_s16): Remove. (vminvq_p_u32): Remove. (vmaxvq_p_u32): Remove. (vminvq_p_s32): Remove. (vmaxvq_p_s32): Remove. (__arm_vminvq_u8): Remove. (__arm_vmaxvq_u8): Remove. (__arm_vminvq_s8): Remove. (__arm_vmaxvq_s8): Remove. (__arm_vminvq_u16): Remove. (__arm_vmaxvq_u16): Remove. (__arm_vminvq_s16): Remove. (__arm_vmaxvq_s16): Remove. (__arm_vminvq_u32): Remove. (__arm_vmaxvq_u32): Remove. (__arm_vminvq_s32): Remove. (__arm_vmaxvq_s32): Remove. (__arm_vminvq_p_u8): Remove. (__arm_vmaxvq_p_u8): Remove. (__arm_vminvq_p_s8): Remove. (__arm_vmaxvq_p_s8): Remove. (__arm_vminvq_p_u16): Remove. (__arm_vmaxvq_p_u16): Remove. (__arm_vminvq_p_s16): Remove. (__arm_vmaxvq_p_s16): Remove. (__arm_vminvq_p_u32): Remove. (__arm_vmaxvq_p_u32): Remove. (__arm_vminvq_p_s32): Remove. (__arm_vmaxvq_p_s32): Remove. (__arm_vminvq): Remove. (__arm_vmaxvq): Remove. (__arm_vminvq_p): Remove. (__arm_vmaxvq_p): Remove. (vminavq): Remove. (vmaxavq): Remove. (vminavq_p): Remove. (vmaxavq_p): Remove. (vminavq_s8): Remove. (vmaxavq_s8): Remove. (vminavq_s16): Remove. (vmaxavq_s16): Remove. (vminavq_s32): Remove. (vmaxavq_s32): Remove. (vminavq_p_s8): Remove. (vmaxavq_p_s8): Remove. (vminavq_p_s16): Remove. (vmaxavq_p_s16): Remove. (vminavq_p_s32): Remove. (vmaxavq_p_s32): Remove. (__arm_vminavq_s8): Remove. (__arm_vmaxavq_s8): Remove. (__arm_vminavq_s16): Remove. (__arm_vmaxavq_s16): Remove. (__arm_vminavq_s32): Remove. (__arm_vmaxavq_s32): Remove. (__arm_vminavq_p_s8): Remove. (__arm_vmaxavq_p_s8): Remove. (__arm_vminavq_p_s16): Remove. (__arm_vmaxavq_p_s16): Remove. (__arm_vminavq_p_s32): Remove. (__arm_vmaxavq_p_s32): Remove. (__arm_vminavq): Remove. (__arm_vmaxavq): Remove. (__arm_vminavq_p): Remove. (__arm_vmaxavq_p): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavqChristophe Lyon2-101/+40
Factorize vmaxvq vminvq vmaxavq vminavq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXVQ_VMINVQ, MVE_VMAXVQ_VMINVQ_P): New. (mve_insn): Add vmaxav, vmaxv, vminav, vminv. (supf): Add VMAXAVQ_S, VMAXAVQ_P_S, VMINAVQ_S, VMINAVQ_P_S. * config/arm/mve.md (mve_vmaxavq_s<mode>, mve_vmaxvq_<supf><mode>) (mve_vminavq_s<mode>, mve_vminvq_<supf><mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmaxavq_p_s<mode>, mve_vmaxvq_p_<supf><mode>) (mve_vminavq_p_s<mode>, mve_vminvq_p_<supf><mode>): Merge into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics add unspec_mve_function_exact_insn_pred_pChristophe Lyon1-0/+64
Introduce a function that will be used to build intrinsics that use p predication. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-functions.h (class unspec_mve_function_exact_insn_pred_p): New.
2023-05-09arm: [MVE intrinsics] add binary_maxavminav shapeChristophe Lyon2-0/+31
This patch adds the binary_maxavminav shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_maxavminav): New. * config/arm/arm-mve-builtins-shapes.h (binary_maxavminav): New.
2023-05-09arm: [MVE intrinsics] add binary_maxvminv shapeChristophe Lyon2-0/+31
This patch adds the binary_maxvminv shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_maxvminv): New. * config/arm/arm-mve-builtins-shapes.h (binary_maxvminv): New.
2023-05-09aarch64: Improve register allocation for lane instructionsRichard Sandiford251-368/+413
REG_ALLOC_ORDER is much less important than it used to be, but it is still used as a tie-breaker when multiple registers in a class are equally good. Previously aarch64 used the default approach of allocating in order of increasing register number. But as the comment in the patch says, it's better to allocate FP and predicate registers in the opposite order, so that we don't eat into smaller register classes unnecessarily. This fixes some existing FIXMEs and improves the register allocation for some Arm ACLE code. Doing this also showed that *vcond_mask_<mode><vpred> (predicated MOV/SEL) unnecessarily required p0-p7 rather than p0-p15 for the unpredicated movprfx alternatives. Only the predicated movprfx alternative requires p0-p7 (due to the movprfx itself, rather than due to the main instruction). gcc/ * config/aarch64/aarch64-protos.h (aarch64_adjust_reg_alloc_order): Declare. * config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define. (ADJUST_REG_ALLOC_ORDER): Likewise. * config/aarch64/aarch64.cc (aarch64_adjust_reg_alloc_order): New function. * config/aarch64/aarch64-sve.md (*vcond_mask_<mode><vpred>): Use Upa rather than Upl for unpredicated movprfx alternatives. gcc/testsuite/ * gcc.target/aarch64/sve/acle/asm/abd_f16.c: Remove XFAILs. * gcc.target/aarch64/sve/acle/asm/abd_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/asr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/asr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f16_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f32_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f64_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulx_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulx_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulx_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmad_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmad_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmad_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmla_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmla_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmla_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmls_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmls_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmls_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmsb_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmsb_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmsb_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f16_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f32_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f64_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c: Likewise.
2023-05-09aarch64: Fix cut-&-pasto in aarch64-sve2-acle-asm.expRichard Sandiford1-1/+1
aarch64-sve2-acle-asm.exp tried to prevent --with-cpu/tune from affecting the results, but it used sve_flags rather than sve2_flags. This was a silent failure when running the full testsuite, but was a fatal error when running the harness individually. gcc/testsuite/ * gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Use sve2_flags instead of sve_flags.
2023-05-09PR modula2/109779 isolib SkipLine skips the first character of the ↵Gaius Mulley3-67/+141
successive line This is a patch for the m2iso library to prevent SkipLine from consuming the next character on the next line. gcc/m2/ChangeLog: PR modula2/109779 * gm2-libs-iso/RTgen.mod (doLook): Remove old. Remove re-assignment of result. * gm2-libs-iso/TextIO.mod (CanRead): Rename into ... (CharAvailable): ... this. (DumpState): New procedure. (SetResult): Rename as SetNul. (WasGoodChar): Rename into ... (EofOrEoln): ... this. (SkipLine): Skip over the newline. (ReadString): Flip THEN ELSE statements after testing for EofOrEoln. (ReadRestLine): Flip THEN ELSE statements after testing for EofOrEoln. gcc/testsuite/ChangeLog: PR modula2/109779 * gm2/isolib/run/pass/skiplinetest.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-05-09c++: Reject pack expansion of assume attribute [PR109756]Jakub Jelinek2-0/+32
http://eel.is/c++draft/dcl.attr#grammar-4 says "In an attribute-list, an ellipsis may appear only if that attribute's specification permits it." and doesn't explicitly permit it on any standard attribute. The https://wg21.link/p1774r8 paper which introduced assume attribute says "We could therefore hypothetically permit the assume attribute to directly support pack expansion: template <int... args> void f() { [[assume(args >= 0)...]]; } However, we do not propose this. It would require substantial additional work for a very rare use case. Note that this can instead be expressed with a fold expression, which is equivalent to the above and works out of the box without any extra effort: template <int... args> void f() { [[assume(((args >= 0) && ...))]]; } ", but as the testcase shows, GCC 13+ ICEs on assume attribute followed by ... if it contains packs. The following patch rejects those instead of ICE and for C++17 or later suggests using fold expressions instead (it doesn't make sense to suggest it for C++14 and earlier when we'd error on the fold expressions). 2023-05-09 Jakub Jelinek <jakub@redhat.com> PR c++/109756 * cp-gimplify.cc (process_stmt_assume_attribute): Diagnose pack expansion of assume attribute. * g++.dg/cpp23/attr-assume11.C: New test.
2023-05-09Eliminate more comparisons on the H8 portJeff Law1-1/+13
This patch fixes a minor code quality issue I found while testing LRA on the H8. Specifically we have a peephole which converts a comparison of a memory location against zero into a load + comparison which is actually more efficient. This triggers when there are registers available at the right point during peephole2. If the load is not a mode dependent address we can actually do better by realizing the load itself sets the proper flags and eliminate the comparison. I may have expected this to happen when I wrote the original peephole2, but cmpelim runs before peephole2, so clearly if we want to eliminate the comparison we have to do it manually. gcc/ * config/h8300/testcompare.md: Add peephole2 which uses a memory load to set flags, thus eliminating a compare against zero.
2023-05-09arm: [MVE intrinsics] rework vshllbq vshlltqChristophe Lyon4-424/+6
Implement vshllbq and vshlltq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vshllbq, vshlltq): New. * config/arm/arm-mve-builtins-base.def (vshllbq, vshlltq): New. * config/arm/arm-mve-builtins-base.h (vshllbq, vshlltq): New. * config/arm/arm_mve.h (vshlltq): Remove. (vshllbq): Remove. (vshllbq_m): Remove. (vshlltq_m): Remove. (vshllbq_x): Remove. (vshlltq_x): Remove. (vshlltq_n_u8): Remove. (vshllbq_n_u8): Remove. (vshlltq_n_s8): Remove. (vshllbq_n_s8): Remove. (vshlltq_n_u16): Remove. (vshllbq_n_u16): Remove. (vshlltq_n_s16): Remove. (vshllbq_n_s16): Remove. (vshllbq_m_n_s8): Remove. (vshllbq_m_n_s16): Remove. (vshllbq_m_n_u8): Remove. (vshllbq_m_n_u16): Remove. (vshlltq_m_n_s8): Remove. (vshlltq_m_n_s16): Remove. (vshlltq_m_n_u8): Remove. (vshlltq_m_n_u16): Remove. (vshllbq_x_n_s8): Remove. (vshllbq_x_n_s16): Remove. (vshllbq_x_n_u8): Remove. (vshllbq_x_n_u16): Remove. (vshlltq_x_n_s8): Remove. (vshlltq_x_n_s16): Remove. (vshlltq_x_n_u8): Remove. (vshlltq_x_n_u16): Remove. (__arm_vshlltq_n_u8): Remove. (__arm_vshllbq_n_u8): Remove. (__arm_vshlltq_n_s8): Remove. (__arm_vshllbq_n_s8): Remove. (__arm_vshlltq_n_u16): Remove. (__arm_vshllbq_n_u16): Remove. (__arm_vshlltq_n_s16): Remove. (__arm_vshllbq_n_s16): Remove. (__arm_vshllbq_m_n_s8): Remove. (__arm_vshllbq_m_n_s16): Remove. (__arm_vshllbq_m_n_u8): Remove. (__arm_vshllbq_m_n_u16): Remove. (__arm_vshlltq_m_n_s8): Remove. (__arm_vshlltq_m_n_s16): Remove. (__arm_vshlltq_m_n_u8): Remove. (__arm_vshlltq_m_n_u16): Remove. (__arm_vshllbq_x_n_s8): Remove. (__arm_vshllbq_x_n_s16): Remove. (__arm_vshllbq_x_n_u8): Remove. (__arm_vshllbq_x_n_u16): Remove. (__arm_vshlltq_x_n_s8): Remove. (__arm_vshlltq_x_n_s16): Remove. (__arm_vshlltq_x_n_u8): Remove. (__arm_vshlltq_x_n_u16): Remove. (__arm_vshlltq): Remove. (__arm_vshllbq): Remove. (__arm_vshllbq_m): Remove. (__arm_vshlltq_m): Remove. (__arm_vshllbq_x): Remove. (__arm_vshlltq_x): Remove.
2023-05-09arm: [MVE intrinsics] factorize vshllbq vshlltqChristophe Lyon2-44/+16
Factorize vshllbq vshlltq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vshllb, vshllt. (VSHLLBQ_N, VSHLLTQ_N): Remove. (VSHLLxQ_N): New. (VSHLLBQ_M_N, VSHLLTQ_M_N): Remove. (VSHLLxQ_M_N): New. * config/arm/mve.md (mve_vshllbq_n_<supf><mode>) (mve_vshlltq_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vshllbq_m_n_<supf><mode>, mve_vshlltq_m_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics] add binary_widen_n shapeChristophe Lyon2-0/+54
This patch adds the binary_widen_n shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_widen_n): New. * config/arm/arm-mve-builtins-shapes.h (binary_widen_n): New.
2023-05-09arm: [MVE intrinsics] rework vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq ↵Christophe Lyon5-789/+25
vqmovuntq Implement vmovnbq, vmovntq, vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmovnbq, vmovntq, vqmovnbq) (vqmovntq, vqmovunbq, vqmovuntq): New. * config/arm/arm-mve-builtins-base.def (vmovnbq, vmovntq) (vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq): New. * config/arm/arm-mve-builtins-base.h (vmovnbq, vmovntq, vqmovnbq) (vqmovntq, vqmovunbq, vqmovuntq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmovnbq, vmovntq, vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq. * config/arm/arm_mve.h (vqmovntq): Remove. (vqmovnbq): Remove. (vqmovnbq_m): Remove. (vqmovntq_m): Remove. (vqmovntq_u16): Remove. (vqmovnbq_u16): Remove. (vqmovntq_s16): Remove. (vqmovnbq_s16): Remove. (vqmovntq_u32): Remove. (vqmovnbq_u32): Remove. (vqmovntq_s32): Remove. (vqmovnbq_s32): Remove. (vqmovnbq_m_s16): Remove. (vqmovntq_m_s16): Remove. (vqmovnbq_m_u16): Remove. (vqmovntq_m_u16): Remove. (vqmovnbq_m_s32): Remove. (vqmovntq_m_s32): Remove. (vqmovnbq_m_u32): Remove. (vqmovntq_m_u32): Remove. (__arm_vqmovntq_u16): Remove. (__arm_vqmovnbq_u16): Remove. (__arm_vqmovntq_s16): Remove. (__arm_vqmovnbq_s16): Remove. (__arm_vqmovntq_u32): Remove. (__arm_vqmovnbq_u32): Remove. (__arm_vqmovntq_s32): Remove. (__arm_vqmovnbq_s32): Remove. (__arm_vqmovnbq_m_s16): Remove. (__arm_vqmovntq_m_s16): Remove. (__arm_vqmovnbq_m_u16): Remove. (__arm_vqmovntq_m_u16): Remove. (__arm_vqmovnbq_m_s32): Remove. (__arm_vqmovntq_m_s32): Remove. (__arm_vqmovnbq_m_u32): Remove. (__arm_vqmovntq_m_u32): Remove. (__arm_vqmovntq): Remove. (__arm_vqmovnbq): Remove. (__arm_vqmovnbq_m): Remove. (__arm_vqmovntq_m): Remove. (vmovntq): Remove. (vmovnbq): Remove. (vmovnbq_m): Remove. (vmovntq_m): Remove. (vmovntq_u16): Remove. (vmovnbq_u16): Remove. (vmovntq_s16): Remove. (vmovnbq_s16): Remove. (vmovntq_u32): Remove. (vmovnbq_u32): Remove. (vmovntq_s32): Remove. (vmovnbq_s32): Remove. (vmovnbq_m_s16): Remove. (vmovntq_m_s16): Remove. (vmovnbq_m_u16): Remove. (vmovntq_m_u16): Remove. (vmovnbq_m_s32): Remove. (vmovntq_m_s32): Remove. (vmovnbq_m_u32): Remove. (vmovntq_m_u32): Remove. (__arm_vmovntq_u16): Remove. (__arm_vmovnbq_u16): Remove. (__arm_vmovntq_s16): Remove. (__arm_vmovnbq_s16): Remove. (__arm_vmovntq_u32): Remove. (__arm_vmovnbq_u32): Remove. (__arm_vmovntq_s32): Remove. (__arm_vmovnbq_s32): Remove. (__arm_vmovnbq_m_s16): Remove. (__arm_vmovntq_m_s16): Remove. (__arm_vmovnbq_m_u16): Remove. (__arm_vmovntq_m_u16): Remove. (__arm_vmovnbq_m_s32): Remove. (__arm_vmovntq_m_s32): Remove. (__arm_vmovnbq_m_u32): Remove. (__arm_vmovntq_m_u32): Remove. (__arm_vmovntq): Remove. (__arm_vmovnbq): Remove. (__arm_vmovnbq_m): Remove. (__arm_vmovntq_m): Remove. (vqmovuntq): Remove. (vqmovunbq): Remove. (vqmovunbq_m): Remove. (vqmovuntq_m): Remove. (vqmovuntq_s16): Remove. (vqmovunbq_s16): Remove. (vqmovuntq_s32): Remove. (vqmovunbq_s32): Remove. (vqmovunbq_m_s16): Remove. (vqmovuntq_m_s16): Remove. (vqmovunbq_m_s32): Remove. (vqmovuntq_m_s32): Remove. (__arm_vqmovuntq_s16): Remove. (__arm_vqmovunbq_s16): Remove. (__arm_vqmovuntq_s32): Remove. (__arm_vqmovunbq_s32): Remove. (__arm_vqmovunbq_m_s16): Remove. (__arm_vqmovuntq_m_s16): Remove. (__arm_vqmovunbq_m_s32): Remove. (__arm_vqmovuntq_m_s32): Remove. (__arm_vqmovuntq): Remove. (__arm_vqmovunbq): Remove. (__arm_vqmovunbq_m): Remove. (__arm_vqmovuntq_m): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq ↵Christophe Lyon2-162/+64
vqmovuntq Factorize vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq vqmovuntq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_MOVN, MVE_MOVN_M): New. (mve_insn): Add vmovnb, vmovnt, vqmovnb, vqmovnt, vqmovunb, vqmovunt. (isu): Likewise. (supf): Add VQMOVUNBQ_M_S, VQMOVUNBQ_S, VQMOVUNTQ_M_S, VQMOVUNTQ_S. * config/arm/mve.md (mve_vmovnbq_<supf><mode>) (mve_vmovntq_<supf><mode>, mve_vqmovnbq_<supf><mode>) (mve_vqmovntq_<supf><mode>, mve_vqmovunbq_s<mode>) (mve_vqmovuntq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmovnbq_m_<supf><mode>, mve_vmovntq_m_<supf><mode>) (mve_vqmovnbq_m_<supf><mode>, mve_vqmovntq_m_<supf><mode>) (mve_vqmovunbq_m_s<mode>, mve_vqmovuntq_m_s<mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics] add binary_move_narrow and binary_move_narrow_unsigned ↵Christophe Lyon2-0/+75
shapes This patch adds the binary_move_narrow and binary_move_narrow_unsigned shapes descriptions. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_move_narrow): New. (binary_move_narrow_unsigned): New. * config/arm/arm-mve-builtins-shapes.h (binary_move_narrow): New. (binary_move_narrow_unsigned): New.
2023-05-09arm: [MVE intrinsics] rework vrndq vrndaq vrndmq vrndnq vrndpq vrndxqChristophe Lyon4-655/+27
Implement vrndq, vrndaq, vrndmq, vrndnq, vrndpq, vrndxq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_F): New. (vrndaq, vrndmq, vrndnq, vrndpq, vrndq, vrndxq): New. * config/arm/arm-mve-builtins-base.def (vrndaq, vrndmq, vrndnq) (vrndpq, vrndq, vrndxq): New. * config/arm/arm-mve-builtins-base.h (vrndaq, vrndmq, vrndnq) (vrndpq, vrndq, vrndxq): New. * config/arm/arm_mve.h (vrndxq): Remove. (vrndq): Remove. (vrndpq): Remove. (vrndnq): Remove. (vrndmq): Remove. (vrndaq): Remove. (vrndaq_m): Remove. (vrndmq_m): Remove. (vrndnq_m): Remove. (vrndpq_m): Remove. (vrndq_m): Remove. (vrndxq_m): Remove. (vrndq_x): Remove. (vrndnq_x): Remove. (vrndmq_x): Remove. (vrndpq_x): Remove. (vrndaq_x): Remove. (vrndxq_x): Remove. (vrndxq_f16): Remove. (vrndxq_f32): Remove. (vrndq_f16): Remove. (vrndq_f32): Remove. (vrndpq_f16): Remove. (vrndpq_f32): Remove. (vrndnq_f16): Remove. (vrndnq_f32): Remove. (vrndmq_f16): Remove. (vrndmq_f32): Remove. (vrndaq_f16): Remove. (vrndaq_f32): Remove. (vrndaq_m_f16): Remove. (vrndmq_m_f16): Remove. (vrndnq_m_f16): Remove. (vrndpq_m_f16): Remove. (vrndq_m_f16): Remove. (vrndxq_m_f16): Remove. (vrndaq_m_f32): Remove. (vrndmq_m_f32): Remove. (vrndnq_m_f32): Remove. (vrndpq_m_f32): Remove. (vrndq_m_f32): Remove. (vrndxq_m_f32): Remove. (vrndq_x_f16): Remove. (vrndq_x_f32): Remove. (vrndnq_x_f16): Remove. (vrndnq_x_f32): Remove. (vrndmq_x_f16): Remove. (vrndmq_x_f32): Remove. (vrndpq_x_f16): Remove. (vrndpq_x_f32): Remove. (vrndaq_x_f16): Remove. (vrndaq_x_f32): Remove. (vrndxq_x_f16): Remove. (vrndxq_x_f32): Remove. (__arm_vrndxq_f16): Remove. (__arm_vrndxq_f32): Remove. (__arm_vrndq_f16): Remove. (__arm_vrndq_f32): Remove. (__arm_vrndpq_f16): Remove. (__arm_vrndpq_f32): Remove. (__arm_vrndnq_f16): Remove. (__arm_vrndnq_f32): Remove. (__arm_vrndmq_f16): Remove. (__arm_vrndmq_f32): Remove. (__arm_vrndaq_f16): Remove. (__arm_vrndaq_f32): Remove. (__arm_vrndaq_m_f16): Remove. (__arm_vrndmq_m_f16): Remove. (__arm_vrndnq_m_f16): Remove. (__arm_vrndpq_m_f16): Remove. (__arm_vrndq_m_f16): Remove. (__arm_vrndxq_m_f16): Remove. (__arm_vrndaq_m_f32): Remove. (__arm_vrndmq_m_f32): Remove. (__arm_vrndnq_m_f32): Remove. (__arm_vrndpq_m_f32): Remove. (__arm_vrndq_m_f32): Remove. (__arm_vrndxq_m_f32): Remove. (__arm_vrndq_x_f16): Remove. (__arm_vrndq_x_f32): Remove. (__arm_vrndnq_x_f16): Remove. (__arm_vrndnq_x_f32): Remove. (__arm_vrndmq_x_f16): Remove. (__arm_vrndmq_x_f32): Remove. (__arm_vrndpq_x_f16): Remove. (__arm_vrndpq_x_f32): Remove. (__arm_vrndaq_x_f16): Remove. (__arm_vrndaq_x_f32): Remove. (__arm_vrndxq_x_f16): Remove. (__arm_vrndxq_x_f32): Remove. (__arm_vrndxq): Remove. (__arm_vrndq): Remove. (__arm_vrndpq): Remove. (__arm_vrndnq): Remove. (__arm_vrndmq): Remove. (__arm_vrndaq): Remove. (__arm_vrndaq_m): Remove. (__arm_vrndmq_m): Remove. (__arm_vrndnq_m): Remove. (__arm_vrndpq_m): Remove. (__arm_vrndq_m): Remove. (__arm_vrndxq_m): Remove. (__arm_vrndq_x): Remove. (__arm_vrndnq_x): Remove. (__arm_vrndmq_x): Remove. (__arm_vrndpq_x): Remove. (__arm_vrndaq_x): Remove. (__arm_vrndxq_x): Remove.
2023-05-09arm: [MVE intrinsics] rework vabsq vnegq vclsq vclzq, vqabsq, vqnegqChristophe Lyon4-1264/+30
Implement vabsq, vnegq, vclsq, vclzq, vqabsq, vqnegq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N_NO_U_F): New. (vabsq, vnegq, vclsq, vclzq, vqabsq, vqnegq): New. * config/arm/arm-mve-builtins-base.def (vabsq, vnegq, vclsq) (vclzq, vqabsq, vqnegq): New. * config/arm/arm-mve-builtins-base.h (vabsq, vnegq, vclsq, vclzq) (vqabsq, vqnegq): New. * config/arm/arm_mve.h (vabsq): Remove. (vabsq_m): Remove. (vabsq_x): Remove. (vabsq_f16): Remove. (vabsq_f32): Remove. (vabsq_s8): Remove. (vabsq_s16): Remove. (vabsq_s32): Remove. (vabsq_m_s8): Remove. (vabsq_m_s16): Remove. (vabsq_m_s32): Remove. (vabsq_m_f16): Remove. (vabsq_m_f32): Remove. (vabsq_x_s8): Remove. (vabsq_x_s16): Remove. (vabsq_x_s32): Remove. (vabsq_x_f16): Remove. (vabsq_x_f32): Remove. (__arm_vabsq_s8): Remove. (__arm_vabsq_s16): Remove. (__arm_vabsq_s32): Remove. (__arm_vabsq_m_s8): Remove. (__arm_vabsq_m_s16): Remove. (__arm_vabsq_m_s32): Remove. (__arm_vabsq_x_s8): Remove. (__arm_vabsq_x_s16): Remove. (__arm_vabsq_x_s32): Remove. (__arm_vabsq_f16): Remove. (__arm_vabsq_f32): Remove. (__arm_vabsq_m_f16): Remove. (__arm_vabsq_m_f32): Remove. (__arm_vabsq_x_f16): Remove. (__arm_vabsq_x_f32): Remove. (__arm_vabsq): Remove. (__arm_vabsq_m): Remove. (__arm_vabsq_x): Remove. (vnegq): Remove. (vnegq_m): Remove. (vnegq_x): Remove. (vnegq_f16): Remove. (vnegq_f32): Remove. (vnegq_s8): Remove. (vnegq_s16): Remove. (vnegq_s32): Remove. (vnegq_m_s8): Remove. (vnegq_m_s16): Remove. (vnegq_m_s32): Remove. (vnegq_m_f16): Remove. (vnegq_m_f32): Remove. (vnegq_x_s8): Remove. (vnegq_x_s16): Remove. (vnegq_x_s32): Remove. (vnegq_x_f16): Remove. (vnegq_x_f32): Remove. (__arm_vnegq_s8): Remove. (__arm_vnegq_s16): Remove. (__arm_vnegq_s32): Remove. (__arm_vnegq_m_s8): Remove. (__arm_vnegq_m_s16): Remove. (__arm_vnegq_m_s32): Remove. (__arm_vnegq_x_s8): Remove. (__arm_vnegq_x_s16): Remove. (__arm_vnegq_x_s32): Remove. (__arm_vnegq_f16): Remove. (__arm_vnegq_f32): Remove. (__arm_vnegq_m_f16): Remove. (__arm_vnegq_m_f32): Remove. (__arm_vnegq_x_f16): Remove. (__arm_vnegq_x_f32): Remove. (__arm_vnegq): Remove. (__arm_vnegq_m): Remove. (__arm_vnegq_x): Remove. (vclsq): Remove. (vclsq_m): Remove. (vclsq_x): Remove. (vclsq_s8): Remove. (vclsq_s16): Remove. (vclsq_s32): Remove. (vclsq_m_s8): Remove. (vclsq_m_s16): Remove. (vclsq_m_s32): Remove. (vclsq_x_s8): Remove. (vclsq_x_s16): Remove. (vclsq_x_s32): Remove. (__arm_vclsq_s8): Remove. (__arm_vclsq_s16): Remove. (__arm_vclsq_s32): Remove. (__arm_vclsq_m_s8): Remove. (__arm_vclsq_m_s16): Remove. (__arm_vclsq_m_s32): Remove. (__arm_vclsq_x_s8): Remove. (__arm_vclsq_x_s16): Remove. (__arm_vclsq_x_s32): Remove. (__arm_vclsq): Remove. (__arm_vclsq_m): Remove. (__arm_vclsq_x): Remove. (vclzq): Remove. (vclzq_m): Remove. (vclzq_x): Remove. (vclzq_s8): Remove. (vclzq_s16): Remove. (vclzq_s32): Remove. (vclzq_u8): Remove. (vclzq_u16): Remove. (vclzq_u32): Remove. (vclzq_m_u8): Remove. (vclzq_m_s8): Remove. (vclzq_m_u16): Remove. (vclzq_m_s16): Remove. (vclzq_m_u32): Remove. (vclzq_m_s32): Remove. (vclzq_x_s8): Remove. (vclzq_x_s16): Remove. (vclzq_x_s32): Remove. (vclzq_x_u8): Remove. (vclzq_x_u16): Remove. (vclzq_x_u32): Remove. (__arm_vclzq_s8): Remove. (__arm_vclzq_s16): Remove. (__arm_vclzq_s32): Remove. (__arm_vclzq_u8): Remove. (__arm_vclzq_u16): Remove. (__arm_vclzq_u32): Remove. (__arm_vclzq_m_u8): Remove. (__arm_vclzq_m_s8): Remove. (__arm_vclzq_m_u16): Remove. (__arm_vclzq_m_s16): Remove. (__arm_vclzq_m_u32): Remove. (__arm_vclzq_m_s32): Remove. (__arm_vclzq_x_s8): Remove. (__arm_vclzq_x_s16): Remove. (__arm_vclzq_x_s32): Remove. (__arm_vclzq_x_u8): Remove. (__arm_vclzq_x_u16): Remove. (__arm_vclzq_x_u32): Remove. (__arm_vclzq): Remove. (__arm_vclzq_m): Remove. (__arm_vclzq_x): Remove. (vqabsq): Remove. (vqnegq): Remove. (vqnegq_m): Remove. (vqabsq_m): Remove. (vqabsq_s8): Remove. (vqabsq_s16): Remove. (vqabsq_s32): Remove. (vqnegq_s8): Remove. (vqnegq_s16): Remove. (vqnegq_s32): Remove. (vqnegq_m_s8): Remove. (vqabsq_m_s8): Remove. (vqnegq_m_s16): Remove. (vqabsq_m_s16): Remove. (vqnegq_m_s32): Remove. (vqabsq_m_s32): Remove. (__arm_vqabsq_s8): Remove. (__arm_vqabsq_s16): Remove. (__arm_vqabsq_s32): Remove. (__arm_vqnegq_s8): Remove. (__arm_vqnegq_s16): Remove. (__arm_vqnegq_s32): Remove. (__arm_vqnegq_m_s8): Remove. (__arm_vqabsq_m_s8): Remove. (__arm_vqnegq_m_s16): Remove. (__arm_vqabsq_m_s16): Remove. (__arm_vqnegq_m_s32): Remove. (__arm_vqabsq_m_s32): Remove. (__arm_vqabsq): Remove. (__arm_vqnegq): Remove. (__arm_vqnegq_m): Remove. (__arm_vqabsq_m): Remove.
2023-05-09arm: [MVE intrinsics] factorize several unary operationsChristophe Lyon2-337/+126
Factorize vabs vcls vclz vneg vqabs vqneg vrnda vrndm vrndn vrndp vrnd vrndx so that they use the same pattern. This patch introduces the mve_mnemo iterator because some of the involved intrinsics have a different name from their mnenonic: for instance vrndq vs vrintz. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_INT_M_UNARY, MVE_INT_UNARY) (MVE_FP_UNARY, MVE_FP_M_UNARY): New. (mve_insn): Add vabs, vcls, vclz, vneg, vqabs, vqneg, vrnda, vrndm, vrndn, vrndp, vrnd, vrndx. (isu): Add VABSQ_M_S, VCLSQ_M_S, VCLZQ_M_S, VCLZQ_M_U, VNEGQ_M_S, VQABSQ_M_S, VQNEGQ_M_S. (mve_mnemo): New. * config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrndxq_f<mode>) (mve_vrndq_f<mode>, mve_vrndpq_f<mode>, mve_vrndnq_f<mode>) (mve_vrndmq_f<mode>, mve_vrndaq_f<mode>): Merge into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vnegq_f<mode>, mve_vabsq_f<mode>): Merge into ... (mve_v<absneg_str>q_f<mode>): ... this. (mve_vnegq_s<mode>, mve_vabsq_s<mode>): Merge into ... (mve_v<absneg_str>q_s<mode>): ... this. (mve_vclsq_s<mode>, mve_vqnegq_s<mode>, mve_vqabsq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vabsq_m_s<mode>, mve_vclsq_m_s<mode>) (mve_vclzq_m_<supf><mode>, mve_vnegq_m_s<mode>) (mve_vqabsq_m_s<mode>, mve_vqnegq_m_s<mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this. (mve_vabsq_m_f<mode>, mve_vnegq_m_f<mode>, mve_vrndaq_m_f<mode>) (mve_vrndmq_m_f<mode>, mve_vrndnq_m_f<mode>, mve_vrndpq_m_f<mode>) (mve_vrndxq_m_f<mode>): Merge into ... (@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09arm: [MVE intrinsics] add unary shapeChristophe Lyon2-0/+28
This patch adds the unary shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary): New. * config/arm/arm-mve-builtins-shapes.h (unary): New.
2023-05-09mux-utils.h: Fix a comment typoJakub Jelinek1-1/+1
Trivial comment typo... 2023-05-09 Jakub Jelinek <jakub@redhat.com> * mux-utils.h: Fix comment typo, avoides -> avoids.
2023-05-09testsuite: Add further testcase for already fixed PR [PR109778]Jakub Jelinek2-0/+29
I came up with a testcase which reproduces all the way to r10-7469. LTO to avoid early inlining it, so that ccp handles rotates and not shifts before they are turned into rotates. 2023-05-09 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/109778 * gcc.dg/lto/pr109778_0.c: New test. * gcc.dg/lto/pr109778_1.c: New file.
2023-05-09tree-ssa-ccp, wide-int: Fix up handling of [LR]ROTATE_EXPR in bitwise ccp ↵Jakub Jelinek3-6/+37
[PR109778] The following testcase is miscompiled, because bitwise ccp2 handles a rotate with a signed type incorrectly. Seems tree-ssa-ccp.cc has the only callers of wi::[lr]rotate with 3 arguments, all other callers just rotate in the right precision and I think work correctly. ccp works with widest_ints and so rotations by the excessive precision certainly don't match what it wants when it sees a rotate in some specific bitsize. Still, if it is unsigned rotate and the widest_int is zero extended from width, the functions perform left shift and logical right shift on the value and then at the end zero extend the result of left shift and uselessly also the result of logical right shift and return | of that. On the testcase we the signed char rrotate by 4 argument is CONSTANT -75 i.e. 0xffffffff....fffffb5 with mask 2. The mask is correctly rotated to 0x20, but because the 8-bit constant is sign extended to 192-bit one, the logical right shift by 4 doesn't yield expected 0xb, but gives 0xfffffffffff....ffffb, and then return wi::zext (left, width) | wi::zext (right, width); where left is 0xfffffff....fb50, so we return 0xfb instead of the expected 0x5b. The following patch fixes that by doing the zero extension in case of the right variable before doing wi::lrshift rather than after it. Also, wi::[lr]rotate widht width < precision always zero extends the result. I'm afraid it can't do better because it doesn't know if it is done for an unsigned or signed type, but the caller in this case knows that very well, so I've done the extension based on sgn in the caller. E.g. 0x5b rotated right (or left) by 4 with width 8 previously gave 0xb5, but sgn == SIGNED in widest_int it should be 0xffffffff....fffb5 instead. 2023-05-09 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/109778 * wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on wi::zext (x, width) rather than x if width != precision, rather than using wi::zext (right, width) after the shift. * tree-ssa-ccp.cc (bit_value_binop): Call wi::ext on the results of wi::lrotate or wi::rrotate. * gcc.c-torture/execute/pr109778.c: New test.
2023-05-09genmatch: fixup get_out_fileAlexander Monakov1-24/+17
get_out_file did not follow the coding conventions (mixing three-space and two-space indentation, missing linebreak before function name). Take that as an excuse to reimplement it in a more terse manner and rename as 'choose_output', which is hopefully more descriptive. gcc/ChangeLog: * genmatch.cc (get_out_file): Make static and rename to ... (choose_output): ... this. Reimplement. Update all uses ... (decision_tree::gen): ... here and ... (main): ... here.
2023-05-09genmatch: clean up showUsageAlexander Monakov1-11/+10
Display usage more consistently and get rid of camelCase. gcc/ChangeLog: * genmatch.cc (showUsage): Reimplement as ... (usage): ...this. Adjust all uses. (main): Print usage when no arguments. Add missing 'return 1'.
2023-05-09genmatch: clean up emit_funcAlexander Monakov1-45/+52
Eliminate boolean parameters of emit_func. The first ('open') just prints 'extern' to generated header, which is unnecessary. Introduce a separate function to use when finishing a declaration in place of the second ('close'). Rename emit_func to 'fp_decl' (matching 'fprintf' in length) to unbreak indentation in several places. Reshuffle emitted line breaks in a few places to make generated declarations less ugly. gcc/ChangeLog: * genmatch.cc (header_file): Make static. (emit_func): Rename to... (fp_decl): ... this. Adjust all uses. (fp_decl_done): New function. Use it... (decision_tree::gen): ... here and... (write_predicate): ... here. (main): Adjust.
2023-05-09aarch64: Avoid hard-coding specific register allocationsRichard Sandiford33-272/+269
Some tests hard-coded specific allocations for temporary registers, whereas the RA should be free to pick anything that doesn't force unnecessary moves or spills. gcc/testsuite/ * gcc.target/aarch64/asimd-mul-to-shl-sub.c: Allow any register allocation for temporary results, rather than requiring specific registers. * gcc.target/aarch64/auto-init-padding-1.c: Likewise. * gcc.target/aarch64/auto-init-padding-2.c: Likewise. * gcc.target/aarch64/auto-init-padding-3.c: Likewise. * gcc.target/aarch64/auto-init-padding-4.c: Likewise. * gcc.target/aarch64/auto-init-padding-9.c: Likewise. * gcc.target/aarch64/memset-corner-cases.c: Likewise. * gcc.target/aarch64/memset-q-reg.c: Likewise. * gcc.target/aarch64/simd/vaddlv_1.c: Likewise. * gcc.target/aarch64/sve-neon-modes_1.c: Likewise. * gcc.target/aarch64/sve-neon-modes_3.c: Likewise. * gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_256.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_512.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_1024.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_2048.c: Likewise. * gcc.target/aarch64/sve/pr89007-1.c: Likewise. * gcc.target/aarch64/sve/pr89007-2.c: Likewise. * gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise. * gcc.target/aarch64/vadd_reduc-1.c: Likewise. * gcc.target/aarch64/vadd_reduc-2.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Allow the temporary predicate register to be any of p4-p7, rather than requiring p4 specifically. * gcc.target/aarch64/sve/pcs/args_5_be_f16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_f32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_f64.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s8.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s64.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u8.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u64.c: Likewise.
2023-05-09aarch64: Relax FP/vector register matchesRichard Sandiford22-82/+82
There were many tests that used [0-9] to match an FP or vector register, but that should allow any of 0-31 instead. asm-x-constraint-1.c required s0-s7, but that's the range for "y" rather than "x". "x" allows s0-s15. sve/pcs/return_9.c required z2-z7 (the initial set of available call-clobbered registers), but z24-z31 are OK too. gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c: Allow any FP/vector register, not just register 0-9. * gcc.target/aarch64/fmul_fcvt_2.c: Likewise. * gcc.target/aarch64/ldp_stp_8.c: Likewise. * gcc.target/aarch64/ldp_stp_17.c: Likewise. * gcc.target/aarch64/ldp_stp_21.c: Likewise. * gcc.target/aarch64/simd/vpaddd_f64.c: Likewise. * gcc.target/aarch64/simd/vpaddd_s64.c: Likewise. * gcc.target/aarch64/simd/vpaddd_u64.c: Likewise. * gcc.target/aarch64/sve/adr_1.c: Likewise. * gcc.target/aarch64/sve/adr_2.c: Likewise. * gcc.target/aarch64/sve/adr_3.c: Likewise. * gcc.target/aarch64/sve/adr_4.c: Likewise. * gcc.target/aarch64/sve/adr_5.c: Likewise. * gcc.target/aarch64/sve/extract_1.c: Likewise. * gcc.target/aarch64/sve/extract_2.c: Likewise. * gcc.target/aarch64/sve/extract_3.c: Likewise. * gcc.target/aarch64/sve/extract_4.c: Likewise. * gcc.target/aarch64/sve/slp_4.c: Likewise. * gcc.target/aarch64/sve/spill_3.c: Likewise. * gcc.target/aarch64/vfp-1.c: Likewise. * gcc.target/aarch64/asm-x-constraint-1.c: Allow s0-s15, not just s0-s7. * gcc.target/aarch64/sve/pcs/return_9.c: Allow z24-z31 as well as z2-z7.
2023-05-09aarch64: Relax predicate register matchesRichard Sandiford22-578/+578
Most governing predicate operands require p0-p7, but some instructions also allow p8-p15. Non-gp uses of predicates often also allow all of p0-p15. This patch fixes up cases where we required p0-p7 unnecessarily. In some cases we match the definition (typically a comparison, PFALSE or PTRUE), sometimes we match the use (like a logic instruction, MOV or SEL), and sometimes we match both. gcc/testsuite/ * g++.target/aarch64/sve/vcond_1.C: Allow any predicate register for the temporary results, not just p0-p7. * gcc.target/aarch64/sve/acle/asm/dupq_b8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dupq_b16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dupq_b32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dupq_b64.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_5.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_6.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_7.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_9.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_10.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilelt_1.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilelt_2.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilelt_3.c: Likewise. * gcc.target/aarch64/sve/pcs/varargs_1.c: Likewise. * gcc.target/aarch64/sve/peel_ind_2.c: Likewise. * gcc.target/aarch64/sve/mask_gather_load_6.c: Likewise. * gcc.target/aarch64/sve/vcond_2.c: Likewise. * gcc.target/aarch64/sve/vcond_3.c: Likewise. * gcc.target/aarch64/sve/vcond_7.c: Likewise. * gcc.target/aarch64/sve/vcond_18.c: Likewise. * gcc.target/aarch64/sve/vcond_19.c: Likewise. * gcc.target/aarch64/sve/vcond_20.c: Likewise.
2023-05-09aarch64: Relax ordering requirements in SVE dup testsRichard Sandiford6-0/+384
Some of the svdup tests expand to a SEL between two constant vectors. This patch allows the constants to be formed in either order. gcc/testsuite/ * gcc.target/aarch64/sve/acle/asm/dup_s16.c: When using SEL to select between two constant vectors, allow the constant moves to appear in either order. * gcc.target/aarch64/sve/acle/asm/dup_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u64.c: Likewise.
2023-05-09aarch64: Allow moves after tied-register intrinsicsRichard Sandiford38-0/+360
Some ACLE intrinsics map to instructions that tie the output operand to an input operand. If all the operands are allocated to different registers, and if MOVPRFX can't be used, we will need a move either before the instruction or after it. Many tests only matched the "before" case; this patch makes them accept the "after" case too. gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c: Allow moves to occur after the intrinsic instruction, rather than requiring them to happen before. * gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c: Likewise. * gcc.target/aarch64/sve/acle/asm/adda_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/adda_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/adda_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/brka_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/brkb_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/brkn_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_bf16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_bf16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pfirst_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u8.c: Likewise.
2023-05-09aarch64: Fix move-after-intrinsic function-body testsRichard Sandiford5-7/+7
Some of the SVE ACLE asm tests tried to be agnostic about the instruction order, but only one of the alternatives was exercised in practice. This patch fixes latent typos in the other versions. gcc/testsuite/ * gcc.target/aarch64/sve2/acle/asm/aesd_u8.c: Fix expected register allocation in the case where a move occurs after the intrinsic instruction. * gcc.target/aarch64/sve2/acle/asm/aese_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c: Likewise.
2023-05-09ira: Don't create copies for earlyclobbered pairsRichard Sandiford19-18/+21
This patch follows on from g:9f635bd13fe9e85872e441b6f3618947f989909a ("the previous patch"). To start by quoting that: If an insn requires two operands to be tied, and the input operand dies in the insn, IRA acts as though there were a copy from the input to the output with the same execution frequency as the insn. Allocating the same register to the input and the output then saves the cost of a move. If there is no such tie, but an input operand nevertheless dies in the insn, IRA creates a similar move, but with an eighth of the frequency. This helps to ensure that chains of instructions reuse registers in a natural way, rather than using arbitrarily different registers for no reason. This heuristic seems to work well in the vast majority of cases. However, the problem fixed in the previous patch was that we could create a copy for an operand pair even if, for all relevant alternatives, the output and input register classes did not have any registers in common. It is then impossible for the output operand to reuse the dying input register. This left unfixed a further case where copies don't make sense: there is no point trying to reuse the dying input register if, for all relevant alternatives, the output is earlyclobbered and the input doesn't match the output. (Matched earlyclobbers are fine.) Handling that case fixes several existing XFAILs and helps with a follow-on aarch64 patch. Tested on aarch64-linux-gnu and x86_64-linux-gnu. A SPEC2017 run on aarch64 showed no differences outside the noise. Also, I tried compiling gcc.c-torture, gcc.dg, and g++.dg for at least one target per cpu directory, using the options -Os -fno-schedule-insns{,2}. The results below summarise the tests that showed a difference in LOC: Target Tests Good Bad Delta Best Worst Median ====== ===== ==== === ===== ==== ===== ====== amdgcn-amdhsa 14 7 7 3 -18 10 -1 arm-linux-gnueabihf 16 15 1 -22 -4 2 -1 csky-elf 6 6 0 -21 -6 -2 -4 hppa64-hp-hpux11.23 5 5 0 -7 -2 -1 -1 ia64-linux-gnu 16 16 0 -70 -15 -1 -3 m32r-elf 53 1 52 64 -2 8 1 mcore-elf 2 2 0 -8 -6 -2 -6 microblaze-elf 285 283 2 -909 -68 4 -1 mmix 7 7 0 -2101 -2091 -1 -1 msp430-elf 1 1 0 -4 -4 -4 -4 pru-elf 8 6 2 -12 -6 2 -2 rx-elf 22 18 4 -40 -5 6 -2 sparc-linux-gnu 15 14 1 -40 -8 1 -2 sparc-wrs-vxworks 15 14 1 -40 -8 1 -2 visium-elf 2 1 1 0 -2 2 -2 xstormy16-elf 1 1 0 -2 -2 -2 -2 with other targets showing no sensitivity to the patch. The only target that seems to be negatively affected is m32r-elf; otherwise the patch seems like an extremely minor but still clear improvement. gcc/ * ira-conflicts.cc (can_use_same_reg_p): Skip over non-matching earlyclobbers. gcc/testsuite/ * gcc.target/aarch64/sve/acle/asm/asr_wide_s16.c: Remove XFAILs. * gcc.target/aarch64/sve/acle/asm/asr_wide_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/asr_wide_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_wide_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_wide_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_wide_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f64.c: Likewise.
2023-05-08c++: non-template friend of template [PR106740]Jason Merrill1-0/+18
This was fixed by r13-1018, but the testcase seems needed. PR c++/106740 gcc/testsuite/ChangeLog: * g++.dg/template/friend78.C: New test.
2023-05-09Daily bump.GCC Administrator5-1/+224
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