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2023-05-11fortran: use grep instead of fgrepXi Ruoyao1-1/+1
fgrep has been deprecated in favor of grep -F for a long time, and the curren grep release (3.10) prints a warning of fgrep is used. Stop using fgrep so we won't see the warning. We can't hard code grep -F here or it may break build on hosts w/o GNU grep. autoconf documentation contains a warning about this issue and suggest to use AC_PROG_FGREP and $FGREP, but these are too overkill in the specific case: there is no way "debian" could be interpreted as an non-trivial regex, so we can use a plain grep here. gcc/fortran/ChangeLog: * Make-lang.in: Use grep instead of fgrep.
2023-05-11arm: [MVE intrinsics] rework vmovlbq vmovltqChristophe Lyon4-454/+6
Implement vmovlbq, vmovltq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmovlbq, vmovltq): New. * config/arm/arm-mve-builtins-base.def (vmovlbq, vmovltq): New. * config/arm/arm-mve-builtins-base.h (vmovlbq, vmovltq): New. * config/arm/arm_mve.h (vmovlbq): Remove. (vmovltq): Remove. (vmovlbq_m): Remove. (vmovltq_m): Remove. (vmovlbq_x): Remove. (vmovltq_x): Remove. (vmovlbq_s8): Remove. (vmovlbq_s16): Remove. (vmovltq_s8): Remove. (vmovltq_s16): Remove. (vmovltq_u8): Remove. (vmovltq_u16): Remove. (vmovlbq_u8): Remove. (vmovlbq_u16): Remove. (vmovlbq_m_s8): Remove. (vmovltq_m_s8): Remove. (vmovlbq_m_u8): Remove. (vmovltq_m_u8): Remove. (vmovlbq_m_s16): Remove. (vmovltq_m_s16): Remove. (vmovlbq_m_u16): Remove. (vmovltq_m_u16): Remove. (vmovlbq_x_s8): Remove. (vmovlbq_x_s16): Remove. (vmovlbq_x_u8): Remove. (vmovlbq_x_u16): Remove. (vmovltq_x_s8): Remove. (vmovltq_x_s16): Remove. (vmovltq_x_u8): Remove. (vmovltq_x_u16): Remove. (__arm_vmovlbq_s8): Remove. (__arm_vmovlbq_s16): Remove. (__arm_vmovltq_s8): Remove. (__arm_vmovltq_s16): Remove. (__arm_vmovltq_u8): Remove. (__arm_vmovltq_u16): Remove. (__arm_vmovlbq_u8): Remove. (__arm_vmovlbq_u16): Remove. (__arm_vmovlbq_m_s8): Remove. (__arm_vmovltq_m_s8): Remove. (__arm_vmovlbq_m_u8): Remove. (__arm_vmovltq_m_u8): Remove. (__arm_vmovlbq_m_s16): Remove. (__arm_vmovltq_m_s16): Remove. (__arm_vmovlbq_m_u16): Remove. (__arm_vmovltq_m_u16): Remove. (__arm_vmovlbq_x_s8): Remove. (__arm_vmovlbq_x_s16): Remove. (__arm_vmovlbq_x_u8): Remove. (__arm_vmovlbq_x_u16): Remove. (__arm_vmovltq_x_s8): Remove. (__arm_vmovltq_x_s16): Remove. (__arm_vmovltq_x_u8): Remove. (__arm_vmovltq_x_u16): Remove. (__arm_vmovlbq): Remove. (__arm_vmovltq): Remove. (__arm_vmovlbq_m): Remove. (__arm_vmovltq_m): Remove. (__arm_vmovlbq_x): Remove. (__arm_vmovltq_x): Remove.
2023-05-11arm: [MVE intrinsics] add unary_widen shapeChristophe Lyon2-0/+47
This patch adds the unary_widen shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_widen): New. * config/arm/arm-mve-builtins-shapes.h (unary_widen): New.
2023-05-11arm: [MVE intrinsics] factorize vmovlbq vmovltqChristophe Lyon2-39/+15
Factorize vmovlbq, vmovltq builtins so that they use the same parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vmovlb, vmovlt. (VMOVLBQ, VMOVLTQ): Merge into ... (VMOVLxQ): ... this. (VMOVLTQ_M, VMOVLBQ_M): Merge into ... (VMOVLxQ_M): ... this. * config/arm/mve.md (mve_vmovltq_<supf><mode>) (mve_vmovlbq_<supf><mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmovlbq_m_<supf><mode>, mve_vmovltq_m_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] rework vaddlvqChristophe Lyon5-93/+51
Implement vaddlvq using the new MVE builtins framework. Since we kept v4si hardcoded in the builtin name, we need to special-case it in unspec_mve_function_exact_insn_pred_p. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vaddlvq): New. * config/arm/arm-mve-builtins-base.def (vaddlvq): New. * config/arm/arm-mve-builtins-base.h (vaddlvq): New. * config/arm/arm-mve-builtins-functions.h (unspec_mve_function_exact_insn_pred_p): Handle vaddlvq. * config/arm/arm_mve.h (vaddlvq): Remove. (vaddlvq_p): Remove. (vaddlvq_s32): Remove. (vaddlvq_u32): Remove. (vaddlvq_p_s32): Remove. (vaddlvq_p_u32): Remove. (__arm_vaddlvq_s32): Remove. (__arm_vaddlvq_u32): Remove. (__arm_vaddlvq_p_s32): Remove. (__arm_vaddlvq_p_u32): Remove. (__arm_vaddlvq): Remove. (__arm_vaddlvq_p): Remove.
2023-05-11arm: [MVE intrinsics] factorize vaddlvqChristophe Lyon2-4/+6
Factorize vaddlvq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddlv. * config/arm/mve.md (mve_vaddlvq_<supf>v4si): Rename into ... (@mve_<mve_insn>q_<supf>v4si): ... this. (mve_vaddlvq_p_<supf>v4si): Rename into ... (@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-11arm: [MVE intrinsics] add unary_acc shapeChristophe Lyon2-0/+29
This patch adds the unary_acc shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_acc): New. * config/arm/arm-mve-builtins-shapes.h (unary_acc): New.
2023-05-11arm: [MVE intrinsics] rework vaddvaqChristophe Lyon4-202/+3
Implement vaddvaq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vaddvaq): New. * config/arm/arm-mve-builtins-base.def (vaddvaq): New. * config/arm/arm-mve-builtins-base.h (vaddvaq): New. * config/arm/arm_mve.h (vaddvaq): Remove. (vaddvaq_p): Remove. (vaddvaq_u8): Remove. (vaddvaq_s8): Remove. (vaddvaq_u16): Remove. (vaddvaq_s16): Remove. (vaddvaq_u32): Remove. (vaddvaq_s32): Remove. (vaddvaq_p_u8): Remove. (vaddvaq_p_s8): Remove. (vaddvaq_p_u16): Remove. (vaddvaq_p_s16): Remove. (vaddvaq_p_u32): Remove. (vaddvaq_p_s32): Remove. (__arm_vaddvaq_u8): Remove. (__arm_vaddvaq_s8): Remove. (__arm_vaddvaq_u16): Remove. (__arm_vaddvaq_s16): Remove. (__arm_vaddvaq_u32): Remove. (__arm_vaddvaq_s32): Remove. (__arm_vaddvaq_p_u8): Remove. (__arm_vaddvaq_p_s8): Remove. (__arm_vaddvaq_p_u16): Remove. (__arm_vaddvaq_p_s16): Remove. (__arm_vaddvaq_p_u32): Remove. (__arm_vaddvaq_p_s32): Remove. (__arm_vaddvaq): Remove. (__arm_vaddvaq_p): Remove.
2023-05-11arm: [MVE intrinsics] add unary_int32_acc shapeChristophe Lyon2-0/+35
This patch adds the unary_int32_acc shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_int32_acc): New. * config/arm/arm-mve-builtins-shapes.h (unary_int32_acc): New.
2023-05-11arm: [MVE intrinsics] factorize vaddvaqChristophe Lyon2-4/+6
Factorize vaddvaq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddva. * config/arm/mve.md (mve_vaddvaq_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vaddvaq_p_<supf><mode>): Rename into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] rework vaddvqChristophe Lyon4-200/+3
Implement vaddvq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vaddvq): New. * config/arm/arm-mve-builtins-base.def (vaddvq): New. * config/arm/arm-mve-builtins-base.h (vaddvq): New. * config/arm/arm_mve.h (vaddvq): Remove. (vaddvq_p): Remove. (vaddvq_s8): Remove. (vaddvq_s16): Remove. (vaddvq_s32): Remove. (vaddvq_u8): Remove. (vaddvq_u16): Remove. (vaddvq_u32): Remove. (vaddvq_p_u8): Remove. (vaddvq_p_s8): Remove. (vaddvq_p_u16): Remove. (vaddvq_p_s16): Remove. (vaddvq_p_u32): Remove. (vaddvq_p_s32): Remove. (__arm_vaddvq_s8): Remove. (__arm_vaddvq_s16): Remove. (__arm_vaddvq_s32): Remove. (__arm_vaddvq_u8): Remove. (__arm_vaddvq_u16): Remove. (__arm_vaddvq_u32): Remove. (__arm_vaddvq_p_u8): Remove. (__arm_vaddvq_p_s8): Remove. (__arm_vaddvq_p_u16): Remove. (__arm_vaddvq_p_s16): Remove. (__arm_vaddvq_p_u32): Remove. (__arm_vaddvq_p_s32): Remove. (__arm_vaddvq): Remove. (__arm_vaddvq_p): Remove.
2023-05-11arm: [MVE intrinsics] add unary_int32 shapeChristophe Lyon2-0/+28
This patch adds the unary_int32 shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_int32): New. * config/arm/arm-mve-builtins-shapes.h (unary_int32): New.
2023-05-11arm: [MVE intrinsics] factorize vaddvqChristophe Lyon3-5/+7
Factorize vaddvq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddv. * config/arm/mve.md (@mve_vaddvq_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vaddvq_p_<supf><mode>): Rename into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this. * config/arm/vec-common.md: Use gen_mve_q instead of gen_mve_vaddvq.
2023-05-11arm: [MVE intrinsics] rework vdupqChristophe Lyon4-333/+13
Implement vdupq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N): New. (vdupq): New. * config/arm/arm-mve-builtins-base.def (vdupq): New. * config/arm/arm-mve-builtins-base.h: (vdupq): New. * config/arm/arm_mve.h (vdupq_n): Remove. (vdupq_m): Remove. (vdupq_n_f16): Remove. (vdupq_n_f32): Remove. (vdupq_n_s8): Remove. (vdupq_n_s16): Remove. (vdupq_n_s32): Remove. (vdupq_n_u8): Remove. (vdupq_n_u16): Remove. (vdupq_n_u32): Remove. (vdupq_m_n_u8): Remove. (vdupq_m_n_s8): Remove. (vdupq_m_n_u16): Remove. (vdupq_m_n_s16): Remove. (vdupq_m_n_u32): Remove. (vdupq_m_n_s32): Remove. (vdupq_m_n_f16): Remove. (vdupq_m_n_f32): Remove. (vdupq_x_n_s8): Remove. (vdupq_x_n_s16): Remove. (vdupq_x_n_s32): Remove. (vdupq_x_n_u8): Remove. (vdupq_x_n_u16): Remove. (vdupq_x_n_u32): Remove. (vdupq_x_n_f16): Remove. (vdupq_x_n_f32): Remove. (__arm_vdupq_n_s8): Remove. (__arm_vdupq_n_s16): Remove. (__arm_vdupq_n_s32): Remove. (__arm_vdupq_n_u8): Remove. (__arm_vdupq_n_u16): Remove. (__arm_vdupq_n_u32): Remove. (__arm_vdupq_m_n_u8): Remove. (__arm_vdupq_m_n_s8): Remove. (__arm_vdupq_m_n_u16): Remove. (__arm_vdupq_m_n_s16): Remove. (__arm_vdupq_m_n_u32): Remove. (__arm_vdupq_m_n_s32): Remove. (__arm_vdupq_x_n_s8): Remove. (__arm_vdupq_x_n_s16): Remove. (__arm_vdupq_x_n_s32): Remove. (__arm_vdupq_x_n_u8): Remove. (__arm_vdupq_x_n_u16): Remove. (__arm_vdupq_x_n_u32): Remove. (__arm_vdupq_n_f16): Remove. (__arm_vdupq_n_f32): Remove. (__arm_vdupq_m_n_f16): Remove. (__arm_vdupq_m_n_f32): Remove. (__arm_vdupq_x_n_f16): Remove. (__arm_vdupq_x_n_f32): Remove. (__arm_vdupq_n): Remove. (__arm_vdupq_m): Remove.
2023-05-11arm: [MVE intrinsics] add unary_n shapeChristophe Lyon2-0/+54
This patch adds the unary_n shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_n): New. * config/arm/arm-mve-builtins-shapes.h (unary_n): New.
2023-05-11arm: [MVE intrinsics] factorize vdupqChristophe Lyon2-10/+20
Factorize vdup builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_FP_M_N_VDUPQ_ONLY) (MVE_FP_N_VDUPQ_ONLY): New. (mve_insn): Add vdupq. * config/arm/mve.md (mve_vdupq_n_f<mode>): Rename into ... (@mve_<mve_insn>q_n_f<mode>): ... this. (mve_vdupq_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vdupq_m_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this. (mve_vdupq_m_n_f<mode>): Rename into ... (@mve_<mve_insn>q_m_n_f<mode>): ... this.
2023-05-11arm: [MVE intrinsics] rework vrev16q vrev32q vrev64qChristophe Lyon4-820/+11
Implement vrev16q, vrev32q, vrev64q using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q): New. * config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q) (vrev64q): New. * config/arm/arm-mve-builtins-base.h (vrev16q, vrev32q) (vrev64q): New. * config/arm/arm_mve.h (vrev16q): Remove. (vrev32q): Remove. (vrev64q): Remove. (vrev64q_m): Remove. (vrev16q_m): Remove. (vrev32q_m): Remove. (vrev16q_x): Remove. (vrev32q_x): Remove. (vrev64q_x): Remove. (vrev64q_f16): Remove. (vrev64q_f32): Remove. (vrev32q_f16): Remove. (vrev16q_s8): Remove. (vrev32q_s8): Remove. (vrev32q_s16): Remove. (vrev64q_s8): Remove. (vrev64q_s16): Remove. (vrev64q_s32): Remove. (vrev64q_u8): Remove. (vrev64q_u16): Remove. (vrev64q_u32): Remove. (vrev32q_u8): Remove. (vrev32q_u16): Remove. (vrev16q_u8): Remove. (vrev64q_m_u8): Remove. (vrev64q_m_s8): Remove. (vrev64q_m_u16): Remove. (vrev64q_m_s16): Remove. (vrev64q_m_u32): Remove. (vrev64q_m_s32): Remove. (vrev16q_m_s8): Remove. (vrev32q_m_f16): Remove. (vrev16q_m_u8): Remove. (vrev32q_m_s8): Remove. (vrev64q_m_f16): Remove. (vrev32q_m_u8): Remove. (vrev32q_m_s16): Remove. (vrev64q_m_f32): Remove. (vrev32q_m_u16): Remove. (vrev16q_x_s8): Remove. (vrev16q_x_u8): Remove. (vrev32q_x_s8): Remove. (vrev32q_x_s16): Remove. (vrev32q_x_u8): Remove. (vrev32q_x_u16): Remove. (vrev64q_x_s8): Remove. (vrev64q_x_s16): Remove. (vrev64q_x_s32): Remove. (vrev64q_x_u8): Remove. (vrev64q_x_u16): Remove. (vrev64q_x_u32): Remove. (vrev32q_x_f16): Remove. (vrev64q_x_f16): Remove. (vrev64q_x_f32): Remove. (__arm_vrev16q_s8): Remove. (__arm_vrev32q_s8): Remove. (__arm_vrev32q_s16): Remove. (__arm_vrev64q_s8): Remove. (__arm_vrev64q_s16): Remove. (__arm_vrev64q_s32): Remove. (__arm_vrev64q_u8): Remove. (__arm_vrev64q_u16): Remove. (__arm_vrev64q_u32): Remove. (__arm_vrev32q_u8): Remove. (__arm_vrev32q_u16): Remove. (__arm_vrev16q_u8): Remove. (__arm_vrev64q_m_u8): Remove. (__arm_vrev64q_m_s8): Remove. (__arm_vrev64q_m_u16): Remove. (__arm_vrev64q_m_s16): Remove. (__arm_vrev64q_m_u32): Remove. (__arm_vrev64q_m_s32): Remove. (__arm_vrev16q_m_s8): Remove. (__arm_vrev16q_m_u8): Remove. (__arm_vrev32q_m_s8): Remove. (__arm_vrev32q_m_u8): Remove. (__arm_vrev32q_m_s16): Remove. (__arm_vrev32q_m_u16): Remove. (__arm_vrev16q_x_s8): Remove. (__arm_vrev16q_x_u8): Remove. (__arm_vrev32q_x_s8): Remove. (__arm_vrev32q_x_s16): Remove. (__arm_vrev32q_x_u8): Remove. (__arm_vrev32q_x_u16): Remove. (__arm_vrev64q_x_s8): Remove. (__arm_vrev64q_x_s16): Remove. (__arm_vrev64q_x_s32): Remove. (__arm_vrev64q_x_u8): Remove. (__arm_vrev64q_x_u16): Remove. (__arm_vrev64q_x_u32): Remove. (__arm_vrev64q_f16): Remove. (__arm_vrev64q_f32): Remove. (__arm_vrev32q_f16): Remove. (__arm_vrev32q_m_f16): Remove. (__arm_vrev64q_m_f16): Remove. (__arm_vrev64q_m_f32): Remove. (__arm_vrev32q_x_f16): Remove. (__arm_vrev64q_x_f16): Remove. (__arm_vrev64q_x_f32): Remove. (__arm_vrev16q): Remove. (__arm_vrev32q): Remove. (__arm_vrev64q): Remove. (__arm_vrev64q_m): Remove. (__arm_vrev16q_m): Remove. (__arm_vrev32q_m): Remove. (__arm_vrev16q_x): Remove. (__arm_vrev32q_x): Remove. (__arm_vrev64q_x): Remove.
2023-05-11arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64qChristophe Lyon2-36/+61
Factorize vrev16q vrev32q vrev64q so that they use generic builtin names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_V8HF, MVE_V16QI) (MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY) (MVE_FP_M_VREV32Q_ONLY): New iterators. (mve_insn): Add vrev16q, vrev32q, vrev64q. * config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ... (@mve_<mve_insn>q_f<mode>): ... this (mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>. (mve_vrev64q_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vrev32q_<supf><mode>): Rename into @mve_<mve_insn>q_<supf><mode>. (mve_vrev16q_<supf>v16qi): Rename into @mve_<mve_insn>q_<supf><mode>. (mve_vrev64q_m_<supf><mode>): Rename into @mve_<mve_insn>q_m_<supf><mode>. (mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>. (mve_vrev32q_m_<supf><mode>): Rename into @mve_<mve_insn>q_m_<supf><mode>. (mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>. (mve_vrev16q_m_<supf>v16qi): Rename into @mve_<mve_insn>q_m_<supf><mode>.
2023-05-11arm: [MVE intrinsics] rework vcmpChristophe Lyon6-2930/+149
Implement vcmp using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vcmpeqq, vcmpneq, vcmpgeq) (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New. * config/arm/arm-mve-builtins-base.def (vcmpeqq, vcmpneq, vcmpgeq) (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New. * config/arm/arm-mve-builtins-base.h (vcmpeqq, vcmpneq, vcmpgeq) (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New. * config/arm/arm-mve-builtins-functions.h (class unspec_based_mve_function_exact_insn_vcmp): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vcmp. * config/arm/arm_mve.h (vcmpneq): Remove. (vcmphiq): Remove. (vcmpeqq): Remove. (vcmpcsq): Remove. (vcmpltq): Remove. (vcmpleq): Remove. (vcmpgtq): Remove. (vcmpgeq): Remove. (vcmpneq_m): Remove. (vcmphiq_m): Remove. (vcmpeqq_m): Remove. (vcmpcsq_m): Remove. (vcmpcsq_m_n): Remove. (vcmpltq_m): Remove. (vcmpleq_m): Remove. (vcmpgtq_m): Remove. (vcmpgeq_m): Remove. (vcmpneq_s8): Remove. (vcmpneq_s16): Remove. (vcmpneq_s32): Remove. (vcmpneq_u8): Remove. (vcmpneq_u16): Remove. (vcmpneq_u32): Remove. (vcmpneq_n_u8): Remove. (vcmphiq_u8): Remove. (vcmphiq_n_u8): Remove. (vcmpeqq_u8): Remove. (vcmpeqq_n_u8): Remove. (vcmpcsq_u8): Remove. (vcmpcsq_n_u8): Remove. (vcmpneq_n_s8): Remove. (vcmpltq_s8): Remove. (vcmpltq_n_s8): Remove. (vcmpleq_s8): Remove. (vcmpleq_n_s8): Remove. (vcmpgtq_s8): Remove. (vcmpgtq_n_s8): Remove. (vcmpgeq_s8): Remove. (vcmpgeq_n_s8): Remove. (vcmpeqq_s8): Remove. (vcmpeqq_n_s8): Remove. (vcmpneq_n_u16): Remove. (vcmphiq_u16): Remove. (vcmphiq_n_u16): Remove. (vcmpeqq_u16): Remove. (vcmpeqq_n_u16): Remove. (vcmpcsq_u16): Remove. (vcmpcsq_n_u16): Remove. (vcmpneq_n_s16): Remove. (vcmpltq_s16): Remove. (vcmpltq_n_s16): Remove. (vcmpleq_s16): Remove. (vcmpleq_n_s16): Remove. (vcmpgtq_s16): Remove. (vcmpgtq_n_s16): Remove. (vcmpgeq_s16): Remove. (vcmpgeq_n_s16): Remove. (vcmpeqq_s16): Remove. (vcmpeqq_n_s16): Remove. (vcmpneq_n_u32): Remove. (vcmphiq_u32): Remove. (vcmphiq_n_u32): Remove. (vcmpeqq_u32): Remove. (vcmpeqq_n_u32): Remove. (vcmpcsq_u32): Remove. (vcmpcsq_n_u32): Remove. (vcmpneq_n_s32): Remove. (vcmpltq_s32): Remove. (vcmpltq_n_s32): Remove. (vcmpleq_s32): Remove. (vcmpleq_n_s32): Remove. (vcmpgtq_s32): Remove. (vcmpgtq_n_s32): Remove. (vcmpgeq_s32): Remove. (vcmpgeq_n_s32): Remove. (vcmpeqq_s32): Remove. (vcmpeqq_n_s32): Remove. (vcmpneq_n_f16): Remove. (vcmpneq_f16): Remove. (vcmpltq_n_f16): Remove. (vcmpltq_f16): Remove. (vcmpleq_n_f16): Remove. (vcmpleq_f16): Remove. (vcmpgtq_n_f16): Remove. (vcmpgtq_f16): Remove. (vcmpgeq_n_f16): Remove. (vcmpgeq_f16): Remove. (vcmpeqq_n_f16): Remove. (vcmpeqq_f16): Remove. (vcmpneq_n_f32): Remove. (vcmpneq_f32): Remove. (vcmpltq_n_f32): Remove. (vcmpltq_f32): Remove. (vcmpleq_n_f32): Remove. (vcmpleq_f32): Remove. (vcmpgtq_n_f32): Remove. (vcmpgtq_f32): Remove. (vcmpgeq_n_f32): Remove. (vcmpgeq_f32): Remove. (vcmpeqq_n_f32): Remove. (vcmpeqq_f32): Remove. (vcmpeqq_m_f16): Remove. (vcmpeqq_m_f32): Remove. (vcmpneq_m_u8): Remove. (vcmpneq_m_n_u8): Remove. (vcmphiq_m_u8): Remove. (vcmphiq_m_n_u8): Remove. (vcmpeqq_m_u8): Remove. (vcmpeqq_m_n_u8): Remove. (vcmpcsq_m_u8): Remove. (vcmpcsq_m_n_u8): Remove. (vcmpneq_m_s8): Remove. (vcmpneq_m_n_s8): Remove. (vcmpltq_m_s8): Remove. (vcmpltq_m_n_s8): Remove. (vcmpleq_m_s8): Remove. (vcmpleq_m_n_s8): Remove. (vcmpgtq_m_s8): Remove. (vcmpgtq_m_n_s8): Remove. (vcmpgeq_m_s8): Remove. (vcmpgeq_m_n_s8): Remove. (vcmpeqq_m_s8): Remove. (vcmpeqq_m_n_s8): Remove. (vcmpneq_m_u16): Remove. (vcmpneq_m_n_u16): Remove. (vcmphiq_m_u16): Remove. (vcmphiq_m_n_u16): Remove. (vcmpeqq_m_u16): Remove. (vcmpeqq_m_n_u16): Remove. (vcmpcsq_m_u16): Remove. (vcmpcsq_m_n_u16): Remove. (vcmpneq_m_s16): Remove. (vcmpneq_m_n_s16): Remove. (vcmpltq_m_s16): Remove. (vcmpltq_m_n_s16): Remove. (vcmpleq_m_s16): Remove. (vcmpleq_m_n_s16): Remove. (vcmpgtq_m_s16): Remove. (vcmpgtq_m_n_s16): Remove. (vcmpgeq_m_s16): Remove. (vcmpgeq_m_n_s16): Remove. (vcmpeqq_m_s16): Remove. (vcmpeqq_m_n_s16): Remove. (vcmpneq_m_u32): Remove. (vcmpneq_m_n_u32): Remove. (vcmphiq_m_u32): Remove. (vcmphiq_m_n_u32): Remove. (vcmpeqq_m_u32): Remove. (vcmpeqq_m_n_u32): Remove. (vcmpcsq_m_u32): Remove. (vcmpcsq_m_n_u32): Remove. (vcmpneq_m_s32): Remove. (vcmpneq_m_n_s32): Remove. (vcmpltq_m_s32): Remove. (vcmpltq_m_n_s32): Remove. (vcmpleq_m_s32): Remove. (vcmpleq_m_n_s32): Remove. (vcmpgtq_m_s32): Remove. (vcmpgtq_m_n_s32): Remove. (vcmpgeq_m_s32): Remove. (vcmpgeq_m_n_s32): Remove. (vcmpeqq_m_s32): Remove. (vcmpeqq_m_n_s32): Remove. (vcmpeqq_m_n_f16): Remove. (vcmpgeq_m_f16): Remove. (vcmpgeq_m_n_f16): Remove. (vcmpgtq_m_f16): Remove. (vcmpgtq_m_n_f16): Remove. (vcmpleq_m_f16): Remove. (vcmpleq_m_n_f16): Remove. (vcmpltq_m_f16): Remove. (vcmpltq_m_n_f16): Remove. (vcmpneq_m_f16): Remove. (vcmpneq_m_n_f16): Remove. (vcmpeqq_m_n_f32): Remove. (vcmpgeq_m_f32): Remove. (vcmpgeq_m_n_f32): Remove. (vcmpgtq_m_f32): Remove. (vcmpgtq_m_n_f32): Remove. (vcmpleq_m_f32): Remove. (vcmpleq_m_n_f32): Remove. (vcmpltq_m_f32): Remove. (vcmpltq_m_n_f32): Remove. (vcmpneq_m_f32): Remove. (vcmpneq_m_n_f32): Remove. (__arm_vcmpneq_s8): Remove. (__arm_vcmpneq_s16): Remove. (__arm_vcmpneq_s32): Remove. (__arm_vcmpneq_u8): Remove. (__arm_vcmpneq_u16): Remove. (__arm_vcmpneq_u32): Remove. (__arm_vcmpneq_n_u8): Remove. (__arm_vcmphiq_u8): Remove. (__arm_vcmphiq_n_u8): Remove. (__arm_vcmpeqq_u8): Remove. (__arm_vcmpeqq_n_u8): Remove. (__arm_vcmpcsq_u8): Remove. (__arm_vcmpcsq_n_u8): Remove. (__arm_vcmpneq_n_s8): Remove. (__arm_vcmpltq_s8): Remove. (__arm_vcmpltq_n_s8): Remove. (__arm_vcmpleq_s8): Remove. (__arm_vcmpleq_n_s8): Remove. (__arm_vcmpgtq_s8): Remove. (__arm_vcmpgtq_n_s8): Remove. (__arm_vcmpgeq_s8): Remove. (__arm_vcmpgeq_n_s8): Remove. (__arm_vcmpeqq_s8): Remove. (__arm_vcmpeqq_n_s8): Remove. (__arm_vcmpneq_n_u16): Remove. (__arm_vcmphiq_u16): Remove. (__arm_vcmphiq_n_u16): Remove. (__arm_vcmpeqq_u16): Remove. (__arm_vcmpeqq_n_u16): Remove. (__arm_vcmpcsq_u16): Remove. (__arm_vcmpcsq_n_u16): Remove. (__arm_vcmpneq_n_s16): Remove. (__arm_vcmpltq_s16): Remove. (__arm_vcmpltq_n_s16): Remove. (__arm_vcmpleq_s16): Remove. (__arm_vcmpleq_n_s16): Remove. (__arm_vcmpgtq_s16): Remove. (__arm_vcmpgtq_n_s16): Remove. (__arm_vcmpgeq_s16): Remove. (__arm_vcmpgeq_n_s16): Remove. (__arm_vcmpeqq_s16): Remove. (__arm_vcmpeqq_n_s16): Remove. (__arm_vcmpneq_n_u32): Remove. (__arm_vcmphiq_u32): Remove. (__arm_vcmphiq_n_u32): Remove. (__arm_vcmpeqq_u32): Remove. (__arm_vcmpeqq_n_u32): Remove. (__arm_vcmpcsq_u32): Remove. (__arm_vcmpcsq_n_u32): Remove. (__arm_vcmpneq_n_s32): Remove. (__arm_vcmpltq_s32): Remove. (__arm_vcmpltq_n_s32): Remove. (__arm_vcmpleq_s32): Remove. (__arm_vcmpleq_n_s32): Remove. (__arm_vcmpgtq_s32): Remove. (__arm_vcmpgtq_n_s32): Remove. (__arm_vcmpgeq_s32): Remove. (__arm_vcmpgeq_n_s32): Remove. (__arm_vcmpeqq_s32): Remove. (__arm_vcmpeqq_n_s32): Remove. (__arm_vcmpneq_m_u8): Remove. (__arm_vcmpneq_m_n_u8): Remove. (__arm_vcmphiq_m_u8): Remove. (__arm_vcmphiq_m_n_u8): Remove. (__arm_vcmpeqq_m_u8): Remove. (__arm_vcmpeqq_m_n_u8): Remove. (__arm_vcmpcsq_m_u8): Remove. (__arm_vcmpcsq_m_n_u8): Remove. (__arm_vcmpneq_m_s8): Remove. (__arm_vcmpneq_m_n_s8): Remove. (__arm_vcmpltq_m_s8): Remove. (__arm_vcmpltq_m_n_s8): Remove. (__arm_vcmpleq_m_s8): Remove. (__arm_vcmpleq_m_n_s8): Remove. (__arm_vcmpgtq_m_s8): Remove. (__arm_vcmpgtq_m_n_s8): Remove. (__arm_vcmpgeq_m_s8): Remove. (__arm_vcmpgeq_m_n_s8): Remove. (__arm_vcmpeqq_m_s8): Remove. (__arm_vcmpeqq_m_n_s8): Remove. (__arm_vcmpneq_m_u16): Remove. (__arm_vcmpneq_m_n_u16): Remove. (__arm_vcmphiq_m_u16): Remove. (__arm_vcmphiq_m_n_u16): Remove. (__arm_vcmpeqq_m_u16): Remove. (__arm_vcmpeqq_m_n_u16): Remove. (__arm_vcmpcsq_m_u16): Remove. (__arm_vcmpcsq_m_n_u16): Remove. (__arm_vcmpneq_m_s16): Remove. (__arm_vcmpneq_m_n_s16): Remove. (__arm_vcmpltq_m_s16): Remove. (__arm_vcmpltq_m_n_s16): Remove. (__arm_vcmpleq_m_s16): Remove. (__arm_vcmpleq_m_n_s16): Remove. (__arm_vcmpgtq_m_s16): Remove. (__arm_vcmpgtq_m_n_s16): Remove. (__arm_vcmpgeq_m_s16): Remove. (__arm_vcmpgeq_m_n_s16): Remove. (__arm_vcmpeqq_m_s16): Remove. (__arm_vcmpeqq_m_n_s16): Remove. (__arm_vcmpneq_m_u32): Remove. (__arm_vcmpneq_m_n_u32): Remove. (__arm_vcmphiq_m_u32): Remove. (__arm_vcmphiq_m_n_u32): Remove. (__arm_vcmpeqq_m_u32): Remove. (__arm_vcmpeqq_m_n_u32): Remove. (__arm_vcmpcsq_m_u32): Remove. (__arm_vcmpcsq_m_n_u32): Remove. (__arm_vcmpneq_m_s32): Remove. (__arm_vcmpneq_m_n_s32): Remove. (__arm_vcmpltq_m_s32): Remove. (__arm_vcmpltq_m_n_s32): Remove. (__arm_vcmpleq_m_s32): Remove. (__arm_vcmpleq_m_n_s32): Remove. (__arm_vcmpgtq_m_s32): Remove. (__arm_vcmpgtq_m_n_s32): Remove. (__arm_vcmpgeq_m_s32): Remove. (__arm_vcmpgeq_m_n_s32): Remove. (__arm_vcmpeqq_m_s32): Remove. (__arm_vcmpeqq_m_n_s32): Remove. (__arm_vcmpneq_n_f16): Remove. (__arm_vcmpneq_f16): Remove. (__arm_vcmpltq_n_f16): Remove. (__arm_vcmpltq_f16): Remove. (__arm_vcmpleq_n_f16): Remove. (__arm_vcmpleq_f16): Remove. (__arm_vcmpgtq_n_f16): Remove. (__arm_vcmpgtq_f16): Remove. (__arm_vcmpgeq_n_f16): Remove. (__arm_vcmpgeq_f16): Remove. (__arm_vcmpeqq_n_f16): Remove. (__arm_vcmpeqq_f16): Remove. (__arm_vcmpneq_n_f32): Remove. (__arm_vcmpneq_f32): Remove. (__arm_vcmpltq_n_f32): Remove. (__arm_vcmpltq_f32): Remove. (__arm_vcmpleq_n_f32): Remove. (__arm_vcmpleq_f32): Remove. (__arm_vcmpgtq_n_f32): Remove. (__arm_vcmpgtq_f32): Remove. (__arm_vcmpgeq_n_f32): Remove. (__arm_vcmpgeq_f32): Remove. (__arm_vcmpeqq_n_f32): Remove. (__arm_vcmpeqq_f32): Remove. (__arm_vcmpeqq_m_f16): Remove. (__arm_vcmpeqq_m_f32): Remove. (__arm_vcmpeqq_m_n_f16): Remove. (__arm_vcmpgeq_m_f16): Remove. (__arm_vcmpgeq_m_n_f16): Remove. (__arm_vcmpgtq_m_f16): Remove. (__arm_vcmpgtq_m_n_f16): Remove. (__arm_vcmpleq_m_f16): Remove. (__arm_vcmpleq_m_n_f16): Remove. (__arm_vcmpltq_m_f16): Remove. (__arm_vcmpltq_m_n_f16): Remove. (__arm_vcmpneq_m_f16): Remove. (__arm_vcmpneq_m_n_f16): Remove. (__arm_vcmpeqq_m_n_f32): Remove. (__arm_vcmpgeq_m_f32): Remove. (__arm_vcmpgeq_m_n_f32): Remove. (__arm_vcmpgtq_m_f32): Remove. (__arm_vcmpgtq_m_n_f32): Remove. (__arm_vcmpleq_m_f32): Remove. (__arm_vcmpleq_m_n_f32): Remove. (__arm_vcmpltq_m_f32): Remove. (__arm_vcmpltq_m_n_f32): Remove. (__arm_vcmpneq_m_f32): Remove. (__arm_vcmpneq_m_n_f32): Remove. (__arm_vcmpneq): Remove. (__arm_vcmphiq): Remove. (__arm_vcmpeqq): Remove. (__arm_vcmpcsq): Remove. (__arm_vcmpltq): Remove. (__arm_vcmpleq): Remove. (__arm_vcmpgtq): Remove. (__arm_vcmpgeq): Remove. (__arm_vcmpneq_m): Remove. (__arm_vcmphiq_m): Remove. (__arm_vcmpeqq_m): Remove. (__arm_vcmpcsq_m): Remove. (__arm_vcmpltq_m): Remove. (__arm_vcmpleq_m): Remove. (__arm_vcmpgtq_m): Remove. (__arm_vcmpgeq_m): Remove.
2023-05-11arm: [MVE intrinsics] add cmp shapeChristophe Lyon2-0/+28
This patch adds the cmp shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (cmp): New. * config/arm/arm-mve-builtins-shapes.h (cmp): New.
2023-05-11arm: [MVE intrinsics] factorize vcmpChristophe Lyon2-387/+135
Factorize vcmp so that they use the same pattern. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N) (MVE_CMP_M_N_F, mve_cmp_op1): New. (isu): Add VCMP* (supf): Likewise. * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>): Rename into ... (@mve_vcmp<mve_cmp_op>q_n_<mode>): ... this. (mve_vcmpeqq_m_f<mode>, mve_vcmpgeq_m_f<mode>) (mve_vcmpgtq_m_f<mode>, mve_vcmpleq_m_f<mode>) (mve_vcmpltq_m_f<mode>, mve_vcmpneq_m_f<mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_f<mode>): ... this. (mve_vcmpcsq_m_u<mode>, mve_vcmpeqq_m_<supf><mode>) (mve_vcmpgeq_m_s<mode>, mve_vcmpgtq_m_s<mode>) (mve_vcmphiq_m_u<mode>, mve_vcmpleq_m_s<mode>) (mve_vcmpltq_m_s<mode>, mve_vcmpneq_m_<supf><mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>): ... this. (mve_vcmpcsq_m_n_u<mode>, mve_vcmpeqq_m_n_<supf><mode>) (mve_vcmpgeq_m_n_s<mode>, mve_vcmpgtq_m_n_s<mode>) (mve_vcmphiq_m_n_u<mode>, mve_vcmpleq_m_n_s<mode>) (mve_vcmpltq_m_n_s<mode>, mve_vcmpneq_m_n_<supf><mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>): ... this. (mve_vcmpeqq_m_n_f<mode>, mve_vcmpgeq_m_n_f<mode>) (mve_vcmpgtq_m_n_f<mode>, mve_vcmpleq_m_n_f<mode>) (mve_vcmpltq_m_n_f<mode>, mve_vcmpneq_m_n_f<mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>): ... this.
2023-05-11Testsuite: Add 'torture-init-done', and use it to conditionalize implicit ↵Thomas Schwinge5-8/+30
'torture-init' Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1 "Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'" made 'torture-init' non-idempotent re 'LTO_TORTURE_OPTIONS', in order to catch certain classes of errors. Now, most of all '*.exp' files have 'torture-init' followed by 'set-torture-options' before 'gcc-dg-runtest' etc., and therefore don't run into the latter's "Some callers set torture options themselves; don't override those." code. Some '*.exp' files however do 'torture-init' but not 'set-torture-options', and therefore we can't any longer conditionalize the implicit 'torture-init' by '![torture-options-exist]'. gcc/testsuite/ * lib/torture-options.exp (torture-init-done): Add. * lib/gcc-dg.exp (gcc-dg-runtest): Use it to conditionalize implicit 'torture-init'. * lib/gfortran-dg.exp (gfortran-dg-runtest): Likewise. * lib/obj-c++-dg.exp (obj-c++-dg-runtest): Likewise. * lib/objc-dg.exp (objc-dg-runtest): Likewise.
2023-05-11Testsuite: Add missing 'torture-init'/'torture-finish' around ↵Thomas Schwinge3-0/+7
'LTO_TORTURE_OPTIONS' usage Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1 "Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'" made it a requirement that 'LTO_TORTURE_OPTIONS' usage be within 'torture-init'/'torture-finish', and missed a few cases that didn't have that. gcc/testsuite/ * gcc.target/arm/acle/acle.exp: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage. * gcc.target/arm/cmse/cmse.exp: Likewise. * gcc.target/arm/pure-code/pure-code.exp: Likewise.
2023-05-11match.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y)Roger Sayle4-0/+100
This patch teaches match.pd to simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y), and the related simplifications that popcount(X)+popcount(Y)-popcount(X&Y) is popcount(X|Y). As surprising as it might seem, this idiom is common in cheminformatics codes (for Tanimoto coefficient calculations). 2023-05-11 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * match.pd <popcount optimizations>: Simplify popcount(X|Y) + popcount(X&Y) as popcount(X)+popcount(Y). Likewise, simplify popcount(X)+popcount(Y)-popcount(X&Y) as popcount(X|Y), and vice versa. gcc/testsuite/ChangeLog * gcc.dg/fold-popcount-8.c: New test case. * gcc.dg/fold-popcount-9.c: Likewise. * gcc.dg/fold-popcount-10.c: Likewise.
2023-05-11match.pd: Simplify popcount/parity of bswap/rotate.Roger Sayle5-0/+210
This is the latest iteration of my patch from August 2020 https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552391.html incorperating feedback and suggestions from reviewers. This patch to match.pd optimizes away bit permutation operations, specifically bswap and rotate, in calls to popcount and parity. 2023-05-11 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * match.pd <popcount optimizations>: Simplify popcount(bswap(x)) as popcount(x). Simplify popcount(rotate(x,y)) as popcount(x). <parity optimizations>: Simplify parity(bswap(x)) as parity(x). Simplify parity(rotate(x,y)) as parity(x). gcc/testsuite/ChangeLog * gcc.dg/fold-parity-6.c: New test. * gcc.dg/fold-parity-7.c: Likewise. * gcc.dg/fold-popcount-6.c: Likewise. * gcc.dg/fold-popcount-7.c: Likewise.
2023-05-11RISC-V: Support const series vector for RVV auto-vectorizationJuzhe-Zhong6-4/+236
This patch is the prerequiste patch for more RVV auto-vectorization support. Since when we enable a very simple binary operations, we will end up with such following ICE: during RTL pass: expand add_run-1.c: In function 'main': add_run-1.c:28:1: internal compiler error: Segmentation fault 0x1618ea3 crash_signal ../../../riscv-gcc/gcc/toplev.cc:314 0xe76cd9 single_set(rtx_insn const*) ../../../riscv-gcc/gcc/rtl.h:3602 0x1080f8a emit_move_insn(rtx_def*, rtx_def*) ../../../riscv-gcc/gcc/expr.cc:4342 0x170c458 insert_value_copy_on_edge ../../../riscv-gcc/gcc/tree-outof-ssa.cc:352 0x170d58e eliminate_phi ../../../riscv-gcc/gcc/tree-outof-ssa.cc:785 0x170df17 expand_phi_nodes(ssaexpand*) ../../../riscv-gcc/gcc/tree-outof-ssa.cc:1024 0xef27e2 execute ../../../riscv-gcc/gcc/cfgexpand.cc:6818 This is because LoopVectorizer assume target is able to handle series const vector when we enable binary operations. Then it will be easily causing ICE like that. gcc/ChangeLog: * config/riscv/autovec.md (@vec_series<mode>): New pattern * config/riscv/riscv-protos.h (expand_vec_series): New function. * config/riscv/riscv-v.cc (emit_binop): Ditto. (emit_index_op): Ditto. (expand_vec_series): Ditto. (expand_const_vector): Add series vector handling. * config/riscv/riscv.cc (riscv_const_insns): Enable series vector for testing. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/series-1.c: New test. * gcc.target/riscv/rvv/autovec/series_run-1.c: New test.
2023-05-11Daily bump.GCC Administrator5-1/+245
2023-05-10c++: wrong std::is_convertible with cv-qual fn [PR109680]Marek Polacek2-4/+51
This PR points out that std::is_convertible has given the wrong answer in static_assert (!std::is_convertible_v <int () const, int (*) ()>, ""); since r13-2822 implemented __is_{,nothrow_}convertible. std::is_convertible uses the imaginary To test() { return std::declval<From>(); } to do its job. Here, From is 'int () const'. std::declval is defined as: template<class T> typename std::add_rvalue_reference<T>::type declval() noexcept; std::add_rvalue_reference is defined as "If T is a function type that has no cv- or ref- qualifier or an object type, provides a member typedef type which is T&&, otherwise type is T." In our case, T is cv-qualified, so the result is T, so we end up with int () const declval() noexcept; which is invalid. In other words, this is pretty much like: using T = int () const; T fn1(); // bad, fn returning a fn T& fn2(); // bad, cannot declare reference to qualified function type T* fn3(); // bad, cannot declare pointer to qualified function type using U = int (); U fn4(); // bad, fn returning a fn U& fn5(); // OK U* fn6(); // OK I think is_convertible_helper needs to simulate std::declval better. To that end, I'm introducing build_trait_object, to be used where a declval is needed. PR c++/109680 gcc/cp/ChangeLog: * method.cc (build_trait_object): New. (assignable_expr): Use it. (ref_xes_from_temporary): Likewise. (is_convertible_helper): Likewise. Check FUNC_OR_METHOD_TYPE_P. gcc/testsuite/ChangeLog: * g++.dg/ext/is_convertible6.C: New test.
2023-05-10Use [(const_int 0)] idiom consistently in i386.mdRoger Sayle1-7/+7
This cleans up the use of [(clobber (const_int 0))] in the i386 backend. 2023-05-10 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/i386/i386.md (*concat<mode><dwi>3_1): Use preferred [(const_int 0)] idiom, instead of [(clobber (const_int 0))]. (*concat<mode><dwi>3_2): Likewise. (*concat<mode><dwi>3_3): Likewise. (*concat<mode><dwi>3_4): Likewise. (*concat<mode><dwi>3_5): Likewise. (*concat<mode><dwi>3_6): Likewise. (*concat<mode><dwi>3_7): Likewise.
2023-05-10c++: adjust conversion diagnosticsJason Merrill1-11/+9
While looking at PR109247 I made this change to improve diagnostics. I don't think I'm going ahead with that patch, but this still seems like a worthy cleanup. gcc/cp/ChangeLog: * call.cc (convert_like_internal): Share ck_ref_bind handling between all bad conversions.
2023-05-10i386: Add missing vector extend patterns [PR92658]Uros Bizjak3-0/+159
Add missing insn pattern for v2qi -> v2si vector extend and named expanders to activate generation of vector extends to 8-byte and 4-byte vectors. gcc/ChangeLog: PR target/92658 * config/i386/mmx.md (sse4_1_<code>v2qiv2si2): New insn pattern. (<insn>v4qiv4hi2): New expander. (<insn>v2hiv2si2): Ditto. (<insn>v2qiv2si2): Ditto. (<insn>v2qiv2hi2): Ditto. gcc/testsuite/ChangeLog: PR target/92658 * gcc.target/i386/pr92658-sse4-4b.c: New test. * gcc.target/i386/pr92658-sse4-8b.c: New test.
2023-05-10Fortran: dump-parse-tree: Mark debug functions with DEBUG_FUNCTIONBernhard Reutner-Fischer1-16/+22
gcc/fortran/ChangeLog: * dump-parse-tree.cc (gfc_debug_expr): Remove forward declaration. (debug): Add DEBUG_FUNCTION. (show_code_node): Remove erroneous whitespace.
2023-05-10Fortran: dump-parse-tree attribs: fix unbalanced braces [PR109624]Bernhard Reutner-Fischer1-3/+13
gcc/fortran/ChangeLog: PR fortran/109624 * dump-parse-tree.cc (debug): New function for gfc_namespace. (gfc_debug_code): Delete forward declaration. (show_attr): Make sure to print balanced braces.
2023-05-10Add another new testcaseAndrew Pinski1-0/+34
While working on improving min/max detection, this code (which is reduced from worse_state in ipa-pure-const.cc) was being miscompiled. Since there was no testcase in the testsuite yet for this, this patch adds one. Committed as obvious after testing the testcase via: make check-gcc RUNTESTFLAGS="execute.exp=20230510-1.c" gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20230510-1.c: New test.
2023-05-10c++: be stricter about constinit [CWG2543]Jason Merrill3-24/+48
DR 2543 clarifies that constinit variables should follow the language, and diagnose non-constant initializers (according to [expr.const]) even if they can actually initialize the variables statically. DR 2543 gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_outermost_constant_expr): Preserve TARGET_EXPR flags. (potential_constant_expression_1): Check TARGET_EXPR_ELIDING_P. * typeck2.cc (store_init_value): Diagnose constinit sooner. gcc/testsuite/ChangeLog: * g++.dg/DRs/dr2543.C: New test.
2023-05-10c++: always check consteval addressJason Merrill6-26/+37
The restriction on the "permitted result of a constant expression" to not refer to an immediate function applies regardless of context. The previous code tried to only check in cases where we wouldn't get the check in cp_fold_r, but with the next patch I would need to add another case and it shouldn't be a problem to always check. We also shouldn't talk about immediate evaluation when we aren't dealing with one. gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_outermost_constant_expr): Always check for address of immediate fn. (maybe_constant_init_1): Evaluate PTRMEM_CST. gcc/testsuite/ChangeLog: * g++.dg/DRs/dr2478.C: Handle -fimplicit-constexpr. * g++.dg/cpp23/consteval-if12.C: Adjust diagnostics. * g++.dg/cpp2a/consteval20.C: Likewise. * g++.dg/cpp2a/consteval24.C: Likewise. * g++.dg/cpp2a/srcloc20.C: Likewise.
2023-05-10Avoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABIRichard Biener1-0/+9
The following forces the g++.dg/torture/pr106922.C testcase to use the C++11 libstdc++ ABI and checks whether that worked. gcc/testsuite/ * g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1.
2023-05-10Fix a couple constraints on the H8 in preparation for LRA conversionJeff Law1-2/+2
So this is the 2nd patch on the way to LRA for the H8. LRA is more sensitive to getting define_constraint vs define_memory_constraint vs define_special_memory_constraint correct. than reload. The H8 port has the "Q" constraint, which is used to indicate memory addresses that can be used under certain circumstances in various ALU operations. So it should be a memory constraint. Ideally it'd would be a simple memory constraint, but it's used in contexts where MEMs are valid only for certain parts in the H8 family. So it really needs to be a special_memory_constraint. The "Zz" constraint accepts memory, but the forms are limited and can not be reloaded into a register. It seems to be working, but I wouldn't be totally surprised if this got stressed in the right way if it broke. Anyway, this patch fixes "Q" and "Zz" to be special memory constraints. Regression tested with gdbsim and pushed to the trunk. gcc * config/h8300/constraints.md (Q): Make this a special memory constraint. (Zz): Similarly.
2023-05-10ipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatchesJakub Jelinek1-1/+1
The PR contains a testcase where the Fortran FE creates FUNCTION_TYPE which doesn't really match the passed in arguments (FUNCTION_TYPE has 5 arguments, call has 6). Now, I think that is a Fortran FE bug that should be fixed there, but I think with function pointers one can create something similar (of course invalid) in C/C++ too,so IMHO IPA should be also more careful. The ipa_get_callee_param_type function can return NULL if something goes wrong and it does e.g. if asked for 7th argument type on a function with just 5 arguments and similar. But, if a function isn't varargs, when asked for 6th argument type on a function with just 5 arguments it actually returns void_type_node because the argument list is in that case terminated with void_list_node. The following patch makes sure we don't treat void_list_node as something holding another argument. 2023-05-10 Jakub Jelinek <jakub@redhat.com> PR fortran/109788 * ipa-prop.cc (ipa_get_callee_param_type): Don't return TREE_VALUE (t) if t is void_list_node.
2023-05-10aarch64: Simplify sqmovun expanderKyrylo Tkachov2-40/+13
This patch is a no-op as it removes the explicit vec-concat-zero patterns in favour of vczle/vczbe. This allows us to delete the explicit expander too. Tests are added to ensure the optimisation required still triggers. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>_insn_le): Delete. (aarch64_sqmovun<mode>_insn_be): Delete. (aarch64_sqmovun<mode><vczle><vczbe>): New define_insn. (aarch64_sqmovun<mode>): Delete expander. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/pr99195_4.c: Add tests for sqmovun.
2023-05-10[PATCH] aarch64: PR target/99195 annotate simple permutation patterns for ↵Kyrylo Tkachov2-8/+16
vec-concat-zero Another straightforward patch annotating patterns for the zip1, zip2, uzp1, uzp2, rev* instructions, plus tests. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_<PERMUTE:perm_insn><mode>): Rename to... (aarch64_<PERMUTE:perm_insn><mode><vczle><vczbe>): ... This. (aarch64_rev<REVERSE:rev_op><mode>): Rename to... (aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add tests for zip and rev intrinsics.
2023-05-10aarch64: PR target/99195 annotate simple saturating add/sub patterns for ↵Kyrylo Tkachov3-11/+41
vec-concat-zero Moving onto the saturating instructions, this one goes through the simple add/sub ones. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_<su_optab>q<addsub><mode>): Rename to... (aarch64_<su_optab>q<addsub><mode><vczle><vczbe>): ... This. (aarch64_<sur>qadd<mode>): Rename to... (aarch64_<sur>qadd<mode><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add testing for qadd, qsub. * gcc.target/aarch64/simd/pr99195_6.c: New test.
2023-05-10aarch64: Simplify QSHRN expanders and patternsKyrylo Tkachov2-34/+50
This patch deletes the explicit BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN patterns for the QSHRN instructions in favour of annotating a single one with <vczle><vczbe>. This allows simplification of the expander too. Tests are added to ensure that we still optimise away the concat-with-zero use case. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): Delete. (aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): Delete. (aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): New define_insn. (aarch64_<sur>q<r>shr<u>n_n<mode>): Simplify expander. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/pr99195_5.c: New test.
2023-05-10aarch64: PR target/99195 annotate simple narrowing patterns for vec-concat-zeroKyrylo Tkachov2-84/+37
This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN instructions. Using the <vczle><vczbe> attributes we can remove the BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN cases, as well as the intrinsic expanders that select between the two. Tests are also added. Thankfully the diffstat comes out negative \O/. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Delete. (aarch64_xtn<mode>_insn_be): Likewise. (trunc<mode><Vnarrowq>2): Rename to... (trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This. (aarch64_xtn<mode>): Move under the above. Just emit the truncate RTL. (aarch64_<su>qmovn<mode>): Likewise. (aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn. (aarch64_<su>qmovn<mode>_insn_le): Delete. (aarch64_<su>qmovn<mode>_insn_be): Likewise. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_4.c: Add tests for vmovn, vqmovn.
2023-05-10c++: Reject attributes without arguments used as pack expansion [PR109756]Jakub Jelinek2-2/+40
The following testcase shows we silently accept (and ignore) attributes without arguments used as pack expansions. This is because we call make_pack_expansion and that starts with if (!arg || arg == error_mark_node) return arg; Now, an attribute without arguments like [[noreturn...]] is IMHO always invalid, in this case for 2 reasons; one is that as it has no arguments, no pack can be present and second is that the standard says that attributes need to specially permit uses of parameter pack and doesn't explicitly permit it for any of the standard attributes (except for alignas? which has different syntax). If an attribute has some arguments but doesn't contain packs in those arguments, make_pack_expansion will already diagnose it. The patch also changes cp_parser_std_attribute, such that for attributes unknown to the compiler (or perhaps registered just for -Wno-attributes=) we differentiate between the attribute having no arguments (in that case we want to diagnose them when followed by ellipsis even if they are unknown, as they can't contain a pack in that case) and the case where they do have arguments but we've just skipped over those arguments because we don't know how to parse them (except that they are a balanced token sequence) - in that case we really don't know if they contain packs or not. 2023-05-10 Jakub Jelinek <jakub@redhat.com> PR c++/109756 * parser.cc (cp_parser_std_attribute): For unknown attributes with arguments set TREE_VALUE (attribute) to error_mark_node after skipping the balanced tokens. (cp_parser_std_attribute_list): If ... is used after attribute without arguments, diagnose it and return error_mark_node. If TREE_VALUE (attribute) is error_mark_node, don't call make_pack_expansion nor return early error_mark_node. * g++.dg/cpp0x/gen-attrs-78.C: New test.
2023-05-10RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying ↵Li Xu3-0/+56
REG_P(operand[1]) in -O0. This issue happens is because the operand1 of scalar move can be REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to not insert the vsetvl instruction correctly, and the compiler crashes. Consider this following case: int16_t foo1 (void *base, size_t vl) { int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl)); return maxVal; } Before this patch: bug.c:15:1: internal compiler error: Segmentation fault 15 | } | ^ 0x145d723 crash_signal ../.././riscv-gcc/gcc/toplev.cc:314 0x22929dd const_csr_operand(rtx_def*, machine_mode) ../.././riscv-gcc/gcc/config/riscv/predicates.md:44 0x2292a21 csr_operand(rtx_def*, machine_mode) ../.././riscv-gcc/gcc/config/riscv/predicates.md:46 0x23dfbb0 recog_356 ../.././riscv-gcc/gcc/config/riscv/iterators.md:72 0x23efecd recog(rtx_def*, rtx_insn*, int*) ../.././riscv-gcc/gcc/config/riscv/iterators.md:89 0xdddc15 recog_memoized(rtx_insn*) ../.././riscv-gcc/gcc/recog.h:273 After this patch: vsetivli zero,0,e16,m1,ta,ma vmv.x.s a5,v1 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s intruction replace null avl with (const_int 0). gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/scalar_move-10.c: New test. * gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
2023-05-10RISC-V: Fix incorrect implementation of ↵Juzhe-Zhong15-39/+32
TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT This incorrect codes blocks the scalable RVV auto-vectorization. Take a look at this target hook implementation of aarch64. They only have the similiar handling on TARGET_SIMD. They let movmisalign<mode> to handle scalable vector of SVE. For RVV, we should follow the same implementation of ARM SVE. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix incorrect codes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase. * gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto.
2023-05-10RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773]Juzhe-Zhong3-0/+71
This patch is fix dead loop in vsetvl intrinsic avl checking. vsetvli->get_def () has vsetvli->get_def () has vsetvli..... Then it will keep looping in the vsetvli avl checking which is a dead loop. PR target/109773 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_source_has_vsetvl_p): New function. (source_equal_p): Fix dead loop in vsetvl avl checking. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: New test. * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: New test.
2023-05-10New testcaseAndrew Pinski1-0/+28
While I was writting a match.pd patch, I can across GCC was being miscompiled but no testcase was failing. So this adds that testcase. Committed after testing on x86_64 with make check-gcc RUNTESTFLAGS="execute.exp=20230509-1.c" gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20230509-1.c: New test.
2023-05-10CRIS: Fix ccmode typo in cris_postdbr_cmpelimHans-Peter Nilsson1-1/+1
Typo spotted while doing CCmode improvements, as a missed optimization. It's almost visible from the patch context; there's not much done in terms of "mode-adjustment" when replacing (reg:CC CRIS_CC0_REGNUM) with a copy! This bug affects functions in the newlib printf-formatting functions (nothing else in libgcc or newlib libc), with the performance impact on coremark scores being less than 1e-6 (3/5078992 cycles, 6/48543 bytes). * config/cris/cris.cc (cris_postdbr_cmpelim): Correct mode of modeadjusted_dccr.
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