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2023-05-12RISC-V: Fix fail of vmv-imm-rv64.c in rv32Juzhe Zhong1-1/+1
After update local codebase to the trunk. I realize there is one more fail in RV32. After this patch, all fails of RVV are cleaned up. Thanks. FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c -O3 -ftree-vectorize (test for excess errors) Excess errors: cc1: error: ABI requires '-march=rv32' gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Add ABI Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
2023-05-12RISC-V: Add basic vec_init for VLS RVV auto-vectorizationJuzhe Zhong22-0/+1547
typedef int8_t vnx16qi __attribute__((vector_size (16))); typedef int8_t vnx16qi __attribute__ ((vector_size (16))); typedef int8_t vnx32qi __attribute__ ((vector_size (32))); typedef int8_t vnx64qi __attribute__ ((vector_size (64))); typedef int8_t vnx128qi __attribute__ ((vector_size (128))); __attribute__ ((noipa)) void f_vnx128qi (int8_t a, int8_t b, int8_t c, int8_t d, int8_t e, int8_t f, int8_t g, int8_t h, int8_t *out) { vnx128qi v = {a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h}; *(vnx128qi *) out = v; } This patch codegen: f_vnx128qi: andi a1,a1,0xff andi a0,a0,0xff slli a1,a1,8 andi a2,a2,0xff or a1,a1,a0 slli a2,a2,16 andi a3,a3,0xff or a2,a2,a1 slli a3,a3,24 andi a4,a4,0xff or a3,a3,a2 slli a4,a4,32 andi a5,a5,0xff or a4,a4,a3 slli a5,a5,40 andi a6,a6,0xff or a5,a5,a4 slli a6,a6,48 or a6,a6,a5 vsetvli a5,zero,e64,m8,ta,ma ld a5,0(sp) slli a7,a7,56 or a7,a7,a6 vmv.v.x v8,a7 vs8r.v v8,0(a5) ret We support more optimizations cases in the future. But they are not included in this patch. Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/autovec.md (vec_init<mode><vel>): New pattern. * config/riscv/riscv-protos.h (expand_vec_init): New function. * config/riscv/riscv-v.cc (class rvv_builder): New class. (rvv_builder::can_duplicate_repeating_sequence_p): New function. (rvv_builder::get_merged_repeating_sequence): Ditto. (expand_vector_init_insert_elems): Ditto. (expand_vec_init): Ditto. * config/riscv/vector-iterators.md: New attribute. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: * gcc.target/riscv/rvv/autovec/vls-vlmax/insert-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-4.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-5.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: New test.
2023-05-12RISC-V: Reorganize binary autovec testcasesPan Li60-0/+2
1. This patch is moving binary autovec testcases into binop directory to make it easier to maintain. 2. Current binary autovec only tested in LMUL = 1, enable testing in LMUL = 2/4/8. Tested on both rv32/rv64, with no fails in RVV. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/shift-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/shift-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-run.c: ...here. * gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: ...here. * gcc.target/riscv/rvv/autovec/shift-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-template.h: ...here. * gcc.target/riscv/rvv/autovec/vadd-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vadd-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: ...here. * gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vadd-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-template.h: ...here. * gcc.target/riscv/rvv/autovec/vand-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vand-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-run.c: ...here. * gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vand-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-template.h: ...here. * gcc.target/riscv/rvv/autovec/vdiv-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vdiv-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: ...here. * gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vdiv-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmax-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmax-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: ...here. * gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmax-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmin-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmin-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: ...here. * gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmin-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmul-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmul-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: ...here. * gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmul-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-template.h: ...here. * gcc.target/riscv/rvv/autovec/vor-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vor-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-run.c: ...here. * gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vor-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-template.h: ...here. * gcc.target/riscv/rvv/autovec/vrem-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vrem-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: ...here. * gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vrem-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-template.h: ...here. * gcc.target/riscv/rvv/autovec/vsub-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vsub-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: ...here. * gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vsub-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: ...here. * gcc.target/riscv/rvv/autovec/vxor-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vxor-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: ...here. * gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vxor-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-template.h: ...here. * gcc.target/riscv/rvv/rvv.exp: Add autovec LMUL = 2/4/8 for binary. Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
2023-05-12RISC-V: Fix RVV binary auto-vectorizaiton test failsPan Li22-23/+23
In rv32: FAIL: gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmin-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vand-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vrem-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmul-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vand-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vdiv-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vor-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-scalar-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmax-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vor-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) In rv64: FAIL: gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/shift-run.c: Fix fail. * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: Ditto.
2023-05-12rs6000: Change ilp32 target check for scalar-extract-sig and ↵Haochen Gui3-3/+3
scalar-insert-exp test cases gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Replace ilp32 check with dg-skip-if has_arch_ppc64. * gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Likewise.
2023-05-12rs6000: Change mode and insn condition for scalar insert exp instructionHaochen Gui8-14/+14
gcc/ * config/rs6000/rs6000-builtins.def (__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp to xsiexpdp_di. (__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from xsiexpdpf to xsiexpdpf_di. * config/rs6000/vsx.md (xsiexpdp): Rename to... (xsiexpdp_<mode>): ..., set the mode of second operand to GPR and replace TARGET_64BIT with TARGET_POWERPC64. (xsiexpdpf): Rename to... (xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and replace TARGET_64BIT with TARGET_POWERPC64. gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Replace lp64 check with has_arch_ppc64. * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise.
2023-05-12rs6000: Change mode and insn condition for scalar extract sig instructionHaochen Gui5-5/+5
gcc/ * config/rs6000/rs6000-builtins.def (__builtin_vsx_scalar_extract_sig): Set return type to const signed long long. * config/rs6000/vsx.md (xsxsigdp): Replace TARGET_64BIT with TARGET_POWERPC64. gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Replace lp64 check with has_arch_ppc64. * gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise.
2023-05-12rs6000: Change mode and insn condition for scalar extract exp instructionHaochen Gui7-34/+10
gcc/ * config/rs6000/rs6000-builtins.def (__builtin_vsx_scalar_extract_exp): Set return type to const signed int and set its bif-pattern to xsxexpdp_si, move it from power9-64 to power9 catalog. * config/rs6000/vsx.md (xsxexpdp): Rename to ... (xsxexpdp_<mode>): ..., set mode of operand 0 to GPR and remove TARGET_64BIT check. * doc/extend.texi (scalar_extract_exp): Remove 64-bit environment requirement when it has a 64-bit argument. gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Remove lp64 check. * gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-2.c: Delete as the case is invalid now. * gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Remove lp64 check.
2023-05-12Var-Tracking: Typedef pointer_mux<tree_node, rtx_def> as decl_or_valuePan Li2-52/+37
The decl_or_value is defined as void * before this PATCH. It will take care of both the tree_node and rtx_def. Unfortunately, given a void pointer cannot tell the input is tree_node or rtx_def. Then we have some implicit structure layout requirement similar as below. Or we will touch unreasonable bits when cast void * to tree_node or rtx_def. +--------+-----------+----------+ | offset | tree_node | rtx_def | +--------+-----------+----------+ | 0 | code: 16 | code: 16 | <- require the same location and bitssize +--------+-----------+----------+ | 16 | ... | mode: 8 | +--------+-----------+----------+ | ... | +--------+-----------+----------+ | 24 | ... | ... | +--------+-----------+----------+ This behavior blocks the PATCH that extend the rtx_def mode from 8 to 16 bits for running out of machine mode. This PATCH introduced the pointer_mux to tell the input is tree_node or rtx_def, and decouple the above implicit dependency. Signed-off-by: Pan Li <pan2.li@intel.com> Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com> Co-Authored-By: Richard Biener <rguenther@suse.de> Co-Authored-By: Jakub Jelinek <jakub@redhat.com> gcc/ChangeLog: * mux-utils.h: Add overload operator == and != for pointer_mux. * var-tracking.cc: Included mux-utils.h for pointer_tmux. (decl_or_value): Changed from void * to pointer_mux<tree_node, rtx_def>. (dv_is_decl_p): Reconciled to the new type, aka pointer_mux. (dv_as_decl): Ditto. (dv_as_opaque): Removed due to unnecessary. (struct variable_hasher): Take decl_or_value as compare_type. (variable_hasher::equal): Diito. (dv_from_decl): Reconciled to the new type, aka pointer_mux. (dv_from_value): Ditto. (attrs_list_member): Ditto. (vars_copy): Ditto. (var_reg_decl_set): Ditto. (var_reg_delete_and_set): Ditto. (find_loc_in_1pdv): Ditto. (canonicalize_values_star): Ditto. (variable_post_merge_new_vals): Ditto. (dump_onepart_variable_differences): Ditto. (variable_different_p): Ditto. (set_slot_part): Ditto. (clobber_slot_part): Ditto. (clobber_variable_part): Ditto.
2023-05-12Daily bump.GCC Administrator6-1/+1980
2023-05-12PR modula2/109810 ICE fix when an array is assigned by a larger stringGaius Mulley6-139/+183
This patch fixes an ICE when an array variable is assigned with a string which exceeds the array size. It improves the accuracy of the virtual token used to indicate the error message. gcc/m2/ChangeLog: PR modula2/109810 * gm2-compiler/M2ALU.mod (ConvertConstToType): Use PrepareCopyString in place of DoCopyString. * gm2-compiler/M2GenGCC.def (DoCopyString): Rename to ... (PrepareCopyString): ... this. * gm2-compiler/M2GenGCC.mod (CodeStatement): Call CodeReturnValue with a single parameter. Call CodeXIndr with a single parameter. (CodeReturnValue): Remove parameters and replace with a single quadno. Reimplement using PrepareCopyString. Issue error if the string exceeds designator space. (DoCopyString): Reimplement and rename to ... (PrepareCopyString): ... this. (CodeXIndr): Remove parameters and replace with a single quadno. Reimplement using PrepareCopyString. Issue error if the string exceeds designator space. (CodeBecomes): Remove parameters and replace with a single quadno. Reimplement using PrepareCopyString. Issue error if the string exceeds designator space. * gm2-compiler/M2Quads.def (BuildReturn): Rename parameter to tokreturn. * gm2-compiler/M2Quads.mod (BuildReturn): Rename parameter to tokreturn. Rename tokno to tokcombined. gcc/testsuite/ChangeLog: PR modula2/109810 * gm2/pim/fail/highice.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-05-11c++: 'mutable' subobject of constexpr variable [PR109745]Patrick Palka4-4/+96
r13-2701-g7107ea6fb933f1 made us correctly accept during constexpr evaluation 'mutable' member accesses of objects constructed during that evaluation, while continuing to reject such accesses for constexpr objects constructed outside of that evaluation, by considering the CONSTRUCTOR_MUTABLE_POISON flag during cxx_eval_component_reference. However, this flag is set only for the outermost CONSTRUCTOR of a constexpr variable initializer, so if we're accessing a 'mutable' member of a nested CONSTRUCTOR, the flag won't be set and we won't reject the access. This can lead to us accepting invalid code, as in the first testcase, or even wrong code generation due to our speculative constexpr evaluation, as in the second and third testcase. This patch fixes this by setting CONSTRUCTOR_MUTABLE_POISON recursively rather than only on the outermost CONSTRUCTOR. PR c++/109745 gcc/cp/ChangeLog: * typeck2.cc (poison_mutable_constructors): Define. (store_init_value): Use it instead of setting CONSTRUCTOR_MUTABLE_POISON directly. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/constexpr-mutable4.C: New test. * g++.dg/cpp0x/constexpr-mutable5.C: New test. * g++.dg/cpp1y/constexpr-mutable2.C: New test.
2023-05-11aarch64: convert vector shift + bitwise and + multiply to vector comparemtsamis2-0/+133
When using SWAR (SIMD in a register) techniques a comparison operation within such a register can be made by using a combination of shifts, bitwise and and multiplication. If code using this scheme is vectorized then there is potential to replace all these operations with a single vector comparison, by reinterpreting the vector types to match the width of the SWAR register. For example, for the test function packed_cmp_16_32, the original generated code is: ldr q0, [x0] add w1, w1, 1 ushr v0.4s, v0.4s, 15 and v0.16b, v0.16b, v2.16b shl v1.4s, v0.4s, 16 sub v0.4s, v1.4s, v0.4s str q0, [x0], 16 cmp w2, w1 bhi .L20 with this pattern the above can be optimized to: ldr q0, [x0] add w1, w1, 1 cmlt v0.8h, v0.8h, #0 str q0, [x0], 16 cmp w2, w1 bhi .L20 The effect is similar for x86-64. Bootstrapped and reg-tested for x86 and aarch64. gcc/ChangeLog: * match.pd: simplify vector shift + bit_and + multiply. gcc/testsuite/ChangeLog: * gcc.target/aarch64/swar_to_vec_cmp.c: New test. Signed-off-by: Manolis Tsamis <manolis.tsamis@vrull.eu> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-05-11arm: [MVE intrinsics] rework vmlaq vmlasq vqdmlahq vqdmlashq vqrdmlahq ↵Christophe Lyon5-894/+24
vqrdmlashq Implement vmlaq, vmlasq, vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmlaq, vmlasq, vqdmlahq) (vqdmlashq, vqrdmlahq, vqrdmlashq): New. * config/arm/arm-mve-builtins-base.def (vmlaq, vmlasq, vqdmlahq) (vqdmlashq, vqrdmlahq, vqrdmlashq): New. * config/arm/arm-mve-builtins-base.h (vmlaq, vmlasq, vqdmlahq) (vqdmlashq, vqrdmlahq, vqrdmlashq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmlaq, vmlasq, vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq. * config/arm/arm_mve.h (vqrdmlashq): Remove. (vqrdmlahq): Remove. (vqdmlashq): Remove. (vqdmlahq): Remove. (vmlasq): Remove. (vmlaq): Remove. (vmlaq_m): Remove. (vmlasq_m): Remove. (vqdmlashq_m): Remove. (vqdmlahq_m): Remove. (vqrdmlahq_m): Remove. (vqrdmlashq_m): Remove. (vmlasq_n_u8): Remove. (vmlaq_n_u8): Remove. (vqrdmlashq_n_s8): Remove. (vqrdmlahq_n_s8): Remove. (vqdmlahq_n_s8): Remove. (vqdmlashq_n_s8): Remove. (vmlasq_n_s8): Remove. (vmlaq_n_s8): Remove. (vmlasq_n_u16): Remove. (vmlaq_n_u16): Remove. (vqrdmlashq_n_s16): Remove. (vqrdmlahq_n_s16): Remove. (vqdmlashq_n_s16): Remove. (vqdmlahq_n_s16): Remove. (vmlasq_n_s16): Remove. (vmlaq_n_s16): Remove. (vmlasq_n_u32): Remove. (vmlaq_n_u32): Remove. (vqrdmlashq_n_s32): Remove. (vqrdmlahq_n_s32): Remove. (vqdmlashq_n_s32): Remove. (vqdmlahq_n_s32): Remove. (vmlasq_n_s32): Remove. (vmlaq_n_s32): Remove. (vmlaq_m_n_s8): Remove. (vmlaq_m_n_s32): Remove. (vmlaq_m_n_s16): Remove. (vmlaq_m_n_u8): Remove. (vmlaq_m_n_u32): Remove. (vmlaq_m_n_u16): Remove. (vmlasq_m_n_s8): Remove. (vmlasq_m_n_s32): Remove. (vmlasq_m_n_s16): Remove. (vmlasq_m_n_u8): Remove. (vmlasq_m_n_u32): Remove. (vmlasq_m_n_u16): Remove. (vqdmlashq_m_n_s8): Remove. (vqdmlashq_m_n_s32): Remove. (vqdmlashq_m_n_s16): Remove. (vqdmlahq_m_n_s8): Remove. (vqdmlahq_m_n_s32): Remove. (vqdmlahq_m_n_s16): Remove. (vqrdmlahq_m_n_s8): Remove. (vqrdmlahq_m_n_s32): Remove. (vqrdmlahq_m_n_s16): Remove. (vqrdmlashq_m_n_s8): Remove. (vqrdmlashq_m_n_s32): Remove. (vqrdmlashq_m_n_s16): Remove. (__arm_vmlasq_n_u8): Remove. (__arm_vmlaq_n_u8): Remove. (__arm_vqrdmlashq_n_s8): Remove. (__arm_vqdmlashq_n_s8): Remove. (__arm_vqrdmlahq_n_s8): Remove. (__arm_vqdmlahq_n_s8): Remove. (__arm_vmlasq_n_s8): Remove. (__arm_vmlaq_n_s8): Remove. (__arm_vmlasq_n_u16): Remove. (__arm_vmlaq_n_u16): Remove. (__arm_vqrdmlashq_n_s16): Remove. (__arm_vqdmlashq_n_s16): Remove. (__arm_vqrdmlahq_n_s16): Remove. (__arm_vqdmlahq_n_s16): Remove. (__arm_vmlasq_n_s16): Remove. (__arm_vmlaq_n_s16): Remove. (__arm_vmlasq_n_u32): Remove. (__arm_vmlaq_n_u32): Remove. (__arm_vqrdmlashq_n_s32): Remove. (__arm_vqdmlashq_n_s32): Remove. (__arm_vqrdmlahq_n_s32): Remove. (__arm_vqdmlahq_n_s32): Remove. (__arm_vmlasq_n_s32): Remove. (__arm_vmlaq_n_s32): Remove. (__arm_vmlaq_m_n_s8): Remove. (__arm_vmlaq_m_n_s32): Remove. (__arm_vmlaq_m_n_s16): Remove. (__arm_vmlaq_m_n_u8): Remove. (__arm_vmlaq_m_n_u32): Remove. (__arm_vmlaq_m_n_u16): Remove. (__arm_vmlasq_m_n_s8): Remove. (__arm_vmlasq_m_n_s32): Remove. (__arm_vmlasq_m_n_s16): Remove. (__arm_vmlasq_m_n_u8): Remove. (__arm_vmlasq_m_n_u32): Remove. (__arm_vmlasq_m_n_u16): Remove. (__arm_vqdmlahq_m_n_s8): Remove. (__arm_vqdmlahq_m_n_s32): Remove. (__arm_vqdmlahq_m_n_s16): Remove. (__arm_vqrdmlahq_m_n_s8): Remove. (__arm_vqrdmlahq_m_n_s32): Remove. (__arm_vqrdmlahq_m_n_s16): Remove. (__arm_vqrdmlashq_m_n_s8): Remove. (__arm_vqrdmlashq_m_n_s32): Remove. (__arm_vqrdmlashq_m_n_s16): Remove. (__arm_vqdmlashq_m_n_s8): Remove. (__arm_vqdmlashq_m_n_s16): Remove. (__arm_vqdmlashq_m_n_s32): Remove. (__arm_vmlasq): Remove. (__arm_vmlaq): Remove. (__arm_vqrdmlashq): Remove. (__arm_vqdmlashq): Remove. (__arm_vqrdmlahq): Remove. (__arm_vqdmlahq): Remove. (__arm_vmlaq_m): Remove. (__arm_vmlasq_m): Remove. (__arm_vqdmlahq_m): Remove. (__arm_vqrdmlahq_m): Remove. (__arm_vqrdmlashq_m): Remove. (__arm_vqdmlashq_m): Remove.
2023-05-11arm: [MVE intrinsics] factorize vmlaq_n vmlasq_n vqdmlahq_n vqdmlashq_n ↵Christophe Lyon2-84/+28
vqrdmlahq_n vqrdmlashq_n Factorize vmlaq_n, vmlasq_n, vqdmlahq_n, vqdmlashq_n, vqrdmlahq_n, vqrdmlashq_n builtins so that they use the same parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMLxQ_N): New. (mve_insn): Add vmla, vmlas, vqdmlah, vqdmlash, vqrdmlah, vqrdmlash. (supf): Add VQDMLAHQ_N_S, VQDMLASHQ_N_S, VQRDMLAHQ_N_S, VQRDMLASHQ_N_S. * config/arm/mve.md (mve_vmlaq_n_<supf><mode>) (mve_vmlasq_n_<supf><mode>, mve_vqdmlahq_n_<supf><mode>) (mve_vqdmlashq_n_<supf><mode>, mve_vqrdmlahq_n_<supf><mode>) (mve_vqrdmlashq_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] add ternary_n shapeChristophe Lyon2-0/+28
This patch adds the ternary_n shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (ternary_n): New. * config/arm/arm-mve-builtins-shapes.h (ternary_n): New.
2023-05-11arm: [MVE intrinsics] rework vqrdmladhq vqrdmladhxq vqrdmlsdhq vqrdmlsdhxq ↵Christophe Lyon5-928/+32
vqdmladhq vqdmladhxq vqdmlsdhq vqdmlsdhxq Implement vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vqdmladhq, vqdmladhxq) (vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq) (vqrdmlsdhxq): New. * config/arm/arm-mve-builtins-base.def (vqdmladhq, vqdmladhxq) (vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq) (vqrdmlsdhxq): New. * config/arm/arm-mve-builtins-base.h (vqdmladhq, vqdmladhxq) (vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq) (vqrdmlsdhxq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq. * config/arm/arm_mve.h (vqrdmlsdhxq): Remove. (vqrdmlsdhq): Remove. (vqrdmladhxq): Remove. (vqrdmladhq): Remove. (vqdmlsdhxq): Remove. (vqdmlsdhq): Remove. (vqdmladhxq): Remove. (vqdmladhq): Remove. (vqdmladhq_m): Remove. (vqdmladhxq_m): Remove. (vqdmlsdhq_m): Remove. (vqdmlsdhxq_m): Remove. (vqrdmladhq_m): Remove. (vqrdmladhxq_m): Remove. (vqrdmlsdhq_m): Remove. (vqrdmlsdhxq_m): Remove. (vqrdmlsdhxq_s8): Remove. (vqrdmlsdhq_s8): Remove. (vqrdmladhxq_s8): Remove. (vqrdmladhq_s8): Remove. (vqdmlsdhxq_s8): Remove. (vqdmlsdhq_s8): Remove. (vqdmladhxq_s8): Remove. (vqdmladhq_s8): Remove. (vqrdmlsdhxq_s16): Remove. (vqrdmlsdhq_s16): Remove. (vqrdmladhxq_s16): Remove. (vqrdmladhq_s16): Remove. (vqdmlsdhxq_s16): Remove. (vqdmlsdhq_s16): Remove. (vqdmladhxq_s16): Remove. (vqdmladhq_s16): Remove. (vqrdmlsdhxq_s32): Remove. (vqrdmlsdhq_s32): Remove. (vqrdmladhxq_s32): Remove. (vqrdmladhq_s32): Remove. (vqdmlsdhxq_s32): Remove. (vqdmlsdhq_s32): Remove. (vqdmladhxq_s32): Remove. (vqdmladhq_s32): Remove. (vqdmladhq_m_s8): Remove. (vqdmladhq_m_s32): Remove. (vqdmladhq_m_s16): Remove. (vqdmladhxq_m_s8): Remove. (vqdmladhxq_m_s32): Remove. (vqdmladhxq_m_s16): Remove. (vqdmlsdhq_m_s8): Remove. (vqdmlsdhq_m_s32): Remove. (vqdmlsdhq_m_s16): Remove. (vqdmlsdhxq_m_s8): Remove. (vqdmlsdhxq_m_s32): Remove. (vqdmlsdhxq_m_s16): Remove. (vqrdmladhq_m_s8): Remove. (vqrdmladhq_m_s32): Remove. (vqrdmladhq_m_s16): Remove. (vqrdmladhxq_m_s8): Remove. (vqrdmladhxq_m_s32): Remove. (vqrdmladhxq_m_s16): Remove. (vqrdmlsdhq_m_s8): Remove. (vqrdmlsdhq_m_s32): Remove. (vqrdmlsdhq_m_s16): Remove. (vqrdmlsdhxq_m_s8): Remove. (vqrdmlsdhxq_m_s32): Remove. (vqrdmlsdhxq_m_s16): Remove. (__arm_vqrdmlsdhxq_s8): Remove. (__arm_vqrdmlsdhq_s8): Remove. (__arm_vqrdmladhxq_s8): Remove. (__arm_vqrdmladhq_s8): Remove. (__arm_vqdmlsdhxq_s8): Remove. (__arm_vqdmlsdhq_s8): Remove. (__arm_vqdmladhxq_s8): Remove. (__arm_vqdmladhq_s8): Remove. (__arm_vqrdmlsdhxq_s16): Remove. (__arm_vqrdmlsdhq_s16): Remove. (__arm_vqrdmladhxq_s16): Remove. (__arm_vqrdmladhq_s16): Remove. (__arm_vqdmlsdhxq_s16): Remove. (__arm_vqdmlsdhq_s16): Remove. (__arm_vqdmladhxq_s16): Remove. (__arm_vqdmladhq_s16): Remove. (__arm_vqrdmlsdhxq_s32): Remove. (__arm_vqrdmlsdhq_s32): Remove. (__arm_vqrdmladhxq_s32): Remove. (__arm_vqrdmladhq_s32): Remove. (__arm_vqdmlsdhxq_s32): Remove. (__arm_vqdmlsdhq_s32): Remove. (__arm_vqdmladhxq_s32): Remove. (__arm_vqdmladhq_s32): Remove. (__arm_vqdmladhq_m_s8): Remove. (__arm_vqdmladhq_m_s32): Remove. (__arm_vqdmladhq_m_s16): Remove. (__arm_vqdmladhxq_m_s8): Remove. (__arm_vqdmladhxq_m_s32): Remove. (__arm_vqdmladhxq_m_s16): Remove. (__arm_vqdmlsdhq_m_s8): Remove. (__arm_vqdmlsdhq_m_s32): Remove. (__arm_vqdmlsdhq_m_s16): Remove. (__arm_vqdmlsdhxq_m_s8): Remove. (__arm_vqdmlsdhxq_m_s32): Remove. (__arm_vqdmlsdhxq_m_s16): Remove. (__arm_vqrdmladhq_m_s8): Remove. (__arm_vqrdmladhq_m_s32): Remove. (__arm_vqrdmladhq_m_s16): Remove. (__arm_vqrdmladhxq_m_s8): Remove. (__arm_vqrdmladhxq_m_s32): Remove. (__arm_vqrdmladhxq_m_s16): Remove. (__arm_vqrdmlsdhq_m_s8): Remove. (__arm_vqrdmlsdhq_m_s32): Remove. (__arm_vqrdmlsdhq_m_s16): Remove. (__arm_vqrdmlsdhxq_m_s8): Remove. (__arm_vqrdmlsdhxq_m_s32): Remove. (__arm_vqrdmlsdhxq_m_s16): Remove. (__arm_vqrdmlsdhxq): Remove. (__arm_vqrdmlsdhq): Remove. (__arm_vqrdmladhxq): Remove. (__arm_vqrdmladhq): Remove. (__arm_vqdmlsdhxq): Remove. (__arm_vqdmlsdhq): Remove. (__arm_vqdmladhxq): Remove. (__arm_vqdmladhq): Remove. (__arm_vqdmladhq_m): Remove. (__arm_vqdmladhxq_m): Remove. (__arm_vqdmlsdhq_m): Remove. (__arm_vqdmlsdhxq_m): Remove. (__arm_vqrdmladhq_m): Remove. (__arm_vqrdmladhxq_m): Remove. (__arm_vqrdmlsdhq_m): Remove. (__arm_vqrdmlsdhxq_m): Remove.
2023-05-11arm: [MVE intrinsics] factorize vqdmladhq vqdmladhxq vqdmlsdhq vqdmlsdhxq ↵Christophe Lyon2-116/+38
vqrdmladhq vqrdmladhxq vqrdmlsdhq vqrdmlsdhxq Factorize vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq builtins so that they use the same parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VQxDMLxDHxQ_S): New. (mve_insn): Add vqdmladh, vqdmladhx, vqdmlsdh, vqdmlsdhx, vqrdmladh, vqrdmladhx, vqrdmlsdh, vqrdmlsdhx. (supf): Add VQDMLADHQ_S, VQDMLADHXQ_S, VQDMLSDHQ_S, VQDMLSDHXQ_S, VQRDMLADHQ_S,VQRDMLADHXQ_S, VQRDMLSDHQ_S, VQRDMLSDHXQ_S. * config/arm/mve.md (mve_vqrdmladhq_s<mode>) (mve_vqrdmladhxq_s<mode>, mve_vqrdmlsdhq_s<mode>) (mve_vqrdmlsdhxq_s<mode>, mve_vqdmlsdhxq_s<mode>) (mve_vqdmlsdhq_s<mode>, mve_vqdmladhxq_s<mode>) (mve_vqdmladhq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] add ternary shapeChristophe Lyon2-0/+27
This patch adds the ternary shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (ternary): New. * config/arm/arm-mve-builtins-shapes.h (ternary): New.
2023-05-11arm: [MVE intrinsics] rework vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxqChristophe Lyon4-368/+12
Implement vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmlaldavaq, vmlaldavaxq) (vmlsldavaq, vmlsldavaxq): New. * config/arm/arm-mve-builtins-base.def (vmlaldavaq, vmlaldavaxq) (vmlsldavaq, vmlsldavaxq): New. * config/arm/arm-mve-builtins-base.h (vmlaldavaq, vmlaldavaxq) (vmlsldavaq, vmlsldavaxq): New. * config/arm/arm_mve.h (vmlaldavaq): Remove. (vmlaldavaxq): Remove. (vmlsldavaq): Remove. (vmlsldavaxq): Remove. (vmlaldavaq_p): Remove. (vmlaldavaxq_p): Remove. (vmlsldavaq_p): Remove. (vmlsldavaxq_p): Remove. (vmlaldavaq_s16): Remove. (vmlaldavaxq_s16): Remove. (vmlsldavaq_s16): Remove. (vmlsldavaxq_s16): Remove. (vmlaldavaq_u16): Remove. (vmlaldavaq_s32): Remove. (vmlaldavaxq_s32): Remove. (vmlsldavaq_s32): Remove. (vmlsldavaxq_s32): Remove. (vmlaldavaq_u32): Remove. (vmlaldavaq_p_s32): Remove. (vmlaldavaq_p_s16): Remove. (vmlaldavaq_p_u32): Remove. (vmlaldavaq_p_u16): Remove. (vmlaldavaxq_p_s32): Remove. (vmlaldavaxq_p_s16): Remove. (vmlsldavaq_p_s32): Remove. (vmlsldavaq_p_s16): Remove. (vmlsldavaxq_p_s32): Remove. (vmlsldavaxq_p_s16): Remove. (__arm_vmlaldavaq_s16): Remove. (__arm_vmlaldavaxq_s16): Remove. (__arm_vmlsldavaq_s16): Remove. (__arm_vmlsldavaxq_s16): Remove. (__arm_vmlaldavaq_u16): Remove. (__arm_vmlaldavaq_s32): Remove. (__arm_vmlaldavaxq_s32): Remove. (__arm_vmlsldavaq_s32): Remove. (__arm_vmlsldavaxq_s32): Remove. (__arm_vmlaldavaq_u32): Remove. (__arm_vmlaldavaq_p_s32): Remove. (__arm_vmlaldavaq_p_s16): Remove. (__arm_vmlaldavaq_p_u32): Remove. (__arm_vmlaldavaq_p_u16): Remove. (__arm_vmlaldavaxq_p_s32): Remove. (__arm_vmlaldavaxq_p_s16): Remove. (__arm_vmlsldavaq_p_s32): Remove. (__arm_vmlsldavaq_p_s16): Remove. (__arm_vmlsldavaxq_p_s32): Remove. (__arm_vmlsldavaxq_p_s16): Remove. (__arm_vmlaldavaq): Remove. (__arm_vmlaldavaxq): Remove. (__arm_vmlsldavaq): Remove. (__arm_vmlsldavaxq): Remove. (__arm_vmlaldavaq_p): Remove. (__arm_vmlaldavaxq_p): Remove. (__arm_vmlsldavaq_p): Remove. (__arm_vmlsldavaxq_p): Remove.
2023-05-11arm: [MVE intrinsics] factorize vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxqChristophe Lyon2-107/+42
Factorize vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq builtins so that they use the same parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMLxLDAVAxQ, MVE_VMLxLDAVAxQ_P): New. (mve_insn): Add vmlaldava, vmlaldavax, vmlsldava, vmlsldavax. (supf): Add VMLALDAVAXQ_P_S, VMLALDAVAXQ_S, VMLSLDAVAQ_P_S, VMLSLDAVAQ_S, VMLSLDAVAXQ_P_S, VMLSLDAVAXQ_S. * config/arm/mve.md (mve_vmlaldavaq_<supf><mode>) (mve_vmlsldavaq_s<mode>, mve_vmlsldavaxq_s<mode>) (mve_vmlaldavaxq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmlaldavaq_p_<supf><mode>, mve_vmlaldavaxq_p_<supf><mode>) (mve_vmlsldavaq_p_s<mode>, mve_vmlsldavaxq_p_s<mode>): Merge into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] add binary_acca_int64 shapeChristophe Lyon2-0/+38
This patch adds the binary_acca_int64 shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_acca_int64): New. * config/arm/arm-mve-builtins-shapes.h (binary_acca_int64): New.
2023-05-11arm: [MVE intrinsics] rework vrmlaldavhq vrmlaldavhxq vrmlsldavhq vrmlsldavhxqChristophe Lyon5-184/+18
Implement vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vrmlaldavhq, vrmlaldavhxq) (vrmlsldavhq, vrmlsldavhxq): New. * config/arm/arm-mve-builtins-base.def (vrmlaldavhq, vrmlaldavhxq) (vrmlsldavhq, vrmlsldavhxq): New. * config/arm/arm-mve-builtins-base.h (vrmlaldavhq, vrmlaldavhxq) (vrmlsldavhq, vrmlsldavhxq): New. * config/arm/arm-mve-builtins-functions.h (unspec_mve_function_exact_insn_pred_p): Handle vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq. * config/arm/arm_mve.h (vrmlaldavhq): Remove. (vrmlsldavhxq): Remove. (vrmlsldavhq): Remove. (vrmlaldavhxq): Remove. (vrmlaldavhq_p): Remove. (vrmlaldavhxq_p): Remove. (vrmlsldavhq_p): Remove. (vrmlsldavhxq_p): Remove. (vrmlaldavhq_u32): Remove. (vrmlsldavhxq_s32): Remove. (vrmlsldavhq_s32): Remove. (vrmlaldavhxq_s32): Remove. (vrmlaldavhq_s32): Remove. (vrmlaldavhq_p_s32): Remove. (vrmlaldavhxq_p_s32): Remove. (vrmlsldavhq_p_s32): Remove. (vrmlsldavhxq_p_s32): Remove. (vrmlaldavhq_p_u32): Remove. (__arm_vrmlaldavhq_u32): Remove. (__arm_vrmlsldavhxq_s32): Remove. (__arm_vrmlsldavhq_s32): Remove. (__arm_vrmlaldavhxq_s32): Remove. (__arm_vrmlaldavhq_s32): Remove. (__arm_vrmlaldavhq_p_s32): Remove. (__arm_vrmlaldavhxq_p_s32): Remove. (__arm_vrmlsldavhq_p_s32): Remove. (__arm_vrmlsldavhxq_p_s32): Remove. (__arm_vrmlaldavhq_p_u32): Remove. (__arm_vrmlaldavhq): Remove. (__arm_vrmlsldavhxq): Remove. (__arm_vrmlsldavhq): Remove. (__arm_vrmlaldavhxq): Remove. (__arm_vrmlaldavhq_p): Remove. (__arm_vrmlaldavhxq_p): Remove. (__arm_vrmlsldavhq_p): Remove. (__arm_vrmlsldavhxq_p): Remove.
2023-05-11arm: [MVE intrinsics] factorize vrmlaldavhq vrmlaldavhxq vrmlsldavhq ↵Christophe Lyon2-102/+43
vrmlsldavhxq Factorize vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq builtins so that they use the same parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VRMLxLDAVxQ, MVE_VRMLxLDAVHxQ_P): New. (mve_insn): Add vrmlaldavh, vrmlaldavhx, vrmlsldavh, vrmlsldavhx. (supf): Add VRMLALDAVHXQ_P_S, VRMLALDAVHXQ_S, VRMLSLDAVHQ_P_S, VRMLSLDAVHQ_S, VRMLSLDAVHXQ_P_S, VRMLSLDAVHXQ_S. * config/arm/mve.md (mve_vrmlaldavhxq_sv4si) (mve_vrmlsldavhq_sv4si, mve_vrmlsldavhxq_sv4si) (mve_vrmlaldavhq_<supf>v4si): Merge into ... (@mve_<mve_insn>q_<supf>v4si): ... this. (mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhq_p_sv4si) (mve_vrmlsldavhxq_p_sv4si, mve_vrmlaldavhq_p_<supf>v4si): Merge into ... (@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-11arm: [MVE intrinsics] rework vmlaldavq vmlaldavxq vmlsldavq vmlsldavxqChristophe Lyon4-366/+12
Implement vmlaldavq, vmlaldavxq, vmlsldavq, vmlsldavxq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmlaldavq, vmlaldavxq) (vmlsldavq, vmlsldavxq): New. * config/arm/arm-mve-builtins-base.def (vmlaldavq, vmlaldavxq) (vmlsldavq, vmlsldavxq): New. * config/arm/arm-mve-builtins-base.h (vmlaldavq, vmlaldavxq) (vmlsldavq, vmlsldavxq): New. * config/arm/arm_mve.h (vmlaldavq): Remove. (vmlsldavxq): Remove. (vmlsldavq): Remove. (vmlaldavxq): Remove. (vmlaldavq_p): Remove. (vmlaldavxq_p): Remove. (vmlsldavq_p): Remove. (vmlsldavxq_p): Remove. (vmlaldavq_u16): Remove. (vmlsldavxq_s16): Remove. (vmlsldavq_s16): Remove. (vmlaldavxq_s16): Remove. (vmlaldavq_s16): Remove. (vmlaldavq_u32): Remove. (vmlsldavxq_s32): Remove. (vmlsldavq_s32): Remove. (vmlaldavxq_s32): Remove. (vmlaldavq_s32): Remove. (vmlaldavq_p_s16): Remove. (vmlaldavxq_p_s16): Remove. (vmlsldavq_p_s16): Remove. (vmlsldavxq_p_s16): Remove. (vmlaldavq_p_u16): Remove. (vmlaldavq_p_s32): Remove. (vmlaldavxq_p_s32): Remove. (vmlsldavq_p_s32): Remove. (vmlsldavxq_p_s32): Remove. (vmlaldavq_p_u32): Remove. (__arm_vmlaldavq_u16): Remove. (__arm_vmlsldavxq_s16): Remove. (__arm_vmlsldavq_s16): Remove. (__arm_vmlaldavxq_s16): Remove. (__arm_vmlaldavq_s16): Remove. (__arm_vmlaldavq_u32): Remove. (__arm_vmlsldavxq_s32): Remove. (__arm_vmlsldavq_s32): Remove. (__arm_vmlaldavxq_s32): Remove. (__arm_vmlaldavq_s32): Remove. (__arm_vmlaldavq_p_s16): Remove. (__arm_vmlaldavxq_p_s16): Remove. (__arm_vmlsldavq_p_s16): Remove. (__arm_vmlsldavxq_p_s16): Remove. (__arm_vmlaldavq_p_u16): Remove. (__arm_vmlaldavq_p_s32): Remove. (__arm_vmlaldavxq_p_s32): Remove. (__arm_vmlsldavq_p_s32): Remove. (__arm_vmlsldavxq_p_s32): Remove. (__arm_vmlaldavq_p_u32): Remove. (__arm_vmlaldavq): Remove. (__arm_vmlsldavxq): Remove. (__arm_vmlsldavq): Remove. (__arm_vmlaldavxq): Remove. (__arm_vmlaldavq_p): Remove. (__arm_vmlaldavxq_p): Remove. (__arm_vmlsldavq_p): Remove. (__arm_vmlsldavxq_p): Remove.
2023-05-11arm: [MVE intrinsics] factorize vmlaldavq vmlaldavxq vmlsldavq vmlsldavxqChristophe Lyon2-100/+42
Factorize vmlaldavq, vmlaldavxq, vmlsldavq, vmlsldavxq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMLxLDAVxQ, MVE_VMLxLDAVxQ_P): New. (mve_insn): Add vmlaldav, vmlaldavx, vmlsldav, vmlsldavx. (supf): Add VMLALDAVXQ_S, VMLSLDAVQ_S, VMLSLDAVXQ_S, VMLALDAVXQ_P_S, VMLSLDAVQ_P_S, VMLSLDAVXQ_P_S. * config/arm/mve.md (mve_vmlaldavq_<supf><mode>) (mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>) (mve_vmlsldavxq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmlaldavq_p_<supf><mode>, mve_vmlaldavxq_p_s<mode>) (mve_vmlsldavq_p_s<mode>, mve_vmlsldavxq_p_s<mode>): Merge into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] add binary_acc_int64 shapeChristophe Lyon2-0/+24
This patch adds the binary_acc_int64 shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_acc_int64): New. * config/arm/arm-mve-builtins-shapes.h (binary_acc_int64): New.
2023-05-11arm: [MVE intrinsics] rework vabavqChristophe Lyon4-215/+3
Implement vabavq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vabavq): New. * config/arm/arm-mve-builtins-base.def (vabavq): New. * config/arm/arm-mve-builtins-base.h (vabavq): New. * config/arm/arm_mve.h (vabavq): Remove. (vabavq_p): Remove. (vabavq_s8): Remove. (vabavq_s16): Remove. (vabavq_s32): Remove. (vabavq_u8): Remove. (vabavq_u16): Remove. (vabavq_u32): Remove. (vabavq_p_s8): Remove. (vabavq_p_u8): Remove. (vabavq_p_s16): Remove. (vabavq_p_u16): Remove. (vabavq_p_s32): Remove. (vabavq_p_u32): Remove. (__arm_vabavq_s8): Remove. (__arm_vabavq_s16): Remove. (__arm_vabavq_s32): Remove. (__arm_vabavq_u8): Remove. (__arm_vabavq_u16): Remove. (__arm_vabavq_u32): Remove. (__arm_vabavq_p_s8): Remove. (__arm_vabavq_p_u8): Remove. (__arm_vabavq_p_s16): Remove. (__arm_vabavq_p_u16): Remove. (__arm_vabavq_p_s32): Remove. (__arm_vabavq_p_u32): Remove. (__arm_vabavq): Remove. (__arm_vabavq_p): Remove.
2023-05-11arm: [MVE intrinsics] factorize vabavqChristophe Lyon2-4/+6
Factorize vabavq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vabav. * config/arm/mve.md (mve_vabavq_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this,. (mve_vabavq_p_<supf><mode>): Rename into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this,.
2023-05-11arm: [MVE intrinsics] rework vmladavaq vmladavaxq vmlsdavaq vmlsdavaxqChristophe Lyon4-538/+12
Implement vmladavaq, vmladavaxq, vmlsdavaq, vmlsdavaxq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmladavaxq, vmladavaq) (vmlsdavaq, vmlsdavaxq): New. * config/arm/arm-mve-builtins-base.def (vmladavaxq, vmladavaq) (vmlsdavaq, vmlsdavaxq): New. * config/arm/arm-mve-builtins-base.h (vmladavaxq, vmladavaq) (vmlsdavaq, vmlsdavaxq): New. * config/arm/arm_mve.h (vmladavaq): Remove. (vmlsdavaxq): Remove. (vmlsdavaq): Remove. (vmladavaxq): Remove. (vmladavaq_p): Remove. (vmladavaxq_p): Remove. (vmlsdavaq_p): Remove. (vmlsdavaxq_p): Remove. (vmladavaq_u8): Remove. (vmlsdavaxq_s8): Remove. (vmlsdavaq_s8): Remove. (vmladavaxq_s8): Remove. (vmladavaq_s8): Remove. (vmladavaq_u16): Remove. (vmlsdavaxq_s16): Remove. (vmlsdavaq_s16): Remove. (vmladavaxq_s16): Remove. (vmladavaq_s16): Remove. (vmladavaq_u32): Remove. (vmlsdavaxq_s32): Remove. (vmlsdavaq_s32): Remove. (vmladavaxq_s32): Remove. (vmladavaq_s32): Remove. (vmladavaq_p_s8): Remove. (vmladavaq_p_s32): Remove. (vmladavaq_p_s16): Remove. (vmladavaq_p_u8): Remove. (vmladavaq_p_u32): Remove. (vmladavaq_p_u16): Remove. (vmladavaxq_p_s8): Remove. (vmladavaxq_p_s32): Remove. (vmladavaxq_p_s16): Remove. (vmlsdavaq_p_s8): Remove. (vmlsdavaq_p_s32): Remove. (vmlsdavaq_p_s16): Remove. (vmlsdavaxq_p_s8): Remove. (vmlsdavaxq_p_s32): Remove. (vmlsdavaxq_p_s16): Remove. (__arm_vmladavaq_u8): Remove. (__arm_vmlsdavaxq_s8): Remove. (__arm_vmlsdavaq_s8): Remove. (__arm_vmladavaxq_s8): Remove. (__arm_vmladavaq_s8): Remove. (__arm_vmladavaq_u16): Remove. (__arm_vmlsdavaxq_s16): Remove. (__arm_vmlsdavaq_s16): Remove. (__arm_vmladavaxq_s16): Remove. (__arm_vmladavaq_s16): Remove. (__arm_vmladavaq_u32): Remove. (__arm_vmlsdavaxq_s32): Remove. (__arm_vmlsdavaq_s32): Remove. (__arm_vmladavaxq_s32): Remove. (__arm_vmladavaq_s32): Remove. (__arm_vmladavaq_p_s8): Remove. (__arm_vmladavaq_p_s32): Remove. (__arm_vmladavaq_p_s16): Remove. (__arm_vmladavaq_p_u8): Remove. (__arm_vmladavaq_p_u32): Remove. (__arm_vmladavaq_p_u16): Remove. (__arm_vmladavaxq_p_s8): Remove. (__arm_vmladavaxq_p_s32): Remove. (__arm_vmladavaxq_p_s16): Remove. (__arm_vmlsdavaq_p_s8): Remove. (__arm_vmlsdavaq_p_s32): Remove. (__arm_vmlsdavaq_p_s16): Remove. (__arm_vmlsdavaxq_p_s8): Remove. (__arm_vmlsdavaxq_p_s32): Remove. (__arm_vmlsdavaxq_p_s16): Remove. (__arm_vmladavaq): Remove. (__arm_vmlsdavaxq): Remove. (__arm_vmlsdavaq): Remove. (__arm_vmladavaxq): Remove. (__arm_vmladavaq_p): Remove. (__arm_vmladavaxq_p): Remove. (__arm_vmlsdavaq_p): Remove. (__arm_vmlsdavaxq_p): Remove.
2023-05-11arm: [MVE intrinsics] add binary_acca_int32 shapeChristophe Lyon2-0/+38
This patch adds the binary_acca_int32 shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_acca_int32): New. * config/arm/arm-mve-builtins-shapes.h (binary_acca_int32): New.
2023-05-11arm: [MVE intrinsics] rework vmladavq vmladavxq vmlsdavq vmlsdavxqChristophe Lyon4-523/+12
Implement vmladavq, vmladavxq, vmlsdavq, vmlsdavxq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmladavq, vmladavxq) (vmlsdavq, vmlsdavxq): New. * config/arm/arm-mve-builtins-base.def (vmladavq, vmladavxq) (vmlsdavq, vmlsdavxq): New. * config/arm/arm-mve-builtins-base.h (vmladavq, vmladavxq) (vmlsdavq, vmlsdavxq): New. * config/arm/arm_mve.h (vmladavq): Remove. (vmlsdavxq): Remove. (vmlsdavq): Remove. (vmladavxq): Remove. (vmladavq_p): Remove. (vmlsdavxq_p): Remove. (vmlsdavq_p): Remove. (vmladavxq_p): Remove. (vmladavq_u8): Remove. (vmlsdavxq_s8): Remove. (vmlsdavq_s8): Remove. (vmladavxq_s8): Remove. (vmladavq_s8): Remove. (vmladavq_u16): Remove. (vmlsdavxq_s16): Remove. (vmlsdavq_s16): Remove. (vmladavxq_s16): Remove. (vmladavq_s16): Remove. (vmladavq_u32): Remove. (vmlsdavxq_s32): Remove. (vmlsdavq_s32): Remove. (vmladavxq_s32): Remove. (vmladavq_s32): Remove. (vmladavq_p_u8): Remove. (vmlsdavxq_p_s8): Remove. (vmlsdavq_p_s8): Remove. (vmladavxq_p_s8): Remove. (vmladavq_p_s8): Remove. (vmladavq_p_u16): Remove. (vmlsdavxq_p_s16): Remove. (vmlsdavq_p_s16): Remove. (vmladavxq_p_s16): Remove. (vmladavq_p_s16): Remove. (vmladavq_p_u32): Remove. (vmlsdavxq_p_s32): Remove. (vmlsdavq_p_s32): Remove. (vmladavxq_p_s32): Remove. (vmladavq_p_s32): Remove. (__arm_vmladavq_u8): Remove. (__arm_vmlsdavxq_s8): Remove. (__arm_vmlsdavq_s8): Remove. (__arm_vmladavxq_s8): Remove. (__arm_vmladavq_s8): Remove. (__arm_vmladavq_u16): Remove. (__arm_vmlsdavxq_s16): Remove. (__arm_vmlsdavq_s16): Remove. (__arm_vmladavxq_s16): Remove. (__arm_vmladavq_s16): Remove. (__arm_vmladavq_u32): Remove. (__arm_vmlsdavxq_s32): Remove. (__arm_vmlsdavq_s32): Remove. (__arm_vmladavxq_s32): Remove. (__arm_vmladavq_s32): Remove. (__arm_vmladavq_p_u8): Remove. (__arm_vmlsdavxq_p_s8): Remove. (__arm_vmlsdavq_p_s8): Remove. (__arm_vmladavxq_p_s8): Remove. (__arm_vmladavq_p_s8): Remove. (__arm_vmladavq_p_u16): Remove. (__arm_vmlsdavxq_p_s16): Remove. (__arm_vmlsdavq_p_s16): Remove. (__arm_vmladavxq_p_s16): Remove. (__arm_vmladavq_p_s16): Remove. (__arm_vmladavq_p_u32): Remove. (__arm_vmlsdavxq_p_s32): Remove. (__arm_vmlsdavq_p_s32): Remove. (__arm_vmladavxq_p_s32): Remove. (__arm_vmladavq_p_s32): Remove. (__arm_vmladavq): Remove. (__arm_vmlsdavxq): Remove. (__arm_vmlsdavq): Remove. (__arm_vmladavxq): Remove. (__arm_vmladavq_p): Remove. (__arm_vmlsdavxq_p): Remove. (__arm_vmlsdavq_p): Remove. (__arm_vmladavxq_p): Remove.
2023-05-11arm: [MVE intrinsics] factorize vmladav vmladavx vmlsdav vmlsdavx vmladava ↵Christophe Lyon2-208/+84
vmladavax vmlsdava vmlsdavax Factorize vmladav, vmladavx, vmlsdav, vmlsdavx, vmladava, vmladavax, vmlsdava, vmlsdavax builtins so that they use the same parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMLxDAVQ, MVE_VMLxDAVQ_P) (MVE_VMLxDAVAQ, MVE_VMLxDAVAQ_P): New. (mve_insn): Add vmladava, vmladavax, vmladav, vmladavx, vmlsdava, vmlsdavax, vmlsdav, vmlsdavx. (supf): Add VMLADAVAXQ_P_S, VMLADAVAXQ_S, VMLADAVXQ_P_S, VMLADAVXQ_S, VMLSDAVAQ_P_S, VMLSDAVAQ_S, VMLSDAVAXQ_P_S, VMLSDAVAXQ_S, VMLSDAVQ_P_S, VMLSDAVQ_S, VMLSDAVXQ_P_S, VMLSDAVXQ_S. * config/arm/mve.md (mve_vmladavq_<supf><mode>) (mve_vmladavxq_s<mode>, mve_vmlsdavq_s<mode>) (mve_vmlsdavxq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmlsdavaq_s<mode>, mve_vmladavaxq_s<mode>) (mve_vmlsdavaxq_s<mode>, mve_vmladavaq_<supf><mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmladavq_p_<supf><mode>, mve_vmladavxq_p_s<mode>) (mve_vmlsdavq_p_s<mode>, mve_vmlsdavxq_p_s<mode>): Merge into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this. (mve_vmladavaq_p_<supf><mode>, mve_vmladavaxq_p_s<mode>) (mve_vmlsdavaq_p_s<mode>, mve_vmlsdavaxq_p_s<mode>): Merge into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] add binary_acc_int32 shapeChristophe Lyon2-0/+28
This patch adds the binary_acc_int32 shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_acc_int32): New. * config/arm/arm-mve-builtins-shapes.h (binary_acc_int32): New.
2023-05-11arm: [MVE intrinsics] rework vaddlvaqChristophe Lyon4-74/+3
Implement vaddlvaq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vaddlvaq): New. * config/arm/arm-mve-builtins-base.def (vaddlvaq): New. * config/arm/arm-mve-builtins-base.h (vaddlvaq): New. * config/arm/arm_mve.h (vaddlvaq): Remove. (vaddlvaq_p): Remove. (vaddlvaq_u32): Remove. (vaddlvaq_s32): Remove. (vaddlvaq_p_s32): Remove. (vaddlvaq_p_u32): Remove. (__arm_vaddlvaq_u32): Remove. (__arm_vaddlvaq_s32): Remove. (__arm_vaddlvaq_p_s32): Remove. (__arm_vaddlvaq_p_u32): Remove. (__arm_vaddlvaq): Remove. (__arm_vaddlvaq_p): Remove.
2023-05-11arm: [MVE intrinsics] add unary_widen_acc shapeChristophe Lyon2-0/+35
This patch adds the unary_widen_acc shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_widen_acc): New. * config/arm/arm-mve-builtins-shapes.h (unary_widen_acc): New.
2023-05-11arm: [MVE intrinsics] factorize vaddlvaqChristophe Lyon2-4/+6
Factorize vaddlvaq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddlva. * config/arm/mve.md (mve_vaddlvaq_<supf>v4si): Rename into ... (@mve_<mve_insn>q_<supf>v4si): ... this. (mve_vaddlvaq_p_<supf>v4si): Rename into ... (@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-11i386: Handle V4HI and V2SImode in ix86_widen_mult_cost [PR109807]Uros Bizjak2-0/+6
Do not crash when asking ix86_widen_mult_cost for the cost of a widening mul operation to V4HI or V2SImode. gcc/ChangeLog: PR target/109807 * config/i386/i386.cc (ix86_widen_mult_cost): Handle V4HImode and V2SImode. gcc/testsuite/ChangeLog: PR target/109807 * gcc.target/i386/pr109807.c: New test.
2023-05-11Improve simple_dce for phis that only used in itselfAndrew Pinski1-2/+28
While I was looking at differences before and after r14-569-g21e2ef2dc25de3, I noticed that one phi node was not being removed. For an example, while compiling combine.cc, in expand_field_assignment, we would remove `# pos_51 = PHI <pos_221(31), pos_51(30)>` but we don't any more since pos_51 has more than zero users but in this case it is only itself. This patch improves simple_dce_from_worklist to detect that case and now we able to remove this phi statement again. OK? Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-dce.cc (simple_dce_from_worklist): For ssa names defined by a phi node with more than one uses, allow for the only uses are in that same defining statement.
2023-05-11syscall: add prlimitIan Lance Taylor1-1/+1
As of https://go.dev/cl/476695 golang.org/x/sys/unix can call syscall.prlimit, so we need such a function in libgo. For golang/go#46279 Fixes golang/go#59712 Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/486576
2023-05-11c++: Add testcase for already fixed PR [PR103807]Patrick Palka1-0/+11
We accept this testcase since r13-806-g221acd67ca50f8. PR c++/103807 gcc/testsuite/ChangeLog: * g++.dg/cpp2a/lambda-targ1.C: New test.
2023-05-11RISC-V: Allow vector constants in riscv_const_insns.Robin Dapp5-0/+130
This patch adds various vector constants to riscv_const_insns in order for them to be properly recognized as immediate operands. This then allows to emit vmv.v.i instructions via autovectorization. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Add permissible vector constants. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: New test. * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: New test. * gcc.target/riscv/rvv/autovec/vmv-imm-template.h: New test. * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: New test.
2023-05-11c++: converted lambda as template argument [PR83258, ...]Patrick Palka5-4/+32
r8-1253-g3d2e25a240c711 removed the template argument linkage requirement in convert_nontype_argument for C++17 (which r9-3836-g4be5c72cf3ea3e later factored out into invalid_tparm_referent_p), but we need to also remove the one in convert_nontype_argument_function for benefit of the first and third testcase which we currently reject even in C++17/20 mode. And in invalid_tparm_referent_p we're inadvertendly returning false for the address of a lambda's static op() since it's DECL_ARTIFICIAL, which currently causes us to reject the second (C++20) testcase. But this DECL_ARTIFICIAL check seems to be relevant only for VAR_DECL, and in fact this code path was originally reachable only for VAR_DECL until recently (r13-6970-gb5e38b1c166357). So this patch restricts the check to VAR_DECL. Co-authored-by: Jonathan Wakely <jwakely@redhat.com> PR c++/83258 PR c++/80488 PR c++/97700 gcc/cp/ChangeLog: * pt.cc (convert_nontype_argument_function): Remove linkage requirement for C++17 and later. (invalid_tparm_referent_p) <case ADDR_EXPR>: Restrict DECL_ARTIFICIAL rejection test to VAR_DECL. gcc/testsuite/ChangeLog: * g++.dg/ext/visibility/anon8.C: Don't expect a "no linkage" error for the template argument &B2:fn in C++17 mode. * g++.dg/cpp0x/lambda/lambda-conv15.C: New test. * g++.dg/cpp2a/nontype-class56.C: New test. * g++.dg/template/function2.C: New test.
2023-05-11[vxworks] [testsuite] [aarch64] use builtin in pred-not-gen-4.cAlexandre Oliva1-3/+1
On vxworks, isunordered is defined as a macro that ultimately calls a _Fpcomp function, that GCC doesn't recognize as a builtin, so it can't optimize accordingly. Use __builtin_isunordered instead to get the desired code for the test. for gcc/testsuite/ChangeLog * gcc.target/aarch64/sve/pred-not-gen-4.c: Drop math.h include, call builtin.
2023-05-11RISC-V: Update RVV integer compare simplification commentsPan Li1-1/+8
The VMSET simplification RVV integer comparision has merged already. This patch would like to update the comments for the cases that the define_split will act on. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * config/riscv/vector.md: Add comments for simplifying to vmset. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-11RISC-V: Add autovectorization tests for binary integer operations.Robin Dapp59-0/+1375
This patchs adds scan as well as execution tests for vectorized binary integer operations. The tests are not comprehensive as the vector type promotions (vec_unpack, extend etc.) are not implemented yet. Also, vmulh, vmulhu, and vmulhsu and others are still missing. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-template.h: New test. * gcc.target/riscv/rvv/autovec/shift-run.c: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-template.h: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: New test. * gcc.target/riscv/rvv/autovec/vadd-run-template.h: New test. * gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vadd-template.h: New test. * gcc.target/riscv/rvv/autovec/vand-run.c: New test. * gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vand-template.h: New test. * gcc.target/riscv/rvv/autovec/vdiv-run.c: New test. * gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vdiv-template.h: New test. * gcc.target/riscv/rvv/autovec/vmax-run.c: New test. * gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmax-template.h: New test. * gcc.target/riscv/rvv/autovec/vmin-run.c: New test. * gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmin-template.h: New test. * gcc.target/riscv/rvv/autovec/vmul-run.c: New test. * gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmul-template.h: New test. * gcc.target/riscv/rvv/autovec/vor-run.c: New test. * gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vor-template.h: New test. * gcc.target/riscv/rvv/autovec/vrem-run.c: New test. * gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vrem-template.h: New test. * gcc.target/riscv/rvv/autovec/vsub-run.c: New test. * gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vsub-template.h: New test. * gcc.target/riscv/rvv/autovec/vxor-run.c: New test. * gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vxor-template.h: New test. Co-authored-by: Michael Collison <collison@rivosinc.com>
2023-05-11RISC-V: Split off shift patterns for autovectorization.Robin Dapp2-1/+50
This patch splits off the shift patterns of the binop patterns. This is necessary as the scalar shifts require a Pmode operand as shift count. To this end, a new iterator any_int_binop_no_shift is introduced. At a later point when the binops are split up further in commutative and non-commutative patterns (which both do not include the shift patterns) we might not need this anymore. gcc/ChangeLog: * config/riscv/autovec.md (<optab><mode>3): Add scalar shift pattern. (v<optab><mode>3): Add vector shift pattern. * config/riscv/vector-iterators.md: New iterator.
2023-05-11RISC-V: Clarify vlmax and length handling.Robin Dapp5-61/+83
This patch tries to improve the wrappers that emit either vlmax or non-vlmax operations. Now, emit_len_op can be used to emit a regular operation. Depending on whether a length != NULL is passed either no VLMAX flags are set or we emit a vsetvli and set VLMAX flags. The patch also adds some comments that describes some of the rationale of the current handling of vlmax/nonvlmax operations. gcc/ChangeLog: * config/riscv/autovec.md: Use renamed functions. * config/riscv/riscv-protos.h (emit_vlmax_op): Rename. (emit_vlmax_reg_op): To this. (emit_nonvlmax_op): Rename. (emit_len_op): To this. (emit_nonvlmax_binop): Rename. (emit_len_binop): To this. * config/riscv/riscv-v.cc (emit_pred_op): Add default parameter. (emit_pred_binop): Remove vlmax_p. (emit_vlmax_op): Rename. (emit_vlmax_reg_op): To this. (emit_nonvlmax_op): Rename. (emit_len_op): To this. (emit_nonvlmax_binop): Rename. (emit_len_binop): To this. (sew64_scalar_helper): Use renamed functions. (expand_tuple_move): Use renamed functions. * config/riscv/riscv.cc (vector_zero_call_used_regs): Use renamed functions. * config/riscv/vector.md: Use renamed functions.
2023-05-11RISC-V: Add vectorized binops and insn_expander helpers.Robin Dapp3-64/+123
This patch adds basic binary integer operations support. It is based on Michael Collison's work and makes use of the existing helpers in riscv-c.cc. It introduces emit_nonvlmax_binop which, in turn, uses emit_pred_binop. Setting the destination as well as the mask and the length are factored out into separate functions. gcc/ChangeLog: * config/riscv/autovec.md (<optab><mode>3): Add integer binops. * config/riscv/riscv-protos.h (emit_nonvlmax_binop): Declare. * config/riscv/riscv-v.cc (emit_pred_op): New function. (set_expander_dest_and_mask): New function. (emit_pred_binop): New function. (emit_nonvlmax_binop): New function. Co-authored-by: Michael Collison <collison@rivosinc.com>
2023-05-11VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IVPan Li10-26/+29
This patch is going to be commited after bootstrap && regression on X86 PASSED. Thanks Richards. gcc/ChangeLog: * cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR. * gimple-loop-interchange.cc (tree_loop_interchange::map_inductions_to_loop): Ditto. * tree-ssa-loop-ivcanon.cc (create_canonical_iv): Ditto. * tree-ssa-loop-ivopts.cc (create_new_iv): Ditto. * tree-ssa-loop-manip.cc (create_iv): Ditto. (tree_transform_and_unroll_loop): Ditto. (canonicalize_loop_ivs): Ditto. * tree-ssa-loop-manip.h (create_iv): Ditto. * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Ditto. * tree-vect-loop-manip.cc (vect_set_loop_controls_directly): Ditto. (vect_set_loop_condition_normal): Ditto. * tree-vect-loop.cc (vect_create_epilog_for_reduction): Ditto. * tree-vect-stmts.cc (vectorizable_store): Ditto. (vectorizable_load): Ditto. Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
generated by cgit v1.1 at 2025-09-23 08:08:40 +0000