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2024-06-15RISC-V: Add testcases for vector unsigned SAT_SUB form 2Pan Li8-0/+379
The previous RISC-V backend .SAT_SUB enabling patch missed the form 2 testcases of vector modes. Aka: Form 2: #define DEF_VEC_SAT_U_SUB_FMT_2(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = (x - y) & (-(T)(x > y)); \ } \ } This patch would like to make it up to ensure form 2 of .SAT_SUB vector is covered. Passed the rv64gcv rvv.exp tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-15riscv: Allocate enough space to strcpy() stringChristoph Müllner1-3/+3
I triggered an ICE on Ubuntu 24.04 when compiling code that uses function attributes. Looking into the sources shows that we have a systematic issue in the attribute handling code: * we determine the length with strlen() (excluding the terminating null) * we allocate a buffer with this length * we copy the original string using strcpy() (incl. the terminating null) To quote the man page of strcpy(): "The programmer is responsible for allocating a destination buffer large enough, that is, strlen(src) + 1." The ICE looks like this: *** buffer overflow detected ***: terminated xtheadmempair_bench.c:14:1: internal compiler error: Aborted 14 | { | ^ 0xaf3b99 crash_signal /home/ubuntu/src/gcc/scaleff/gcc/toplev.cc:319 0xe5b957 strcpy /usr/include/riscv64-linux-gnu/bits/string_fortified.h:79 0xe5b957 riscv_process_target_attr /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:339 0xe5baaf riscv_process_target_attr /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:314 0xe5bc5f riscv_option_valid_attribute_p(tree_node*, tree_node*, tree_node*, int) /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:389 0x6a31e5 handle_target_attribute /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-attribs.cc:5915 0x5d3a07 decl_attributes(tree_node**, tree_node*, int, tree_node*) /home/ubuntu/src/gcc/scaleff/gcc/attribs.cc:900 0x5db403 c_decl_attributes /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:5501 0x5e8965 start_function(c_declspecs*, c_declarator*, tree_node*) /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:10562 0x6318ed c_parser_declaration_or_fndef /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2914 0x63a8ad c_parser_external_declaration /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2048 0x63b219 c_parser_translation_unit /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:1902 0x63b219 c_parse_file() /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:27277 0x68fec5 c_common_parse_file() /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-opts.cc:1311 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See <https://gcc.gnu.org/bugs/> for instructions. gcc/ChangeLog: * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Fix allocation size of buffer. (riscv_process_one_target_attr): Likewise. (riscv_process_target_attr): Likewise. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-06-15RISC-V: Refine the SAT_ARITH test help header files [NFC]Pan Li18-68/+80
Separate the vector part code to one standalone header file, which is independent with the scalar part. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Leverage the new header file for vector part. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Ditto. * gcc.target/riscv/sat_arith.h: Move vector part out. * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-15doc: Remove pointer to old versions of binutilsGerald Pfeifer1-4/+0
The oldest release in the advertised location dates back to August 2002, which is way older than we remotely want to cover here. gcc: PR target/69374 * doc/install.texi (Specific): Remove pointer to old versions of binutils.
2024-06-15Daily bump.GCC Administrator4-1/+457
2024-06-14Dont add varying values to gori_on_edge mass calculations.Andrew MacLeod1-9/+15
gori_on_edge will return an ssa_lazy_cache with all contextual ranges that can be generated by an edge. This patch adjusts it so that a VARYING range is never added. * gimple-range-gori.cc (gori_calc_operands): Do not continue nor add the range when VARYING is produced for an operand.
2024-06-14Add merge facility to ssa_lazy_cache.Andrew MacLeod2-0/+19
The ssa_lazy_cache has a routine to merge a range for an ssa-name with an existing range in the cache. This adds a method which will merge all elements of another ssa_lazy_cache. * gimple-range-cache.cc (ssa_lazy_cache::merge): New. * gimple-range-cache.h (ssa_lazy_cache::merge): New prototype.
2024-06-14Do not assume LHS of call is an ssa-name.Andrew MacLeod1-1/+1
gimple_range_fold makes an assumption that the LHS of a call is an ssa_name, which later in compilation may not be true. * gimple-range-fold.cc (fold_using_range::range_of_call): Ensure LHS is an SSA_NAME before invoking gimple_range_global.
2024-06-14testsuite: Add -Wno-psabi to vshuf-mem.C testJakub Jelinek1-1/+1
The newly added test FAILs on i686-linux. On x86_64-linux make check-g++ RUNTESTFLAGS='--target_board=unix\{-m64,-m32/-msse2,-m32/-mno-sse/-mno-mmx\} dg-torture.exp=vshuf-mem.C' shows that as well. The problem is that without SSE2/MMX the vector is passed differently than normally and so GCC warns about that. -Wno-psabi is the usual way to shut it up. Also wonder about the // { dg-additional-options "-march=z14" { target s390*-*-* } } line, doesn't that mean the test will FAIL on all pre-z14 HW? Shouldn't it use some z14_runtime or similar effective target, or check in main (in that case copied over to g++.target/s390) whether z14 instructions can be actually used at runtime? 2024-06-14 Jakub Jelinek <jakub@redhat.com> * g++.dg/torture/vshuf-mem.C: Add -Wno-psabi to dg-options.
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 10Pan Li9-0/+182
After the middle-end support the form 10 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 10 of unsigned .SAT_SUB. Form 10: #define SAT_SUB_U_10(T) \ T sat_sub_u_10_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-37.c: New test. * gcc.target/riscv/sat_u_sub-38.c: New test. * gcc.target/riscv/sat_u_sub-39.c: New test. * gcc.target/riscv/sat_u_sub-40.c: New test. * gcc.target/riscv/sat_u_sub-run-37.c: New test. * gcc.target/riscv/sat_u_sub-run-38.c: New test. * gcc.target/riscv/sat_u_sub-run-39.c: New test. * gcc.target/riscv/sat_u_sub-run-40.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 9Pan Li9-0/+182
After the middle-end support the form 9 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 9 of unsigned .SAT_SUB. Form 9: #define SAT_SUB_U_9(T) \ T sat_sub_u_9_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return overflow ? 0 : ret; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-33.c: New test. * gcc.target/riscv/sat_u_sub-34.c: New test. * gcc.target/riscv/sat_u_sub-35.c: New test. * gcc.target/riscv/sat_u_sub-36.c: New test. * gcc.target/riscv/sat_u_sub-run-33.c: New test. * gcc.target/riscv/sat_u_sub-run-34.c: New test. * gcc.target/riscv/sat_u_sub-run-35.c: New test. * gcc.target/riscv/sat_u_sub-run-36.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 8Pan Li9-0/+182
After the middle-end support the form 8 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 8 of unsigned .SAT_SUB. Form 8: #define SAT_SUB_U_8(T) \ T sat_sub_u_8_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)-(!overflow); \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-29.c: New test. * gcc.target/riscv/sat_u_sub-30.c: New test. * gcc.target/riscv/sat_u_sub-31.c: New test. * gcc.target/riscv/sat_u_sub-32.c: New test. * gcc.target/riscv/sat_u_sub-run-29.c: New test. * gcc.target/riscv/sat_u_sub-run-30.c: New test. * gcc.target/riscv/sat_u_sub-run-31.c: New test. * gcc.target/riscv/sat_u_sub-run-32.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 7Pan Li9-0/+182
After the middle-end support the form 7 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 7 of unsigned .SAT_SUB. Form 7: #define SAT_SUB_U_7(T) \ T sat_sub_u_7_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)(overflow - 1); \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-25.c: New test. * gcc.target/riscv/sat_u_sub-26.c: New test. * gcc.target/riscv/sat_u_sub-27.c: New test. * gcc.target/riscv/sat_u_sub-28.c: New test. * gcc.target/riscv/sat_u_sub-run-25.c: New test. * gcc.target/riscv/sat_u_sub-run-26.c: New test. * gcc.target/riscv/sat_u_sub-run-27.c: New test. * gcc.target/riscv/sat_u_sub-run-28.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 6Pan Li9-0/+180
After the middle-end support the form 6 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 6 of unsigned .SAT_SUB. Form 6: #define SAT_SUB_U_6(T) \ T sat_sub_u_6_##T (T x, T y) \ { \ return x <= y ? 0 : x - y; \ } gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-21.c: New test. * gcc.target/riscv/sat_u_sub-22.c: New test. * gcc.target/riscv/sat_u_sub-23.c: New test. * gcc.target/riscv/sat_u_sub-24.c: New test. * gcc.target/riscv/sat_u_sub-run-21.c: New test. * gcc.target/riscv/sat_u_sub-run-22.c: New test. * gcc.target/riscv/sat_u_sub-run-23.c: New test. * gcc.target/riscv/sat_u_sub-run-24.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 5Pan Li9-0/+180
After the middle-end support the form 5 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 5 of unsigned .SAT_SUB. Form 5: #define SAT_SUB_U_5(T) \ T sat_sub_u_5_##T (T x, T y) \ { \ return x < y ? 0 : x - y; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-17.c: New test. * gcc.target/riscv/sat_u_sub-18.c: New test. * gcc.target/riscv/sat_u_sub-19.c: New test. * gcc.target/riscv/sat_u_sub-20.c: New test. * gcc.target/riscv/sat_u_sub-run-17.c: New test. * gcc.target/riscv/sat_u_sub-run-18.c: New test. * gcc.target/riscv/sat_u_sub-run-19.c: New test. * gcc.target/riscv/sat_u_sub-run-20.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 4Pan Li9-0/+180
After the middle-end support the form 4 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 4 of unsigned .SAT_SUB. Form 4: #define SAT_SUB_U_4(T) \ T sat_sub_u_4_##T (T x, T y) \ { \ return x >= y ? x - y : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-13.c: New test. * gcc.target/riscv/sat_u_sub-14.c: New test. * gcc.target/riscv/sat_u_sub-15.c: New test. * gcc.target/riscv/sat_u_sub-16.c: New test. * gcc.target/riscv/sat_u_sub-run-13.c: New test. * gcc.target/riscv/sat_u_sub-run-14.c: New test. * gcc.target/riscv/sat_u_sub-run-15.c: New test. * gcc.target/riscv/sat_u_sub-run-16.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 3Pan Li9-0/+180
After the middle-end support the form 3 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 3 of unsigned .SAT_SUB. Form 3: #define SAT_SUB_U_3(T) \ T sat_sub_u_3_##T (T x, T y) \ { \ return x > y ? x - y : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-10.c: New test. * gcc.target/riscv/sat_u_sub-11.c: New test. * gcc.target/riscv/sat_u_sub-12.c: New test. * gcc.target/riscv/sat_u_sub-9.c: New test. * gcc.target/riscv/sat_u_sub-run-10.c: New test. * gcc.target/riscv/sat_u_sub-run-11.c: New test. * gcc.target/riscv/sat_u_sub-run-12.c: New test. * gcc.target/riscv/sat_u_sub-run-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14Match: Support more forms for the scalar unsigned .SAT_SUBPan Li2-2/+56
After we support the scalar unsigned form 1 and 2, we would like to introduce more forms include the branch and branchless. There are forms 3-10 list as below: Form 3: #define SAT_SUB_U_3(T) \ T sat_sub_u_3_##T (T x, T y) \ { \ return x > y ? x - y : 0; \ } Form 4: #define SAT_SUB_U_4(T) \ T sat_sub_u_4_##T (T x, T y) \ { \ return x >= y ? x - y : 0; \ } Form 5: #define SAT_SUB_U_5(T) \ T sat_sub_u_5_##T (T x, T y) \ { \ return x < y ? 0 : x - y; \ } Form 6: #define SAT_SUB_U_6(T) \ T sat_sub_u_6_##T (T x, T y) \ { \ return x <= y ? 0 : x - y; \ } Form 7: #define SAT_SUB_U_7(T) \ T sat_sub_u_7_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)(overflow - 1); \ } Form 8: #define SAT_SUB_U_8(T) \ T sat_sub_u_8_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)-(!overflow); \ } Form 9: #define SAT_SUB_U_9(T) \ T sat_sub_u_9_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return overflow ? 0 : ret; \ } Form 10: #define SAT_SUB_U_10(T) \ T sat_sub_u_10_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Take form 10 as example: SAT_SUB_U_10(uint64_t); Before this patch: uint8_t sat_sub_u_10_uint8_t (uint8_t x, uint8_t y) { unsigned char _1; unsigned char _2; uint8_t _3; __complex__ unsigned char _6; ;; basic block 2, loop depth 0 ;; pred: ENTRY _6 = .SUB_OVERFLOW (x_4(D), y_5(D)); _2 = IMAGPART_EXPR <_6>; if (_2 == 0) goto <bb 3>; [50.00%] else goto <bb 4>; [50.00%] ;; succ: 3 ;; 4 ;; basic block 3, loop depth 0 ;; pred: 2 _1 = REALPART_EXPR <_6>; ;; succ: 4 ;; basic block 4, loop depth 0 ;; pred: 2 ;; 3 # _3 = PHI <0(2), _1(3)> return _3; ;; succ: EXIT } After this patch: uint8_t sat_sub_u_10_uint8_t (uint8_t x, uint8_t y) { uint8_t _3; ;; basic block 2, loop depth 0 ;; pred: ENTRY _3 = .SAT_SUB (x_4(D), y_5(D)); [tail call] return _3; ;; succ: EXIT } The below test suites are passed for this patch: 1. The rv64gcv fully regression test with newlib. 2. The rv64gcv build with glibc. 3. The x86 bootstrap test. 4. The x86 fully regression test. gcc/ChangeLog: * match.pd: Add more match for unsigned sat_sub. * tree-ssa-math-opts.cc (match_unsigned_saturation_sub): Add new func impl to match phi node for .SAT_SUB. (math_opts_dom_walker::after_dom_children): Try match .SAT_SUB for the phi node, MULT_EXPR, BIT_XOR_EXPR and BIT_AND_EXPR. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14configure: adjustments for building with in-tree binutilsJan Beulich2-6/+6
For one setting ld_ver in a conditional (no in-tree ld) when it's used, for x86 at least, in unconditional ways can't be quite right. And then prefixing relative paths to binaries with ${objdir}/, when ${objdir} nowadays resolves to just .libs, can at best be a leftover that wasn't properly cleaned up at some earlier point. gcc/ * configure.ac: Drop ${objdir}/ from NM and AR. Move setting of ld_ver out of conditional. * configure: Re-generate.
2024-06-14Adjust gcc.target/i386/vect-strided-3.cRichard Biener1-1/+1
The following disables SSE4 instead of just AVX to avoid pextrq being used, confusing the assembler scanning. This avoids the reported failure with -march=cascadelake but adds a FAIL for -march=cascadelake -m32 (I've opened PR115487 for that). * gcc.target/i386/vect-strided-3.c: Disable SSE4 instead of AVX.
2024-06-14Support single def-use cycle optimization for SLP reduction vectorizationRichard Biener2-18/+45
We can at least mimic single def-use cycle optimization when doing single-lane SLP reductions and that's required to avoid regressing compared to non-SLP. * tree-vect-loop.cc (vectorizable_reduction): Allow single-def-use cycles with SLP. (vect_transform_reduction): Handle SLP single def-use cycles. (vect_transform_cycle_phi): Likewise. * gcc.dg/vect/slp-reduc-12.c: New testcase.
2024-06-14doc: Consolidate duplicate MOVBE listings for Intel CPUsGerald Pfeifer1-14/+14
gcc: * doc/invoke.texi (x86 Options): Consolidate duplicate MOVBE listings for haswell, broadwell, skylake, skylake-avx512, cannonlake, icelake-client, icelake-server, cascadelake, cooperlake, tigerlake, sapphirerapids, rocketlake, graniterapids, and graniterapids-d options to -march.
2024-06-14RISC-V: Bugfix vec_extract v mode iterator restriction mismatchPan Li3-1/+65
We have vec_extract pattern which takes ZVFHMIN as the mode iterator of the V mode. Aka VF_ZVFHMIN iterator. But it will expand to pred_extract_first pattern which takes the ZVFH as the mode iterator of the V mode. AKa VF. The mismatch will result in one ICE similar as below: insn 30 29 31 2 (set (reg:HF 156 [ _2 ]) (unspec:HF [ (vec_select:HF (reg:RVVMF2HF 134 [ _1 ]) (parallel [ (const_int 0 [0]) ])) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1 (nil)) during RTL pass: vregs compress_run-2.c:25:1: internal compiler error: in extract_insn, at recog.cc:2812 0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) ../../../gcc/gcc/rtl-error.cc:108 0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*) ../../../gcc/gcc/rtl-error.cc:116 0xb3a545 extract_insn(rtx_insn*) ../../../gcc/gcc/recog.cc:2812 0x1010e9e instantiate_virtual_regs_in_insn ../../../gcc/gcc/function.cc:1612 0x1010e9e instantiate_virtual_regs ../../../gcc/gcc/function.cc:1995 0x1010e9e execute ../../../gcc/gcc/function.cc:2042 The below test suites are passed for this patch. 1. The rv64gcv fully regression test. 2. The rv64gcv build with glibc. There may be other similar issue(s) for the mismatch, we will take care of them by test cases one by one. PR target/115456 gcc/ChangeLog: * config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V which contains the VF_ZVFHMIN for alignment. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr115456-2.c: New test. * gcc.target/riscv/rvv/base/pr115456-3.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14doc: Remove reference to InterixGerald Pfeifer1-2/+1
This apparently was missed when support for Interix was removed in 2016. gcc: PR target/69374 * doc/install.texi (Specific): Remove stale reference to Interix.
2024-06-14ada: Do not include target-specific makefile fragmentsEric Botcazou1-6/+0
They are unused in this context. gcc/ada/ * gcc-interface/Makefile.in (tmake_file): Remove all references.
2024-06-14ada: Fix return mechanism reported by -gnatRmEric Botcazou1-7/+27
The return mechanism of functions is reported when the -gnatRm switch is specified, but it is incorrect when the result type is not a by-reference type in the language sense but is nevertheless returned by reference. gcc/ada/ * gcc-interface/decl.cc: Include function.h. (gnat_to_gnu_param): Minor comment tweaks. (gnat_to_gnu_subprog_type): Take into account the default for the computation of the return mechanism. Give a warning if a by-copy specified mechanism cannot be honored.
2024-06-14ada: Skip subprogram body entities inside scopesYannick Moy1-0/+8
Entities of kind E_Subprogram_Body, used on bodies of subprograms for which there is a separate declaration, have been added in the entities linked from a scope in order to get the representation information on their enclosed object and type declarations. Skip these entities in gigi. gcc/ada/ * gcc-interface/trans.cc (elaborate_all_entities_for_package) (process_freeze_entity): Skip entities of kind E_Subprogram_Body.
2024-06-14ada: Do not create null GCC thunksEric Botcazou1-10/+19
This prevents Gigi from creating null GCC thunks, i.e. thunks that have all their internal parameters set to zero, replacing them with aliases. They can arise in degenerate cases and null thunks would trip on an assertion in former_thunk_p when they are later optimized. gcc/ada/ PR ada/109817 * gcc-interface/trans.cc (maybe_make_gnu_thunk): Create an alias instead of a null thunk.
2024-06-14ada: Typo and indentation fixMarc Poulhiès4-7/+7
Fixes typo in comments and 2 instances of bad indentation. gcc/ada/ * gcc-interface/decl.cc (gnat_to_gnu_entity): Typo fix. (gnat_to_gnu_component_type): Indent fix. * gcc-interface/gigi.h (build_call_alloc_dealloc): Typo fix. * gcc-interface/utils.cc (make_dummy_type): Typo fix. * gcc-interface/utils2.cc (gnat_protect_expr): Indent fix.
2024-06-14ada: Fix parts of classification of aspectsEric Botcazou2-62/+101
Many aspects are (correctly) marked as GNAT-specific but nevertheless not listed in the Implementation_Defined_Aspect array, so this aligns the two sides and also removes Default_Initial_Condition and Object_Size from the list, since they are defined in Ada 2022. This also moves No_Controlled_Parts and No_Task_Parts to the subclass of boolean aspects, and completes the list of nonoverridable aspects defined in Ada 2022. gcc/ada/ * aspects.ads (Aspect_Id): Alphabetize, remove the GNAT tag from Default_Initial_Condition and Object_Size, move No_Controlled_Parts and No_Task_Parts to boolean subclass. (Nonoverridable_Aspect_Id): Add missing Ada 2022 aspects. (Implementation_Defined_Aspect): Add all missing aspects, remove Max_Entry_Queue_Length and Object_Size (Aspect_Argument): Remove specific entries for No_Controlled_Parts and No_Task_Parts, list boolean aspects last. (Is_Representation_Aspect ): Move boolean aspects last. (Aspect_Names): Alphabetize. * sem_ch13.adb (Analyze_Aspect_Disable_Controlled): Adjust. (Analyze_Aspect_Specifications): Move around processing for No_Controlled_Parts and No_Task_Parts. (Check_Aspect_At_Freeze_Point): Remove specific entries for No_Controlled_Parts and No_Task_Parts
2024-06-14ada: Bad tree built for Obj.Discrim_Dep_Component'Loop_Entry in assertionSteve Baird1-7/+18
The Etype for an N_Selected_Component node usually should not match the Etype of the referenced component if the component is subject to a discriminant-dependent constraint. Instead Build_Actual_Subtype_Of_Component should be called. Fix a case where this rule was not being followed (because B_A_S_O_C is not called during preanalysis of a component selection), resulting in a tree that confused CodePeer because the subtype was wrong. gcc/ada/ * exp_attr.adb (Expand_Loop_Entry_Attribute): Ensure that Etype of the saved expression is set correctly.
2024-06-14ada: Simplify handling of VxWorks-specific error codes for ENOENTJerome Guitton1-7/+20
These error codes were defined on older versions of VxWorks (5, 6, 7 SR0540) and now they are either not defined or they fallback to ENOENT. To handle these cases without using complex tests against vxworks versions, leverage on __has_include and provide a fallback to ENOENT if these error codes are not defined. gcc/ada/ * sysdep.c (S_dosFsLib_FILE_NOT_FOUND, S_nfsLib_NFSERR_NOENT): New macros, falback to ENOENT when not already defined. (__gnat_is_file_not_found_error): Use these new macros to remove tests against VxWorks flavors.
2024-06-14ada: Minor tweak in SnamesEric Botcazou1-4/+1
gcc/ada/ * snames.ads-tmpl (Name_Present): Move to Repinfo section.
2024-06-14ada: Add prototype for mutably tagged typesJustin Squirek30-130/+1235
This patch implements mutably tagged types via the new Size'Class aspect. gcc/ada/ * doc/gnat_rm/gnat_language_extensions.rst: Add documentation for mutably tagged type feature. * aspects.ads: Add registration for 'Size'Class. * einfo.ads: Add documentation for new components Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type. * exp_aggr.adb (Gen_Assign): Assume associated mutably tagged type when class-wide equivalent type is encountered. (Contains_Mutably_Tagged_Type): New subprogram. (Convert_To_Positional): Assume associated mutably tagged type when class-wide equivalent type is encountered. (Is_Static_Element): Assume associated mutably tagged type when class-wide equivalent type is encountered. (Expand_Array_Aggregate): Assume associated mutably tagged type when class-wide equivalent type is encountered. (Expand_Record_Aggregate): Force mutably tagged records to be expanded into assignments. * exp_ch3.adb (Build_Array_Init_Proc): Assume associated mutably tagged type when class-wide equivalent type is encountered. (Simple_Initialization_OK): Disallow simple initialization for class-wide equivalent types. (Build_Init_Statements): Assume associated mutably tagged type when class-wide equivalent type is encountered. (Expand_Freeze_Array_Type): Ignore building of record init procs for mutably tagged types. (Expand_N_Full_Type_Declaration): Replace mutably tagged type declarations with their associated class-wide equivalent types. (Default_Initialize_Object): Add special handling for mutably tagged types. * exp_ch4.adb (Expand_N_Allocator): Add initialization for mutably tagged types. (Expand_Record_Equality): Generate mutably tagged unchecked conversions. * exp_ch5.adb (Expand_N_Assignment_Statement): Generate a special assignment case for class-wide equivalent types which does tag assignments and ignores certain checks. * exp_ch6.adb (Expand_Call_Helper): Propagate constrained extra formal actuals for mutably tagged types. * exp_ch7.adb (Make_Init_Call): Handle mutably tagged type initialization. * exp_util.adb (Make_CW_Equivalent_Type): Modify to handle mutably tagged objects which contain no initialization expression. (Make_Subtype_From_Expr): Modify call to Make_CW_Equivalent_Type. * exp_util.ads (Make_CW_Equivalent_Type): Move declaration from body to spec. * freeze.adb (Size_Known): No longer return false automatically when a class-wide type is encountered. (Freeze_Entity): Ignore error messages about size not being known for mutably tagged types. * gen_il-fields.ads: Register new fields Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type. * gen_il-gen-gen_entities.adb: Register new fields Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type for type entities. * mutably_tagged.adb, mutably_tagged.ads (Corresponding_Mutably_Tagged_Type): New subprogram. (Depends_On_Mutably_Tagged_Ext_Comp): New subprogram. (Get_Corresponding_Mutably_Tagged_Type_If_Present): New subprogram. (Get_Corresponding_Tagged_Type_If_Present): New subprogram. (Is_Mutably_Tagged_Conversion): New subprogram. (Is_Mutably_Tagged_CW_Equivalent_Type): New subprogram. (Make_Mutably_Tagged_Conversion): New subprogram. (Make_CW_Size_Compile_Check): New subprogram. (Make_Mutably_Tagged_CW_Check): New subprogram. * sem_aggr.adb (Resolve_Array_Aggregate): Skip tag checks for class-wide equivalent types. (Resolve_Aggr_Expr): Assume associated mutably tagged type when class-wide equivalent type is encountered. * sem_attr.adb (Analyze_Attribute): Allow 'Tag on mutably tagged types. (Resolve_Attribute): Detect errors for dependence of mutably tagged extension type component. * sem_ch12.adb (Instantiate_Object): Detect errors for dependence of mutably tagged extension type component. * sem_ch13.adb (Analyze_One_Aspect): Propagate 'Size'Class to class-wide type. (Analyze_Attribute_Definition_Clause): Add handling of 'Size'Class by generating class-wide equivalent types and checking for illegal uses. * sem_ch2.adb (Analyze_Identifier): Generate unchecked conversion for class-wide equivalent types. * sem_ch3.adb (Analyze_Component_Declaration): Avoid unconstrained errors on mutably tagged types. (Analyze_Object_Declaration): Rewrite declarations of mutably tagged types to use class-wide equivalent types. (Array_Type_Declaration): Modify arrays of mutably tagged types to use their corresponding class-wide equivalent types. (Derived_Type_Declaration): Add various checks for mutably tagged derived types. * sem_ch4.adb (Analyze_Allocator): Replace reference to mutably tagged type with cooresponding tagged type. (Process_Indexed_Component): Generate unchecked conversion for class-wide equivalent type. (Analyze_One_Call): Generate unchecked conversion for class-wide equivalent types. (Analyze_Selected_Component): Assume reference to class-wide equivalent type is associated mutably tagged type. (Analyze_Type_Conversion): Generate unchecked conversion for class-wide equivalent type. * sem_ch5.adb (Analyze_Assignment): Assume associated mutably tagged type when class-wide equivalent type is encountered. (Analyze_Iterator_Specification): Detect errors for dependence of mutably tagged extension type component. * sem_ch6.adb (Create_Extra_Formals): Add code to generate extra formal for mutably tagged types to signal if they are constrained. * sem_ch8.adb (Analyze_Object_Renaming): Detect error on renaming of mutably tagged extension type component. (Analyze_Renaming_Primitive_Operation): Detect error on renaming of mutably tagged extension type component. * sem_res.adb (Resolve_Actuals): Allow class-wide arguments on class-wide equivalent types. (Valid_Conversion): Assume associated mutably tagged type when class-wide equivalent type is encountered. * sem_util.adb (Is_Fully_Initialized_Type): Flag mutably tagged types as fully initialized. (Needs_Simple_Initalization): Flag class-wide equivalent types as needing initialization. * gnat_rm.texi: Regenerate. * gcc-interface/Make-lang.in: Add entry for mutably_tagged.o.
2024-06-14ada: Crash checking accessibility level on private typeJustin Squirek1-1/+5
This patch fixes an issue in the compiler whereby calculating a static accessibility level on a private type with an access discriminant resulted in a compile time crash when No_Dynamic_Accessibility_Checks is enabled. gcc/ada/ * accessibility.adb: (Accessibility_Level): Replace call Get_Full_View with call to Full_View since Get_Full_View only works with incomplete types.
2024-06-14ada: Minor tweaks to processing of Aggregate aspectEric Botcazou3-15/+15
The main one is to give the error for Aggregate applied to array types from Analyze_Aspects_At_Freeze_Point instead of Check_Aspect_At_Freeze_Point, as for the other aspects. The message is also changed to be more direct. gcc/ada/ * aspects.ads (Operational_Aspect): Alphabetize. * sem_ch13.ads (Analyze_Aspects_At_Freeze_Point): Fix description. * sem_ch13.adb (Analyze_Aspects_At_Freeze_Point) <Aggregate>: Give the error for array types here instead of... (Analyze_Aspect_Specifications) <Aggregate>: Adjust comment. (Check_Aspect_At_Freeze_Point) <Aggregate>: ...here.
2024-06-14ada: Missing initialization of multidimensional array using slidingJavier Miranda1-21/+33
When a multidimensional array is initialized with an array aggregate, and inner dimensions of the array are initialized with array subaggregates using sliding, the code generated by the compiler does not initialize the inner dimensions of the array. gcc/ada/ * exp_aggr.adb (Must_Slide): Add missing support for multidimensional arrays.
2024-06-14ada: Couple of small cleanups in semantic analysis of aspectsEric Botcazou3-60/+58
The first cleanup is to expose a consistent interface from Sem_Ch13 for the analysis of aspects at various points of the program. The second cleanup is to fix the awkward implementation of the analysis of the specification for the aspects Stable_Properties, Designated_Storage_Model, Storage_Model_Type and Aggregate, which are always delayed, and the incorrect placement of that of the aspect Local_Restrictions, which is never delayed. gcc/ada/ * freeze.adb (Freeze_All): Call Check_Aspects_At_End_Of_Declarations to perform the visibility check for aspects. * sem_ch13.ads (Check_Aspects_At_End_Of_Declarations): Declare. (Check_Aspect_At_Freeze_Point): Move to... (Check_Aspect_At_End_Of_Declarations): Move to... * sem_ch13.adb (Check_Aspect_At_Freeze_Point): ...here. (Check_Aspect_At_End_Of_Declarations): ...here. (Analyze_Aspect_Specifications): Remove peculiar processing for Stable_Properties, Designated_Storage_Model, Storage_Model_Type and Aggregate. Move that of Local_Restrictions around. Reset Aitem at the beginning of the loop for each aspect. (Check_Aspects_At_End_Of_Declarations): New procedure.
2024-06-14ada: Allow implicit dereferenced for uses of 'SuperJustin Squirek1-0/+1
This patch modifies the experimental 'Super attribute to allow an access-valued prefix to be equivalent to Prefix.all'Super. gcc/ada/ * sem_attr.adb: (Analyze_Attribute): Add check for dereference.
2024-06-14ada: Remove unused name of aspect from SnamesEric Botcazou1-1/+0
gcc/ada/ * snames.ads-tmpl (Name_Storage_Model): Delete.
2024-06-14Fix fallout of peeling for gap improvementsRichard Biener2-5/+8
The following hopefully addresses an observed bootstrap issue on aarch64 where maybe-uninit diagnostics occur. It also fixes bogus napkin math from myself when I was confusing rounded up size of a single access with rounded up size of the group accessed in a single scalar iteration. So the following puts in a correctness check, leaving a set of peeling for gaps as insufficient. This could be rectified by splitting the last load into multiple ones but I'm leaving this for a followup, better quickly fix the reported wrong-code. * tree-vect-stmts.cc (get_group_load_store_type): Do not re-use poly-int remain but re-compute with non-poly values. Verify the shortened load is good enough to be covered with a single scalar gap iteration before accepting it. * gcc.dg/vect/pr115385.c: Enable AVX2 if available.
2024-06-14Adjust ix86_rtx_costs for pternlog_operand_p.liuhongt7-7/+44
r15-1100-gec985bc97a0157 improves handling of ternlog instructions, now GCC can recognize lots of pternlog_operand with different variants. The patch adjust rtx_costs for that, so pass_combine can reasonably generate more optimal vpternlog instructions. .i.e for avx512f-vpternlog-3.c, with the patch, 2 vpternlog are combined into one. 1532,1533c1526 < vpternlogd $168, %zmm1, %zmm0, %zmm2 < vpternlogd $0x55, %zmm2, %zmm2, %zmm2 > vpternlogd $87, %zmm1, %zmm0, %zmm2 1732,1733c1725,1726 < vpand %xmm0, %xmm1, %xmm0 < vpternlogd $0x55, %zmm0, %zmm0, %zmm0 > vpternlogd $63, %zmm1, %zmm0, %zmm1 > vmovdqa %xmm1, %xmm0 1804,1805c1797 < vpternlogd $188, %zmm2, %zmm0, %zmm1 < vpternlogd $0x55, %zmm1, %zmm1, %zmm1 > vpternlogd $37, %zmm0, %zmm2, %zmm1 gcc/ChangeLog: * config/i386/i386.cc (ix86_rtx_costs): Adjust rtx_cost for pternlog_operand under AVX512, also adjust VEC_DUPLICATE according since vec_dup:mem can't be that cheap. gcc/testsuite/ChangeLog: * gcc.target/i386/avx2-pr98461.c: Scan either notl or vpternlog. * gcc.target/i386/avx512f-pr96891-3.c: Also scan for inversed condition. * gcc.target/i386/avx512f-vpternlogd-3.c: Adjust vpternlog number to 673. * gcc.target/i386/avx512f-vpternlogd-4.c: Ditto. * gcc.target/i386/avx512f-vpternlogd-5.c: Ditto. * gcc.target/i386/sse2-v1ti-vne.c: Add -mno-avx512f.
2024-06-14Remove one_if_conv for latest Intel processors.liuhongt1-2/+2
The tune is added by PR79390 for SciMark2 on Broadwell. For latest GCC, with and without the -mtune-ctrl=^one_if_conv_insn. GCC will generate the same binary for SciMark2. And for SPEC2017, there's no big impact for SKX/CLX/ICX, and small improvements on SPR and later. gcc/ChangeLog: * config/i386/x86-tune.def (X86_TUNE_ONE_IF_CONV_INSN): Remove latest Intel processors. Co-authored by: Lingling Kong <lingling.kong@intel.com>
2024-06-14i386: More use of m{32,64}bcst addressing modes with ternlog.Roger Sayle2-0/+72
This patch makes more use of m32bcst and m64bcst addressing modes in ix86_expand_ternlog. Previously, the i386 backend would only consider using a m32bcst if the inner mode of the vector was 32-bits, or using m64bcst if the inner mode was 64-bits. For ternlog (and other logic operations) this is a strange restriction, as how the same constant is materialized is dependent upon the mode it is used/operated on. Hence, the V16QI constant {2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2} wouldn't use m??bcst, but (V4SI){0x02020202,0x02020202,0x02020202,0x02020202} which has the same bit pattern would. This can optimized by (re)checking whether a CONST_VECTOR can be broadcast from memory after casting it to VxSI (or for m64bst to VxDI) where x has the appropriate vector size. Taking the test case from pr115407: __attribute__((__vector_size__(64))) char v; void foo() { v = v | v << 7; } Compiled with -O2 -mcmodel=large -mavx512bw GCC 14 generates a 64-byte (512-bit) load from the constant pool: foo: movabsq $v, %rax // 10 movabsq $.LC0, %rdx // 10 vpsllw $7, (%rax), %zmm1 // 7 vmovdqa64 (%rax), %zmm0 // 6 vpternlogd $248, (%rdx), %zmm1, %zmm0 // 7 vmovdqa64 %zmm0, (%rax) // 6 vzeroupper // 3 ret // 1 .LC0: .byte -12 // 64 = 114 bytes .byte -128 ;; repeated another 62 times mainline currently generates two instructions, using interunit broadcast: foo: movabsq $v, %rdx // 10 movl $-2139062144, %eax // 5 vmovdqa64 (%rdx), %zmm2 // 6 vpbroadcastd %eax, %zmm0 // 6 vpsllw $7, %zmm2, %zmm1 // 7 vpternlogd $236, %zmm0, %zmm2, %zmm1 // 7 vmovdqa64 %zmm1, (%rdx) // 6 vzeroupper // 3 ret // 1 = 51 bytes With this patch, we now generate a broadcast addressing mode: foo: movabsq $v, %rax // 10 movabsq $.LC1, %rdx // 10 vmovdqa64 (%rax), %zmm1 // 6 vpsllw $7, %zmm1, %zmm0 // 7 vpternlogd $236, (%rdx){1to16}, %zmm1, %zmm0 // 7 vmovdqa64 %zmm0, (%rax) // 6 vzeroupper // 3 ret // 1 = 50 total Without -mcmodel=large, the benefit is two instructions: foo: vmovdqa64 v(%rip), %zmm1 // 10 vpsllw $7, %zmm1, %zmm0 // 7 vpternlogd $236, .LC2(%rip){1to16}, %zmm1, %zmm0 // 11 vmovdqa64 %zmm0, v(%rip) // 10 vzeroupper // 3 ret // 1 = 42 total 2024-06-14 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/i386/i386-expand.cc (ix86_expand_ternlog): Try performing logic operation in a different vector mode if that enables use of a 32-bit or 64-bit broadcast addressing mode. gcc/testsuite/ChangeLog * gcc.target/i386/pr115407.c: New test case.
2024-06-13expand: constify sepops operand to expand_expr_real_2 and ↵Andrew Pinski4-7/+9
expand_widen_pattern_expr [PR113212] While working on an expand patch back in January I noticed that the first argument (of sepops type) of expand_expr_real_2 could be constified as it was not to be touched by the function (nor should it be). There is code in internal-fn.cc that depends on expand_expr_real_2 not touching the ops argument so constification makes this more obvious. Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: PR middle-end/113212 * expr.h (const_seqpops): New typedef. (expand_expr_real_2): Constify the first argument. * optabs.cc (expand_widen_pattern_expr): Likewise. * optabs.h (expand_widen_pattern_expr): Likewise. * expr.cc (expand_expr_real_2): Likewise (do_store_flag): Likewise. Remove incorrect store to ops->code. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-06-14Daily bump.GCC Administrator6-1/+568
2024-06-13Revert "map packed field type to unpacked for debug info"Alexandre Oliva2-6/+1
This reverts commit ea5c9f25241ae0658180afbcad7f4e298352f561.
2024-06-13RISC-V: Add support for subword atomic loads/storesPatrick O'Neill15-50/+610
Andrea Parri recently pointed out that we were emitting overly conservative fences for seq_cst atomic loads/stores. This adds support for the optimized fences specified in the PSABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-atomic.adoc gcc/ChangeLog: * config/riscv/sync-rvwmo.md: Add support for subword fenced loads/stores. * config/riscv/sync-ztso.md: Ditto. * config/riscv/sync.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Increase test coverage to include longs, shorts, chars, and bools. * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> Tested-by: Andrea Parri <andrea@rivosinc.com>
2024-06-13c: Implement C2Y complex increment/decrement supportJoseph Myers7-2/+308
Support for complex increment and decrement (previously supported as an extension) was voted into C2Y today (paper N3259). Thus, change the pedwarn to a pedwarn_c23 and add associated tests. Note: the type of the 1 to be added / subtracted is underspecified (to be addressed in a subsequent paper), but understood to be intended to be a real type (so the sign of a zero imaginary part is never changed) and this is what is implemented; the tests added include verifying that there is no undesired change to the sign of a zero imaginary part. Bootstrapped with no regressions on x86_64-pc-linux-gnu. gcc/c/ * c-typeck.cc (build_unary_op): Use pedwarn_c23 for complex increment and decrement. gcc/testsuite/ * gcc.dg/c23-complex-1.c, gcc.dg/c23-complex-2.c, gcc.dg/c23-complex-3.c, gcc.dg/c23-complex-4.c, gcc.dg/c2y-complex-1.c, gcc.dg/c2y-complex-2.c: New tests.
2024-06-13rs6000, altivec-2-runnable.c should be a runnable testCarl Love1-1/+1
The test case has "dg-do compile" set not "dg-do run" for a runnable test. This patch changes the dg-do command argument to run. gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog: * gcc.target/powerpc/altivec-2-runnable.c: Change dg-do argument to run.
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