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std::unique_ptr
Revert the changes in r15-1111-ge22b7f741ab54f and fix bootstrap with
GCC 4.8 a different way. The original problem is not related to C++17
guaranteed copy elision, it's related to Core DR 1579 [1], which was
part of C++14 but only implemented in G++ as a C++11 DR with
r5-1576-gfb682f9458c6cf (so GCC 4.8 doesn't implement it).
The original fix causes -Wredundant-move warnings with GCC trunk.
[1] https://cplusplus.github.io/CWG/issues/1579.html
gcc/analyzer/ChangeLog
* constraint-manager.cc (equiv_class::make_dump_widget): Change
return type to match return value and do not use std::move on
return value.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* constraint-manager.h (equiv_class::make_dump_widget): Change
return type.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* program-state.cc (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* program-state.h (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* region-model.cc (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region-model.h (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region.cc (region::make_dump_widget): Likewise.
* region.h (region::make_dump_widget): Likewise.
* store.cc (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* store.h (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* svalue.cc (svalue::make_dump_widget): Likewise.
* svalue.h (svalue::make_dump_widget): Likewise.
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This patch adds uses of force_highpart_subreg to places that
already use force_lowpart_subreg.
gcc/
* config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use
force_highpart_subreg instead of gen_highpart and simplify_gen_subreg.
(aarch64_subvti_scratch_regs): Likewise.
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This patch adds a force_highpart_subreg to go along with the
recently added force_lowpart_subreg.
gcc/
* explow.h (force_highpart_subreg): Declare.
* explow.cc (force_highpart_subreg): New function.
* builtins.cc (expand_builtin_issignaling): Use it.
* expmed.cc (emit_store_flag_1): Likewise.
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This patch makes target-independent code use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg in some places.
The criteria were:
(1) The code is obviously specific to expand (where new pseudos
can be created), or at least would be invalid to call when
!can_create_pseudo_p () and temporaries are needed.
(2) The value is obviously an rvalue rather than an lvalue.
Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.
gcc/
* builtins.cc (expand_builtin_issignaling): Use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg.
* expr.cc (convert_mode_scalar, expand_expr_real_2): Likewise.
* optabs.cc (expand_doubleword_mod): Likewise.
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This patch makes more use of force_lowpart_subreg, similarly
to the recent patch for force_subreg. The criteria were:
(1) The code is obviously specific to expand (where new pseudos
can be created).
(2) The value is obviously an rvalue rather than an lvalue.
gcc/
PR target/115464
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
simplify_gen_subreg and lowpart_subreg.
* config/aarch64/aarch64-sve-builtins-base.cc
(svset_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc
(add_load_store_slice_operand): Likewise.
* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
gcc/testsuite/
PR target/115464
* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
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optabs had a local function called lowpart_subreg_maybe_copy
that is very similar to the lowpart version of force_subreg.
This patch adds a force_lowpart_subreg wrapper around
force_subreg and uses it in optabs.cc.
The only difference between the old and new functions is that
the old one asserted success while the new one doesn't.
It's common not to assert elsewhere when taking subregs;
normally a null result is enough.
Later patches will make more use of the new function.
gcc/
* explow.h (force_lowpart_subreg): Declare.
* explow.cc (force_lowpart_subreg): New function.
* optabs.cc (lowpart_subreg_maybe_copy): Delete.
(expand_absneg_bit): Use force_lowpart_subreg instead of
lowpart_subreg_maybe_copy.
(expand_copysign_bit): Likewise.
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This patch makes target-independent code use force_subreg instead
of simplify_gen_subreg in some places. The criteria were:
(1) The code is obviously specific to expand (where new pseudos
can be created), or at least would be invalid to call when
!can_create_pseudo_p () and temporaries are needed.
(2) The value is obviously an rvalue rather than an lvalue.
(3) The offset wasn't a simple lowpart or highpart calculation;
a later patch will deal with those.
Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.
gcc/
* expmed.cc (store_bit_field_using_insv): Use force_subreg
instead of simplify_gen_subreg.
(store_bit_field_1): Likewise.
(extract_bit_field_as_subreg): Likewise.
(extract_integral_bit_field): Likewise.
(emit_store_flag_1): Likewise.
* expr.cc (convert_move): Likewise.
(convert_modes): Likewise.
(emit_group_load_1): Likewise.
(emit_group_store): Likewise.
(expand_assignment): Likewise.
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This patch makes the aarch64 code use force_subreg instead of
simplify_gen_subreg in more places. The criteria were:
(1) The code is obviously specific to expand (where new pseudos
can be created).
(2) The value is obviously an rvalue rather than an lvalue.
(3) The offset wasn't a simple lowpart or highpart calculation;
a later patch will deal with those.
gcc/
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
Use force_subreg instead of simplify_gen_subreg.
* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc
(svget_impl::expand): Likewise.
(svget_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h
(multireg_permute::expand): Likewise.
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While adding more uses of force_subreg, I realised that it should
be more careful to emit no instructions on failure. This kind of
failure should be very rare, so I don't think it's a case worth
optimising for.
gcc/
* explow.cc (force_subreg): Emit no instructions on failure.
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c23 specifies that the type of a redeclared enumerator is the one of the
previous declaration. Convert initializers with different type accordingly
and emit an error when the value does not fit.
2024-06-01 Martin Uecker <uecker@tugraz.at>
PR c/115109
gcc/c/
* c-decl.cc (build_enumerator): When redeclaring an
enumerator convert value to previous type. For redeclared
enumerators use underlying type for computing the next value.
gcc/testsuite/
* gcc.dg/pr115109.c: New test.
* gcc.dg/c23-tag-enum-6.c: New test.
* gcc.dg/c23-tag-enum-7.c: New test.
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While my r15-1001-g4cf2de9b5268224 PCH PIE power fix change decreased the
.data section sizes (219792 -> 189336), it increased the size of already
huge rs6000_init_generated_builtins generated function, from 218328
to 228668 bytes. That is because there are thousands of array references
to global arrays and we keep constructing the addresses of the arrays
again and again.
Ideally some optimization would figure out we have a single function which
has
461 rs6000_overload_info
1257 rs6000_builtin_info_fntype
1768 rs6000_builtin_decls
2548 rs6000_instance_info_fntype
array references and that maybe it might be a good idea to just preload
the addresses of those arrays into some register if it decreases code size
and doesn't slow things down.
The function actually is called just once and is huge, so code size is even
more important than speed, which is dominated by all the GC allocations
anyway.
Until that is done, here is a slightly cleaner version of the hack, which
makes the function noipa (so that LTO doesn't undo it) for GCC 8.1+ and
passes the 4 arrays as arguments to the function from the caller.
This decreases the function size from 228668 bytes to 207572 bytes.
2024-06-18 Jakub Jelinek <jakub@redhat.com>
PR target/115324
* config/rs6000/rs6000-gen-builtins.cc (write_decls): Change
declaration of rs6000_init_generated_builtins from no arguments
to 4 pointer arguments.
(write_init_bif_table): Change rs6000_builtin_info_fntype to
builtin_info_fntype and rs6000_builtin_decls to builtin_decls.
(write_init_ovld_table): Change rs6000_instance_info_fntype to
instance_info_fntype, rs6000_builtin_decls to builtin_decls and
rs6000_overload_info to overload_info.
(write_init_file): Add __noipa__ attribute to
rs6000_init_generated_builtins for GCC 8.1+ and change the function
from no arguments to 4 pointer arguments. Change rs6000_builtin_decls
to builtin_decls.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Adjust
rs6000_init_generated_builtins caller.
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The following fixes a bad final value being used when doing single-lane
SLP integer induction cond reduction vectorization.
PR tree-optimization/115493
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Use
the first scalar result.
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Automatic arrays that are not address-taken should not be subject to
store data races. This applies to OMP SIMD in-branch lowered
functions result array which for the testcase otherwise prevents
vectorization with SSE and for AVX and AVX512 ends up with spurious
.MASK_STORE to the stack surviving.
This inefficiency was noted in PR111793.
I've introduced ref_can_have_store_data_races, commonizing uses
of flag_store_data_races in if-conversion, cselim and store motion.
PR tree-optimization/111793
* tree-ssa-alias.h (ref_can_have_store_data_races): Declare.
* tree-ssa-alias.cc (ref_can_have_store_data_races): New
function.
* tree-if-conv.cc (ifcvt_memrefs_wont_trap): Use
ref_can_have_store_data_races to allow more unconditional
stores.
* tree-ssa-loop-im.cc (execute_sm): Likewise.
* tree-ssa-phiopt.cc (cond_store_replacement): Likewise.
* gcc.dg/vect/vect-simd-clone-21.c: New testcase.
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As noted in PR114842, most of the test cases which require
effective target check powerpc_altivec_ok actually care about
if ALTIVEC feature is enabled, and they should adopt effective
target powerpc_altivec instead. Otherwise, when users are
specifying extra option -mno-altivec in RUNTESTFLAGS, the check
powerpc_altivec_ok returns true then the test case would be
tested without ALTIVEC so it would fail. With commit r15-716,
dg-options and dg-additional-options can be taken into account
when evaluating powerpc_altivec, so this patch also moves
dg-{additional,}-options lines before dg-require-effective-target
to make it effective.
PR testsuite/114842
gcc/testsuite/ChangeLog:
* c-c++-common/pr72747-1.c: Replace powerpc_altivec_ok with
powerpc_altivec, move dg-options and dg-additional-options lines
before dg-require-effective-target lines when it doesn't cause
any side effect like note message.
* c-c++-common/pr72747-2.c: Likewise.
* g++.dg/torture/pr79905.C: Likewise.
* g++.target/powerpc/altivec-1.C: Likewise.
* g++.target/powerpc/altivec-10.C: Likewise.
* g++.target/powerpc/altivec-11.C: Likewise.
* g++.target/powerpc/altivec-12.C: Likewise.
* g++.target/powerpc/altivec-13.C: Likewise.
* g++.target/powerpc/altivec-14.C: Likewise.
* g++.target/powerpc/altivec-15.C: Likewise.
* g++.target/powerpc/altivec-16.C: Likewise.
* g++.target/powerpc/altivec-17.C: Likewise.
* g++.target/powerpc/altivec-18.C: Likewise.
* g++.target/powerpc/altivec-2.C: Likewise.
* g++.target/powerpc/altivec-4.C: Likewise.
* g++.target/powerpc/altivec-5.C: Likewise.
* g++.target/powerpc/altivec-6.C: Likewise.
* g++.target/powerpc/altivec-7.C: Likewise.
* g++.target/powerpc/altivec-8.C: Likewise.
* g++.target/powerpc/altivec-9.C: Likewise.
* g++.target/powerpc/altivec-cell-1.C: Likewise.
* g++.target/powerpc/altivec-cell-5.C: Likewise.
* g++.target/powerpc/altivec-types-1.C: Likewise.
* g++.target/powerpc/altivec-types-2.C: Likewise.
* g++.target/powerpc/altivec-types-3.C: Likewise.
* g++.target/powerpc/altivec-types-4.C: Likewise.
* gcc.target/powerpc/altivec-1-runnable.c: Likewise.
* gcc.target/powerpc/altivec-11.c: Likewise.
* gcc.target/powerpc/altivec-13.c: Likewise.
* gcc.target/powerpc/altivec-14.c: Likewise.
* gcc.target/powerpc/altivec-15.c: Likewise.
* gcc.target/powerpc/altivec-16.c: Likewise.
* gcc.target/powerpc/altivec-17.c: Likewise.
* gcc.target/powerpc/altivec-18.c: Likewise.
* gcc.target/powerpc/altivec-19.c: Likewise.
* gcc.target/powerpc/altivec-2.c: Likewise.
* gcc.target/powerpc/altivec-21.c: Likewise.
* gcc.target/powerpc/altivec-22.c: Likewise.
* gcc.target/powerpc/altivec-23.c: Likewise.
* gcc.target/powerpc/altivec-25.c: Likewise.
* gcc.target/powerpc/altivec-26.c: Likewise.
* gcc.target/powerpc/altivec-27.c: Likewise.
* gcc.target/powerpc/altivec-28.c: Likewise.
* gcc.target/powerpc/altivec-29.c: Likewise.
* gcc.target/powerpc/altivec-30.c: Likewise.
* gcc.target/powerpc/altivec-31.c: Likewise.
* gcc.target/powerpc/altivec-32.c: Likewise.
* gcc.target/powerpc/altivec-33.c: Likewise.
* gcc.target/powerpc/altivec-34.c: Likewise.
* gcc.target/powerpc/altivec-35.c: Likewise.
* gcc.target/powerpc/altivec-36.c: Likewise.
* gcc.target/powerpc/altivec-4.c: Likewise.
* gcc.target/powerpc/altivec-5.c: Likewise.
* gcc.target/powerpc/altivec-6.c: Likewise.
* gcc.target/powerpc/altivec-7.c: Likewise.
* gcc.target/powerpc/altivec-8.c: Likewise.
* gcc.target/powerpc/altivec-9.c: Likewise.
* gcc.target/powerpc/altivec-cell-1.c: Likewise.
* gcc.target/powerpc/altivec-cell-5.c: Likewise.
* gcc.target/powerpc/altivec-cell-6.c: Likewise.
* gcc.target/powerpc/altivec-cell-7.c: Likewise.
* gcc.target/powerpc/altivec-perm-1.c: Likewise.
* gcc.target/powerpc/altivec-perm-2.c: Likewise.
* gcc.target/powerpc/altivec-perm-3.c: Likewise.
* gcc.target/powerpc/altivec-perm-4.c: Likewise.
* gcc.target/powerpc/altivec-pr22085.c: Likewise.
* gcc.target/powerpc/altivec-splat.c: Likewise.
* gcc.target/powerpc/altivec-types-1.c: Likewise.
* gcc.target/powerpc/altivec-types-2.c: Likewise.
* gcc.target/powerpc/altivec-types-3.c: Likewise.
* gcc.target/powerpc/altivec-types-4.c: Likewise.
* gcc.target/powerpc/altivec-volatile.c: Likewise.
* gcc.target/powerpc/altivec_vld_vst_addr-1.c: Likewise.
* gcc.target/powerpc/bool2-av.c: Likewise.
* gcc.target/powerpc/bool2-p5.c: Likewise.
* gcc.target/powerpc/bool3-av.c: Likewise.
* gcc.target/powerpc/builtin-vec-sums-be-int.c: Likewise.
* gcc.target/powerpc/builtins-3.c: Likewise.
* gcc.target/powerpc/cell_builtin-3.c: Likewise.
* gcc.target/powerpc/cell_builtin-5.c: Likewise.
* gcc.target/powerpc/cell_builtin-6.c: Likewise.
* gcc.target/powerpc/cell_builtin-7.c: Likewise.
* gcc.target/powerpc/cell_builtin-8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-char.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-short.c: Likewise.
* gcc.target/powerpc/fold-vec-add-1.c: Likewise.
* gcc.target/powerpc/fold-vec-add-2.c: Likewise.
* gcc.target/powerpc/fold-vec-add-3.c: Likewise.
* gcc.target/powerpc/fold-vec-add-5.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-char.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-float.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-int.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-short.c: Likewise.
* gcc.target/powerpc/fold-vec-madd-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-float.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-int.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-short.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-char.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-int.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-short.c: Likewise.
* gcc.target/powerpc/fold-vec-missing-lhs.c: Likewise.
* gcc.target/powerpc/fold-vec-msum-char.c: Likewise.
* gcc.target/powerpc/fold-vec-msum-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mule-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mule-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mult-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mult-short.c: Likewise.
* gcc.target/powerpc/fold-vec-pack-int.c: Likewise.
* gcc.target/powerpc/fold-vec-pack-short.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-char.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-float.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-int.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-pixel.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-short.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-char.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-int.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-left.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-short.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-32.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-8.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-char.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-int.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-short.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-char.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-int.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-short.c: Likewise.
* gcc.target/powerpc/fold-vec-st-char.c: Likewise.
* gcc.target/powerpc/fold-vec-st-float.c: Likewise.
* gcc.target/powerpc/fold-vec-st-int.c: Likewise.
* gcc.target/powerpc/fold-vec-st-short.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-char.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-float.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-int.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-short.c: Likewise.
* gcc.target/powerpc/fold-vec-sums-int.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-char.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-pixel.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-short.c: Likewise.
* gcc.target/powerpc/ppc-fma-3.c: Likewise.
* gcc.target/powerpc/ppc-fma-4.c: Likewise.
* gcc.target/powerpc/ppc-fma-7.c: Likewise.
* gcc.target/powerpc/ppc-vector-memcpy.c: Likewise.
* gcc.target/powerpc/ppc-vector-memset.c: Likewise.
* gcc.target/powerpc/pr100645.c: Likewise.
* gcc.target/powerpc/pr101384-1.c: Likewise.
* gcc.target/powerpc/pr101384-2.c: Likewise.
* gcc.target/powerpc/pr103353.c: Likewise.
* gcc.target/powerpc/pr103702.c: Likewise.
* gcc.target/powerpc/pr108348-1.c: Likewise.
* gcc.target/powerpc/pr108348-2.c: Likewise.
* gcc.target/powerpc/pr109932-1.c: Likewise.
* gcc.target/powerpc/pr109932-2.c: Likewise.
* gcc.target/powerpc/pr110776.c: Likewise.
* gcc.target/powerpc/pr16155.c: Likewise.
* gcc.target/powerpc/pr16286.c: Likewise.
* gcc.target/powerpc/pr27158.c: Likewise.
* gcc.target/powerpc/pr37168.c: Likewise.
* gcc.target/powerpc/pr47197.c: Likewise.
* gcc.target/powerpc/pr67071-1.c: Likewise.
* gcc.target/powerpc/pr67071-2.c: Likewise.
* gcc.target/powerpc/pr67071-3.c: Likewise.
* gcc.target/powerpc/pr70010-2.c: Likewise.
* gcc.target/powerpc/pr70010-3.c: Likewise.
* gcc.target/powerpc/pr71297.c: Likewise.
* gcc.target/powerpc/pr82112.c: Likewise.
* gcc.target/powerpc/pr84220-sld.c: Likewise.
* gcc.target/powerpc/pr84878.c: Likewise.
* gcc.target/powerpc/pr86731-fwrapv.c: Likewise.
* gcc.target/powerpc/pr86731.c: Likewise.
* gcc.target/powerpc/pr88100.c: Likewise.
* gcc.target/powerpc/pragma_power6.c: Likewise.
* gcc.target/powerpc/pragma_power7.c: Likewise.
* gcc.target/powerpc/pragma_power9.c: Likewise.
* gcc.target/powerpc/swaps-p8-21.c: Likewise.
* gcc.target/powerpc/unpack-vectorize-1.c: Likewise.
* gcc.target/powerpc/vec-cg.c: Likewise.
* gcc.target/powerpc/vec-cmpne.c: Likewise.
* gcc.target/powerpc/vec-constvolatile.c: Likewise.
* gcc.target/powerpc/vec-mult-char-2.c: Likewise.
* gcc.target/powerpc/vec-rotate-1.c: Likewise.
* gcc.target/powerpc/vec-rotate-3.c: Likewise.
* gcc.target/powerpc/vec-shift.c: Likewise.
* g++.target/powerpc/altivec-3.C: Likewise.
* g++.target/powerpc/altivec-cell-2.C: Likewise.
* g++.target/powerpc/altivec-cell-3.C: Likewise.
* g++.target/powerpc/altivec-cell-4.C: Likewise.
* g++.target/powerpc/const2.C: Likewise.
* gcc.dg/debug/dwarf2/const-2.c: Likewise.
* gcc.dg/dfp/altivec-types.c: Likewise.
* gcc.dg/ubsan/pr88234.c: Likewise.
* gcc.dg/vect/vect-82_64.c: Likewise.
* gcc.dg/vect/vect-83_64.c: Likewise.
* gcc.target/powerpc/altivec-1.c: Likewise.
* gcc.target/powerpc/altivec-10.c: Likewise.
* gcc.target/powerpc/altivec-12.c: Likewise.
* gcc.target/powerpc/altivec-20.c: Likewise.
* gcc.target/powerpc/altivec-24.c: Likewise.
* gcc.target/powerpc/altivec-3.c: Likewise.
* gcc.target/powerpc/altivec-cell-2.c: Likewise.
* gcc.target/powerpc/altivec-cell-3.c: Likewise.
* gcc.target/powerpc/altivec-cell-4.c: Likewise.
* gcc.target/powerpc/altivec-consts.c: Likewise.
* gcc.target/powerpc/altivec-macros.c: Likewise.
* gcc.target/powerpc/altivec-varargs-1.c: Likewise.
* gcc.target/powerpc/altivec-vec-merge.c: Likewise.
* gcc.target/powerpc/darwin-save-world-1.c: Likewise.
* gcc.target/powerpc/le-altivec-consts.c: Likewise.
* gcc.target/powerpc/pr35907.c: Likewise.
* gcc.target/powerpc/vec-mult-char-1.c: Likewise.
|
|
gcc/ChangeLog:
* config/i386/avxintrin.h: Move cmp[p|s][s|d] to [e|x]mmintrin.h,
and move macros to xmmintrin.h
* config/i386/emmintrin.h: Add cmp[p|s]s intrins.
* config/i386/i386-builtin.def: Modify __builtin_ia32_cmp[p|s][s|d].
* config/i386/i386-expand.cc
(ix86_expand_args_builtin): Raise error when imm is in range of
[8, 32] without avx.
* config/i386/predicates.md (cmpps_imm_operand): New predicate.
* config/i386/sse.md (avx_cmp<mode>3): Modefy define_insn.
(avx_vmcmp<mode>3): Ditto.
* config/i386/xmmintrin.h (_CMP_EQ_OQ): New macro for sse/sse2.
(_CMP_LT_OS): Ditto
(_CMP_LE_OS): Ditto
(_CMP_UNORD_Q): Ditto
(_CMP_NEQ_UQ): Ditto
(_CMP_NLT_US): Ditto
(_CMP_NLE_US): Ditto
(_CMP_ORD_Q): Ditto
(_mm_cmp_ps): Move intrin from avxintrin.h to xmmintrin.h
(_mm_cmp_ss): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/sse-cmp-1.c: New test.
* gcc.target/i386/sse-cmp-2.c: Ditto.
* gcc.target/i386/sse-cmp-error.c: Ditto.
|
|
|
|
This aarch64 sve specific code was fixed by r15-917-gc9842f99042454
which added a riscv specific testcase so adding an aarch64 one to test
the fix does not regress is a good idea.
Committed as obvious after testing the testcase for aarch64-linux-gnu.
PR tree-optimization/97405
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pr97405-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
|
|
insertions
Combine will use zero_extract destinations for certain bitfield
insertions. If the bitfield is a single bit constant, then we can use
bset/bclr.
In this case we are only dealing with word_mode objects, so we don't
have to worry about the SI->DI extension issues for TARGET_64BIT.
The testcase was derived from 502.gcc in spec from the RAU team.
An earlier version of this (TARGET_64BIT only) went through Ventana's CI
system. This version has gone though mine after generalizing it to
handle rv32 as well. I'll wait for pre-commit CI to render its verdict
before moving forward.
gcc/
* config/riscv/bitmanip.md (bsetclr_zero_extract): New pattern.
gcc/testsuite/
* gcc.target/riscv/zbs-zext-3.c: New test.
|
|
gcc/c-family/
* c-ada-spec.cc (is_float16): New predicate.
(dump_ada_node) <REAL_TYPE>: Call it.
|
|
The option_map array for most entries contains just non-NULL opt0
{ "-Wno-", NULL, "-W", false, true },
{ "-fno-", NULL, "-f", false, true },
{ "-gno-", NULL, "-g", false, true },
{ "-mno-", NULL, "-m", false, true },
{ "--debug=", NULL, "-g", false, false },
{ "--machine-", NULL, "-m", true, false },
{ "--machine-no-", NULL, "-m", false, true },
{ "--machine=", NULL, "-m", false, false },
{ "--machine=no-", NULL, "-m", false, true },
{ "--machine", "", "-m", false, false },
{ "--machine", "no-", "-m", false, true },
{ "--optimize=", NULL, "-O", false, false },
{ "--std=", NULL, "-std=", false, false },
{ "--std", "", "-std=", false, false },
{ "--warn-", NULL, "-W", true, false },
{ "--warn-no-", NULL, "-W", false, true },
{ "--", NULL, "-f", true, false },
{ "--no-", NULL, "-f", false, true }
and so add_misspelling_candidates works correctly for it, but 3 out of
these,
{ "--machine", "", "-m", false, false },
{ "--machine", "no-", "-m", false, true },
and
{ "--std", "", "-std=", false, false },
use non-NULL opt1. That says that
--machine foo
should map to
-mfoo
and
--machine no-foo
should map to
-mno-foo
and
--std c++17
should map to
-std=c++17
add_misspelling_canidates was not handling this, so it hapilly
registered say
--stdc++17
or
--machineavx512
(twice) as spelling alternatives, when those options aren't recognized.
Instead we support
--std c++17
or
--machine avx512
--machine no-avx512
The following patch fixes that. On this particular testcase, we no longer
suggest anything, even when among the suggestion is say that
--std c++17
or
-std=c++17
etc.
2024-06-17 Jakub Jelinek <jakub@redhat.com>
PR driver/115440
* opts-common.cc (add_misspelling_candidates): If opt1 is non-NULL,
add a space and opt1 to the alternative suggestion text.
* g++.dg/cpp1z/pr115440.C: New test.
|
|
gcc/testsuite/ChangeLog:
* g++.dg/torture/vshuf-mem.C: Use -march=z14 only, if the we are
on a machine which can actually run it.
|
|
C2Y has adopted support for alignof applied to incomplete array types
(N3273). Add this support to GCC. As the relevant checks are in
c-family code that doesn't have access to functions such as
pedwarn_c23, this remains a hard error for older versions and isn't
handled by -Wc23-c2y-compat, although preferably it would work like
pedwarn_c23 (pedwarn-if-pedantic for older versions, warning with
-Wc23-c2y-compat in C2Y mode).
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
gcc/c-family/
* c-common.cc (c_sizeof_or_alignof_type): Allow alignof on an
incomplete array type for C2Y.
gcc/testsuite/
* gcc.dg/c23-align-10.c, gcc.dg/c2y-align-1.c,
gcc.dg/c2y-align-2.c: New tests.
|
|
The warning code uses %D to print the ARRAY_REF first operands.
That works in the most common case where those operands are decls, but
as can be seen on the following testcase, they can be other expressions
with array type.
Just changing %D to %E isn't enough, because then the diagnostics can
suggest something like
note: use '&(x) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0] == &(y) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0]' to compare the addresses
which is a bad suggestion, the %E printing doesn't know that the
warning code will want to add & before it and [0] after it.
So, the following patch adds ()s around the operand as well, but does
that only for non-decls, for decls keeps it as &arr[0] like before.
2024-06-17 Jakub Jelinek <jakub@redhat.com>
PR c/115290
* c-warn.cc (do_warn_array_compare): Use %E rather than %D for
printing op0 and op1; if those operands aren't decls, also print
parens around them.
* c-c++-common/Warray-compare-3.c: New test.
|
|
if float/double are same size [PR115511]
On AVR and SH with some options sizeof (float) == sizeof (double) and
the 2 types have the same set of values.
http://eel.is/c++draft/conv.rank#2.2 for this says that double still
has bigger rank than float and http://eel.is/c++draft/conv.rank#2.2
says that extended type with the same set of values as more than one
standard floating point type shall have the same rank as double.
I've implemented the latter rule as
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
with the _Float64/double/long double case having same mode case (various
targets with -mlong-double-64) in mind.
But never thought there are actually targets where float and double
are the same, that needs handling too, if cnt > 1 (that is the extended
type mv1 has same set of values as 2 or 3 of float/double/long double)
and mv2 is float, we need to return 2, because mv1 in that case should
have same rank as double and double has bigger rank than float.
2024-06-17 Jakub Jelinek <jakub@redhat.com>
PR target/111343
PR c++/115511
* typeck.cc (cp_compare_floating_point_conversion_ranks): If an
extended floating point type mv1 has same set of values as more
than one standard floating point type and mv2 is float, return 2.
* g++.dg/cpp23/ext-floating18.C: New test.
|
|
Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure
check to prevent emitting Zaamo/Zalrsc in the arch string when the
assember does not support it.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Skip zaamo/zalrsc when not
supported by the assembler.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add zaamo/zalrsc assmeber check.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V
|
|
gcc:
* doc/install.texi (Configuration): Mark up __cxa_atexit as @code.
|
|
We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles. For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call. The fix is to compute the ROP hash save location for all
compiles.
2024-06-14 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/115389
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
rop_hash_save_offset for non-Altivec compiles.
gcc/testsuite
PR target/115389
* gcc.target/powerpc/pr115389.c: New test.
|
|
Another case of being able to safely use bset for 1 << n. In this case
the (1 << n) is explicitly zero extended from SI to DI. Two things to
keep in mind. The (1 << n) is done in SImode. So it doesn't directly
define bits 32..63 and those bits are cleared by the explicit zero
extension. Second if N is out of SImode's range, then the original
source level construct was undefined.
Thus we can use bset with x0 as our source input.
I think this testcase was from the RAU team. It doesn't immediately
look like something from SPEC, but that's where they were primarily focused.
This has been through Ventana's CI system in the past. I've also
recently added zbs testing to my own tester and naturally this passed
there as well. I'll wait for the pre-commit CI to do its thing before
moving forward. The plan would be to commit after passing.
gcc/
* config/riscv/bitmanip.md (bsetdi_2): New pattern.
gcc/testsuite/
* gcc.target/riscv/zbs-zext-2.c: New test.
|
|
When there's a permute after an extern vector we can run into a case
that didn't consider the scheduled node being a permute which lacks
a representative.
PR tree-optimization/115508
* tree-vect-slp.cc (vect_schedule_slp_node): Guard check on
representative.
* gcc.target/i386/pr115508.c: New testcase.
|
|
This adds a testcase for the PR fixed with reversal of
r15-204-g7c469a9fc78550.
PR tree-optimization/115492
* gcc.dg/torture/pr115492.c: New testcase.
|
|
This reverts commit 7c469a9fc785505dc350aba60311812c2bb0c1b5.
|
|
Now that all remaining users of value_range have been renamed to
int_range<>, we can reclaim value_range as a temporary, thus removing
the annoying CamelCase.
gcc/ChangeLog:
* data-streamer-in.cc (streamer_read_value_range): Rename
Value_Range to value_range.
* data-streamer.h (streamer_read_value_range): Same.
* gimple-pretty-print.cc (dump_ssaname_info): Same.
* gimple-range-cache.cc (ssa_block_ranges::dump): Same.
(ssa_lazy_cache::merge): Same.
(block_range_cache::dump): Same.
(ssa_cache::merge_range): Same.
(ssa_cache::dump): Same.
(ranger_cache::edge_range): Same.
(ranger_cache::propagate_cache): Same.
(ranger_cache::fill_block_cache): Same.
(ranger_cache::resolve_dom): Same.
(ranger_cache::range_from_dom): Same.
(ranger_cache::register_inferred_value): Same.
* gimple-range-fold.cc (op1_range): Same.
(op2_range): Same.
(fold_relations): Same.
(fold_using_range::range_of_range_op): Same.
(fold_using_range::range_of_phi): Same.
(fold_using_range::range_of_call): Same.
(fold_using_range::condexpr_adjust): Same.
(fold_using_range::range_of_cond_expr): Same.
(fur_source::register_outgoing_edges): Same.
* gimple-range-fold.h (gimple_range_type): Same.
(gimple_range_ssa_p): Same.
* gimple-range-gori.cc (gori_compute::compute_operand_range): Same.
(gori_compute::logical_combine): Same.
(gori_compute::refine_using_relation): Same.
(gori_compute::compute_operand1_range): Same.
(gori_compute::compute_operand2_range): Same.
(gori_compute::compute_operand1_and_operand2_range): Same.
(gori_calc_operands): Same.
(gori_name_helper): Same.
* gimple-range-infer.cc (gimple_infer_range::check_assume_func): Same.
(gimple_infer_range::gimple_infer_range): Same.
(infer_range_manager::maybe_adjust_range): Same.
(infer_range_manager::add_range): Same.
* gimple-range-infer.h: Same.
* gimple-range-op.cc
(gimple_range_op_handler::gimple_range_op_handler): Same.
(gimple_range_op_handler::calc_op1): Same.
(gimple_range_op_handler::calc_op2): Same.
(gimple_range_op_handler::maybe_builtin_call): Same.
* gimple-range-path.cc (path_range_query::internal_range_of_expr): Same.
(path_range_query::ssa_range_in_phi): Same.
(path_range_query::compute_ranges_in_phis): Same.
(path_range_query::compute_ranges_in_block): Same.
(path_range_query::add_to_exit_dependencies): Same.
* gimple-range-trace.cc (debug_seed_ranger): Same.
* gimple-range.cc (gimple_ranger::range_of_expr): Same.
(gimple_ranger::range_on_entry): Same.
(gimple_ranger::range_on_edge): Same.
(gimple_ranger::range_of_stmt): Same.
(gimple_ranger::prefill_stmt_dependencies): Same.
(gimple_ranger::register_inferred_ranges): Same.
(gimple_ranger::register_transitive_inferred_ranges): Same.
(gimple_ranger::export_global_ranges): Same.
(gimple_ranger::dump_bb): Same.
(assume_query::calculate_op): Same.
(assume_query::calculate_phi): Same.
(assume_query::dump): Same.
(dom_ranger::range_of_stmt): Same.
* ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Same.
(ipa_vr_operation_and_type_effects): Same.
(ipa_value_range_from_jfunc): Same.
(propagate_bits_across_jump_function): Same.
(propagate_vr_across_jump_function): Same.
(ipcp_store_vr_results): Same.
* ipa-cp.h: Same.
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
(evaluate_properties_for_edge): Same.
* ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Same.
(ipa_vr::get_vrange): Same.
(ipa_vr::streamer_read): Same.
(ipa_vr::streamer_write): Same.
(ipa_vr::dump): Same.
(ipa_set_jfunc_vr): Same.
(ipa_compute_jump_functions_for_edge): Same.
(ipcp_get_parm_bits): Same.
(ipcp_update_vr): Same.
(ipa_record_return_value_range): Same.
(ipa_return_value_range): Same.
* ipa-prop.h (ipa_return_value_range): Same.
(ipa_record_return_value_range): Same.
* range-op.h (range_cast): Same.
* tree-ssa-dom.cc
(dom_opt_dom_walker::set_global_ranges_from_unreachable_edges): Same.
(cprop_operand): Same.
* tree-ssa-loop-ch.cc (loop_static_stmt_p): Same.
* tree-ssa-loop-niter.cc (record_nonwrapping_iv): Same.
* tree-ssa-loop-split.cc (split_at_bb_p): Same.
* tree-ssa-phiopt.cc (value_replacement): Same.
* tree-ssa-strlen.cc (get_range): Same.
* tree-ssa-threadedge.cc (hybrid_jt_simplifier::simplify): Same.
(hybrid_jt_simplifier::compute_exit_dependencies): Same.
* tree-ssanames.cc (set_range_info): Same.
(duplicate_ssa_name_range_info): Same.
* tree-vrp.cc (remove_unreachable::handle_early): Same.
(remove_unreachable::remove_and_update_globals): Same.
(execute_ranger_vrp): Same.
* value-query.cc (range_query::value_of_expr): Same.
(range_query::value_on_edge): Same.
(range_query::value_of_stmt): Same.
(range_query::value_on_entry): Same.
(range_query::value_on_exit): Same.
(range_query::get_tree_range): Same.
* value-range-storage.cc (vrange_storage::set_vrange): Same.
* value-range.cc (Value_Range::dump): Same.
(value_range::dump): Same.
(debug): Same.
* value-range.h (enum value_range_discriminator): Same.
(class vrange): Same.
(class Value_Range): Same.
(class value_range): Same.
(Value_Range::Value_Range): Same.
(value_range::value_range): Same.
(Value_Range::~Value_Range): Same.
(value_range::~value_range): Same.
(Value_Range::set_type): Same.
(value_range::set_type): Same.
(Value_Range::init): Same.
(value_range::init): Same.
(Value_Range::operator=): Same.
(value_range::operator=): Same.
(Value_Range::operator==): Same.
(value_range::operator==): Same.
(Value_Range::operator!=): Same.
(value_range::operator!=): Same.
(Value_Range::supports_type_p): Same.
(value_range::supports_type_p): Same.
* vr-values.cc (simplify_using_ranges::fold_cond_with_ops): Same.
(simplify_using_ranges::legacy_fold_cond): Same.
|
|
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-zu-1.c: Add attribute for noinline,
and target apx.
* gcc.target/i386/apx-zu-2.c: Add target-support check.
|
|
gcc/ChangeLog:
PR target/115161
* config/i386/i386-builtin.def: Change CODE_FOR_* for cvtt*'s builtins.
* config/i386/sse.md:
(unspec_avx512fp16_fix<vcvtt_uns_suffix>
_trunc<mode>2<mask_name><round_saeonly_name>):
Use UNSPEC instead of FIX/UNSIGNED_FIX.
(unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name>):
Ditto.
(unspec_avx512fp16_fix<vcvtt_uns_suffix>_truncv2di2<mask_name>): Ditto.
(unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<round_saeonly_name>):
Ditto.
(unspec_sse_cvttps2pi): Ditto.
(unspec_sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Ditto.
(unspec_fix<vcvtt_uns_suffix>_truncv16sfv16si2<mask_name><round_saeonly_name>):
Ditto.
(unspec_fix_truncv8sfv8si2<mask_name>): Ditto.
(unspec_fix_truncv4sfv4si2<mask_name>): Ditto.
(unspec_sse2_cvttpd2pi): Ditto.
(unspec_fixuns_truncv2dfv2si2): Ditto.
(unspec_avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>):
Ditto.
(unspec_avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>):
Ditto.
(unspec_sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>): Ditto.
(unspec_fix<vcvtt_uns_suffix>_truncv8dfv8si2<mask_name><round_saeonly_name>):
Ditto.
(*unspec_fixuns_truncv2dfv2si2): Ditto.
(unspec_fixuns_truncv2dfv2si2_mask): Ditto.
(unspec_fix_truncv4dfv4si2<mask_name>): Ditto.
(unspec_fixuns_truncv4dfv4si2<mask_name>): Ditto.
(unspec_fix<vcvtt_uns_suffix>
_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
Ditto.
(unspec_fix<vcvtt_uns_suffix>
_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
Ditto.
(unspec_avx512dq_fix<vcvtt_uns_suffix>_truncv2sfv2di2<mask_name>):
Ditto.
(<mask_codefor>unspec_fixuns_trunc<mode><sseintvecmodelower>2<mask_name>):
Ditto.
(unspec_sse2_cvttpd2dq<mask_name>): Ditto.
gcc/testsuite/ChangeLog:
PR target/115161
* gcc.target/i386/pr115161-1.c: New test.
|
|
PR fortran/96418
PR fortran/103112
gcc/fortran/ChangeLog:
* trans.cc (gfc_deallocate_with_status): Check that object to deref
is an array, before applying array deref.
gcc/testsuite/ChangeLog:
* gfortran.dg/coarray_alloc_comp_3.f08: Moved to...
* gfortran.dg/coarray/alloc_comp_8.f90: ...here.
Should be tested for both -fcoarray=single and lib, resp.
* gfortran.dg/coarray_alloc_comp_4.f08: Fix program name.
|
|
This patch updates the GCC x86 backend to efficiently handle
odd, incrementally increasing permutations of BF16 vectors
using the cvtne2ps2bf16 instruction.
It modifies ix86_vectorize_vec_perm_const to support these operations
and adds a specific predicate to ensure proper sequence handling.
gcc/ChangeLog:
* config/i386/i386-expand.cc
(ix86_vectorize_vec_perm_const): Convert BF to HI using subreg.
* config/i386/predicates.md
(vcvtne2ps2bf_parallel): New define_insn_and_split.
* config/i386/sse.md
(vpermt2_sepcial_bf16_shuffle_<mode>): New predicates matches odd increasing perm.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vpermt2-special-bf16-shufflue.c: New test.
|
|
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vgm-df-1.c: Removed.
* gcc.target/s390/vector/vgm-di-1.c: Removed.
* gcc.target/s390/vector/vgm-hi-1.c: Removed.
* gcc.target/s390/vector/vgm-int128-1.c: Removed.
* gcc.target/s390/vector/vgm-longdouble-1.c: Removed.
* gcc.target/s390/vector/vgm-qi-1.c: Removed.
* gcc.target/s390/vector/vgm-sf-1.c: Removed.
* gcc.target/s390/vector/vgm-si-1.c: Removed.
* gcc.target/s390/vector/vgm-ti-1.c: Removed.
|
|
This implements a V2SF -> V2DF extend.
gcc/ChangeLog:
* config/s390/vector.md (*vmrhf_half<mode>): New.
(extendv2sfv2df2): New.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vec-extend-3.c: New test.
|
|
For the moment I deliberately left out one-element QHS vectors since it
is unclear whether these are pathological cases or whether they are
really used. If we ever get an extend for V1DI -> V1TI we should
reconsider this.
As a side-effect this fixes PR115261.
gcc/ChangeLog:
PR target/115261
* config/s390/s390.md (any_extend,extend_insn,zero_extend):
New code attributes and code iterator.
* config/s390/vector.md (V_EXTEND): New mode iterator.
(<extend_insn><V_EXTEND:mode><vec_2x_wide>2): New insn.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vec-extend-1.c: New test.
* gcc.target/s390/vector/vec-extend-2.c: New test.
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Starting with r14-5628-g53ba8d669550d3 interprocedural VRP became strong
enough in order to render these tests useless. Fixed by disabling IPA.
gcc/testsuite/ChangeLog:
* gcc.target/s390/nobp-table-jump-inline-z10.c: Do not perform
IPA.
* gcc.target/s390/nobp-table-jump-inline-z900.c: Dito.
* gcc.target/s390/nobp-table-jump-z10.c: Dito.
* gcc.target/s390/nobp-table-jump-z900.c: Dito.
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With the change of r15-787-g57e04879389f9c I forgot to also update this
test.
gcc/testsuite/ChangeLog:
* gcc.target/s390/ifcvt-one-insn-bool.c: Fix loc.
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Joseph pointed out "floating types should have their mode,
not a poorly defined precision value" in the discussion[1],
as he and Richi suggested, the existing macros
{FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE will be replaced with a
hook mode_for_floating_type. To be prepared for that, this
patch is to remove uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE
in m2. Currently they are used for assertion and can be
replaced with TYPE_SIZE check on the corresponding type node,
since we dropped the call to layout_type which would early
return once TYPE_SIZE is set and this assertion ensures it's
safe to drop that call.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651209.html
gcc/m2/ChangeLog:
* gm2-gcc/m2type.cc (build_m2_short_real_node): Adjust assertion with
TYPE_SIZE check.
(build_m2_real_node): Likewise.
(build_m2_long_real_node): Add assertion with TYPE_SIZE check.
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Currrently the size of the array reg_is_wrapped_separately is LAST_SAVED_REGNUM.
But LAST_SAVED_REGNUM could be regno that is being saved. So the size needs
to be `LAST_SAVED_REGNUM + 1` like aarch64_frame->reg_offset is.
Committed as obvious after a bootstrap/test for aarch64-linux-gnu.
gcc/ChangeLog:
PR target/100211
* config/aarch64/aarch64.h (machine_function): Fix the size
of reg_is_wrapped_separately.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
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Another improvement for generating Zbs instructions.
In this case we're looking at stuff like (1 << N) | C where N varies and C is a
single bit constant.
In this pattern the (1 << N) happens in SImode, but is zero extended out to
DImode before the bit manipulation. The fact that we're modifying a DImode
object in the logical op is important as it means we don't have to worry about
whether or not the resulting value is sign extended from SI to DI.
This has run through Ventana's CI system. I'll wait for it to roll through
pre-commit CI before moving forward.
gcc/
* config/riscv/bitmanip.md ((1 << N) | C): New splitter for IOR/XOR
of a single bit an a DImode object.
gcc/testsuite/
* gcc.target/riscv/zbs-zext.c: New test.
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This fixes minor fallout from the IOR->ADD change for rotates that I installed
a little while ago.
Basically the SH backend has a special pattern for setting the T register that
has elements similar to a rotate. With the IOR->ADD change that pattern no
longer matches and we get scan-asm failures.
Fixing isn't a trivial case of just replacing IOR with ADD as the IOR->ADD
change changes some of the simplifications/canonicalizations along the way.
The net is we need a pattern with a slightly different structure. I've
regression tested this on sh3[eb]-linux-gnu and bootstrapped sh4-linux-gnu
(without a regression test).
gcc/
* config/sh/sh.md (neg_zero_extract_4b): New pattern.
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Modern versions of windows (after windows 10 v1511) support VT100 escape
sequences, so translation for them is not necessary. The translation also
mangles embedded warning documentation links.
gcc/ChangeLog:
* pretty-print.cc (mingw_ansi_fputs): Don't translate escape sequences if
the console has ENABLE_VIRTUAL_TERMINAL_PROCESSING.
Signed-off-by: Peter Damianov <peter0x44@disroot.org>
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Windows terminal and mintty both have support for link escape sequences, and so
auto_enable_urls shouldn't be hardcoded to false. For older versions of the
windows console, mingw_ansi_fputs's console API translation logic does mangle
these sequences, but there's nothing useful it could do even if this weren't
the case, so check if the ansi escape sequences are supported at all.
conhost.exe doesn't support link escape sequences, but printing them does not
cause any problems.
gcc/ChangeLog:
* diagnostic-color.cc (auto_enable_urls): Don't hardcode to return
false on mingw hosts.
(auto_enable_urls): Return true if console
supports ansi escape sequences.
Signed-off-by: Peter Damianov <peter0x44@disroot.org>
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Since windows 10 release v1511, the windows console has had support for VT100
escape sequences. We should try to enable this, and utilize it where possible.
gcc/ChangeLog:
* diagnostic-color.cc (should_colorize): Enable processing of VT100
escape sequences on windows consoles
Signed-off-by: Peter Damianov <peter0x44@disroot.org>
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