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In vectorizable_reduction, one check on a reduction operand via index could be
contained by another one check via pointer, so remove the former.
2024-06-16 Feng Xue <fxue@os.amperecomputing.com>
gcc/
* tree-vect-loop.cc (vectorizable_reduction): Remove the duplicated
check.
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Add a utility function to check if a statement is lane-reducing operation,
which could simplify some existing code.
2024-06-16 Feng Xue <fxue@os.amperecomputing.com>
gcc/
* tree-vectorizer.h (lane_reducing_stmt_p): New function.
* tree-vect-slp.cc (vect_analyze_slp): Use new function
lane_reducing_stmt_p to check statement.
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This reverts commit c6a9ab8c920f297c4efd289182aef9fbc73f5906.
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We can unify eqne and other comparison operations.
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_scalar): Ditto
(*pred_eqne<mode>_scalar_narrow): Ditto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test.
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Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify
both Zaamo and Zalrsc, promote them to 'a' in the -march string.
This does not affect testsuite results for users with old versions of binutils.
Testcases that failed due to 'call'/isa string continue to fail after this PATCH
when using an old version of binutils.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add 'a' extension to
riscv_combine_info.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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We don't really support _Complex _BitInt(N), the only place we use
bitint complex types is for the .{ADD,SUB,MUL}_OVERFLOW internal function
results and COMPLEX_EXPR in the usual case should be either not present
yet because the ifns weren't folded and will be lowered, or optimized
into something simpler, because normally the complex bitint should be
used just for extracting the 2 subparts from it.
Still, with disabled optimizations it can occassionally happen that it
appears in the IL and that is why there is support for lowering those,
but it doesn't handle optimizing those too much, so if it uses SSA_NAME,
it relies on them having a backing VAR_DECL during the lowering.
This is normally achieves through the
&& ((is_gimple_assign (use_stmt)
&& (gimple_assign_rhs_code (use_stmt)
!= COMPLEX_EXPR))
|| gimple_code (use_stmt) == GIMPLE_COND)
hunk in gimple_lower_bitint, but as the following testcase shows, there
is one thing I've missed, the load optimization isn't guarded by the
above stuff. So, either we'd need to add support for loads to
lower_complexexpr_stmt, or because they should be really rare, this
patch just disables the load optimization if at least one load use is
a COMPLEX_EXPR (like we do already for PHIs, calls, asm).
2024-06-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/115544
* gimple-lower-bitint.cc (gimple_lower_bitint): Disable optimizing
loads used by COMPLEX_EXPR operands.
* gcc.dg/bitint-107.c: New test.
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This patch enables -march/-mtune=shijidadao, costs and tunings are set
according to the characteristics of the processor.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize shijidadao.
* common/config/i386/i386-common.cc: Add shijidadao.
* common/config/i386/i386-cpuinfo.h (enum processor_subtypes):
Add ZHAOXIN_FAM7H_SHIJIDADAO.
* config.gcc: Add shijidadao.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Let -march=native recognize shijidadao processors.
* config/i386/i386-c.cc (ix86_target_macros_internal): Add shijidadao.
* config/i386/i386-options.cc (m_ZHAOXIN): Add m_SHIJIDADAO.
(m_SHIJIDADAO): New definition.
* config/i386/i386.h (enum processor_type): Add PROCESSOR_SHIJIDADAO.
* config/i386/x86-tune-costs.h (struct processor_costs):
Add shijidadao_cost.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add shijidadao.
(ix86_adjust_cost): Ditto.
* config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Add m_SHIJIDADAO.
(X86_TUNE_USE_GATHER_4PARTS): Ditto.
(X86_TUNE_USE_GATHER_8PARTS): Ditto.
(X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
* doc/extend.texi: Add details about shijidadao.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/mv32.C: Handle new -march
* gcc.target/i386/funcspec-56.inc: Ditto.
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This patch makes avoid inserting a MEMW instruction before a load/store
nstruction with volatile memory reference if there is already a MEMW
immediately before it.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (print_operand):
When outputting MEMW before the instruction, check if the previous
instruction is already that.
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gcc/fortran/ChangeLog:
PR fortran/115390
* trans-decl.cc (gfc_conv_cfi_to_gfc): Move derivation of type sizes
for character via gfc_trans_vla_type_sizes to after character length
has been set.
gcc/testsuite/ChangeLog:
PR fortran/115390
* gfortran.dg/bind_c_char_11.f90: New test.
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This patch adds support for MVE Tail-Predicated Low Overhead Loops by using the
doloop funcitonality added to support predicated vectorized hardware loops.
gcc/ChangeLog:
* config/arm/arm-protos.h (arm_target_bb_ok_for_lob): Change
declaration to pass basic_block.
(arm_attempt_dlstp_transform): New declaration.
* config/arm/arm.cc (TARGET_LOOP_UNROLL_ADJUST): Define targethook.
(TARGET_PREDICT_DOLOOP_P): Likewise.
(arm_target_bb_ok_for_lob): Adapt condition.
(arm_mve_get_vctp_lanes): New function.
(arm_dl_usage_type): New internal enum.
(arm_get_required_vpr_reg): New function.
(arm_get_required_vpr_reg_param): New function.
(arm_get_required_vpr_reg_ret_val): New function.
(arm_mve_get_loop_vctp): New function.
(arm_mve_insn_predicated_by): New function.
(arm_mve_across_lane_insn_p): New function.
(arm_mve_load_store_insn_p): New function.
(arm_mve_impl_pred_on_outputs_p): New function.
(arm_mve_impl_pred_on_inputs_p): New function.
(arm_last_vect_def_insn): New function.
(arm_mve_impl_predicated_p): New function.
(arm_mve_check_reg_origin_is_num_elems): New function.
(arm_mve_dlstp_check_inc_counter): New function.
(arm_mve_dlstp_check_dec_counter): New function.
(arm_mve_loop_valid_for_dlstp): New function.
(arm_predict_doloop_p): New function.
(arm_loop_unroll_adjust): New function.
(arm_emit_mve_unpredicated_insn_to_seq): New function.
(arm_attempt_dlstp_transform): New function.
* config/arm/arm.opt (mdlstp): New option.
* config/arm/iterators.md (dlstp_elemsize, letp_num_lanes,
letp_num_lanes_neg, letp_num_lanes_minus_1): New attributes.
(DLSTP, LETP): New iterators.
* config/arm/mve.md (predicated_doloop_end_internal<letp_num_lanes>,
dlstp<dlstp_elemsize>_insn): New insn patterns.
* config/arm/thumb2.md (doloop_end): Adapt to support tail-predicated
loops.
(doloop_begin): Likewise.
* config/arm/types.md (mve_misc): New mve type to represent
predicated_loop_end insn sequences.
* config/arm/unspecs.md:
(DLSTP8, DLSTP16, DLSTP32, DSLTP64,
LETP8, LETP16, LETP32, LETP64): New unspecs for DLSTP and LETP.
gcc/testsuite/ChangeLog:
* gcc.target/arm/lob.h: Add new helpers.
* gcc.target/arm/lob1.c: Use new helpers.
* gcc.target/arm/lob6.c: Likewise.
* gcc.target/arm/mve/dlstp-compile-asm-1.c: New test.
* gcc.target/arm/mve/dlstp-compile-asm-2.c: New test.
* gcc.target/arm/mve/dlstp-compile-asm-3.c: New test.
* gcc.target/arm/mve/dlstp-int8x16.c: New test.
* gcc.target/arm/mve/dlstp-int8x16-run.c: New test.
* gcc.target/arm/mve/dlstp-int16x8.c: New test.
* gcc.target/arm/mve/dlstp-int16x8-run.c: New test.
* gcc.target/arm/mve/dlstp-int32x4.c: New test.
* gcc.target/arm/mve/dlstp-int32x4-run.c: New test.
* gcc.target/arm/mve/dlstp-int64x2.c: New test.
* gcc.target/arm/mve/dlstp-int64x2-run.c: New test.
* gcc.target/arm/mve/dlstp-invalid-asm.c: New test.
Co-authored-by: Stam Markianos-Wright <stam.markianos-wright@arm.com>
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This patch adds support in the target agnostic doloop pass for the detection of
predicated vectorized hardware loops. Arm is currently the only target that
will make use of this feature.
gcc/ChangeLog:
* df-core.cc (df_bb_regno_only_def_find): New helper function.
* df.h (df_bb_regno_only_def_find): Declare new function.
* loop-doloop.cc (doloop_condition_get): Add support for detecting
predicated vectorized hardware loops.
(doloop_modify): Add support for GTU condition checks.
(doloop_optimize): Update costing computation to support alterations to
desc->niter_expr by the backend.
Co-authored-by: Stam Markianos-Wright <stam.markianos-wright@arm.com>
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After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 10:
#define DEF_VEC_SAT_U_SUB_FMT_10(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = !overflow ? ret : 0; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 9:
#define DEF_VEC_SAT_U_SUB_FMT_9(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = overflow ? 0 : ret; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 8:
#define DEF_VEC_SAT_U_SUB_FMT_8(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = ret & (T)-(!overflow); \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 7:
#define DEF_VEC_SAT_U_SUB_FMT_7(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = ret & (T)(overflow - 1); \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 6:
#define DEF_VEC_SAT_U_SUB_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= y ? 0 : x - y; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 5:
#define DEF_VEC_SAT_U_SUB_FMT_5(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x < y ? 0 : x - y; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 4:
#define DEF_VEC_SAT_U_SUB_FMT_4(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x >= y ? x - y : 0; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 3:
#define DEF_VEC_SAT_U_SUB_FMT_3(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > y ? x - y : 0; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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When dlopen and pthread_create are in libc the variable is
set to "none required", therefore running configure will show
the following errors:
./configure: line 8997: test: too many arguments
./configure: line 8999: test: too many arguments
./configure: line 9003: test: too many arguments
./configure: line 9005: test: =: unary operator expected
gcc/configure also has a similar problem on
gcc_cv_as_mips_explicit_relocs:
./gcc/configure: line 30242: test: =: unary operator expected
ChangeLog:
* configure.ac: Quote variable result of AC_SEARCH_LIBS.
* configure: Regenerate.
gcc/ChangeLog:
* configure.ac: Add missing quotation of variable
gcc_cv_as_mips_explicit_relocs.
* configure: Regenerate.
Signed-off-by: Collin Funk <collin.funk1@gmail.com>
|
|
The following adds a correctness check to the combined store/reduce
vectorization.
* gcc.dg/vect/bb-slp-32.c: Add check for correctness.
|
|
PR fortran/90076
gcc/fortran/ChangeLog:
* trans-decl.cc (gfc_generate_function_code): Set vptr for
results to declared class type.
* trans-expr.cc (gfc_reset_vptr): Allow to provide the typespec
instead of the expression.
* trans.h (gfc_reset_vptr): Same.
gcc/testsuite/ChangeLog:
* gfortran.dg/class_76.f90: Add declared vtab occurrence.
* gfortran.dg/class_78.f90: New test.
|
|
The previous constant synthesis logic had some issues that were non-fatal
but worth considering:
- It didn't work with DFmode literals, because those were cast to SImode
rather SFmode when splitting into two natural-width words by
split_double().
- It didn't work with large literals when TARGET_AUTO_LITPOOLS was enabled,
because those were relaxed MOVI immediates rather references to literal
pool entries,
- It didn't take into account that when literals with the same RTL
representation are pooled multiple times within a function, those entries
are shared (especially important when optimizing for size).
This patch addresses the above issues by making appropriate tweaks to the
constant synthesis logic.
gcc/ChangeLog:
* config/xtensa/xtensa-protos.h (xtensa_constantsynth):
Change the second argument from HOST_WIDE_INT to rtx.
* config/xtensa/xtensa.cc (#include):
Add "context.h" and "pass_manager.h".
(machine_function): Add a new hash_map field "litpool_usage".
(xtensa_constantsynth): Make "src" (the second operand) accept
RTX literal instead of its value, and treat both bare and pooled
SI/SFmode literals equally by bit-exact canonicalization into
CONST_INT RTX internally. And then, make avoid synthesis if
such multiple identical canonicalized literals are found in same
function when optimizing for size. Finally, for literals where
synthesis is not possible or has been avoided, re-emit "move"
RTXes with canonicalized ones to increase the chances of sharing
literal pool entries.
* config/xtensa/xtensa.md (split patterns for constant synthesis):
Change to simply invoke xtensa_constantsynth() as mentioned above,
and add new patterns for when TARGET_AUTO_LITPOOLS is enabled.
|
|
After the middle-end support the form 8 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 8.
Form 8:
#define DEF_VEC_SAT_U_ADD_FMT_8(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > (T)(x + y) ? -1 : (x + y); \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 7 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 7.
Form 7:
#define DEF_VEC_SAT_U_ADD_FMT_7(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) < x ? -1 : (x + y); \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.
Form 6:
#define DEF_VEC_SAT_U_ADD_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= (T)(x + y) ? (x + y) : -1; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 5.
Form 5:
#define DEF_VEC_SAT_U_ADD_FMT_5(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 4.
Form 4:
#define DEF_VEC_SAT_U_ADD_FMT_4(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 3.
Form 3:
#define DEF_VEC_SAT_U_ADD_FMT_3(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_add_overflow (x, y, &ret); \
out[i] = (T)(-overflow) | ret; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 2.
Form 2:
#define DEF_VEC_SAT_U_ADD_FMT_2(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) >= x ? (x + y) : -1; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.
Form 12:
#define DEF_SAT_U_SUB_FMT_12(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_12 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.
Form 11:
#define DEF_SAT_U_SUB_FMT_11(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_11 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
|
|
When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does not have an explicit
machine mode specifying the operand. In this scenario, it will always
assume that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.
Make the assert unconditional and replace it with an internal error for
more descriptive logging
gcc/ChangeLog:
* config/riscv/riscv-v.cc: Move assert out of conditional block
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
|
|
On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
|
|
Applied the wrong patch which didn't have the final testsuite adjustment to
skip -Os on the new test. Fixed thusly.
Pushed to the trunk.
gcc/testsuite
* gcc.target/riscv/zbs-ext-2.c: Do not run for -Os.
|
|
Since these were already aliases just make it clear on that.
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add comment
saying thunderxt81/t83 are aliases of octeontx81/83.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
|
|
Since r7-6575-g71aba51d6460ff, thunderxt88 has been the same as thunderxt88p1 so let's make
them a true alias and remove the odd variant handling and moves it below thunderxt88.
Bootstrapped and tested on aarch64-linux-gnu with no regressions.
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (thunderxt88p1): Make an alias of thunderxt88 and
move below thunderxt88.
* config/aarch64/aarch64-tune.md: Regenerate.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
|
|
Now that nothing in tree-diagnostic-path.cc uses "tree", this patch
renames it to diagnostic-path.cc and moves it from OBJS to
OBJS-libcommon.
No functional change intended.
gcc/ChangeLog:
* Makefile.in (OBJS): Move selftest-diagnostic-path.o,
selftest-logical-location.o, and tree-diagnostic-path.o to...
(OBJS-libcommon): ...here, renaming tree-diagnostic-path.o to
diagnostic-path.o.
* tree-diagnostic-path.cc: Rename to...
* diagnostic-path.cc: ...this. Drop include of "tree.h".
(tree_diagnostic_path_cc_tests): Rename to...
(diagnostic_path_cc_tests): ...this.
* selftest-run-tests.cc (selftest::run_tests): Update for above
renaming.
* selftest.h (tree_diagnostic_path_cc_tests): Rename decl to...
(diagnostic_path_cc_tests): ...this.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
|
|
No functional change intended.
gcc/ChangeLog:
* diagnostic-format-json.cc (diagnostic_output_format_init_json):
Replace clearing of diagnostic_context::m_print_path callback with
setting the path format to DPF_NONE.
* diagnostic-format-sarif.cc
(diagnostic_output_format_init_sarif): Likewise.
* diagnostic.cc (diagnostic_context::show_any_path): Replace call
to diagnostic_context::m_print_path callback with a direct call to
diagnostic_context::print_path.
* diagnostic.h (diagnostic_context::print_path): New decl.
(diagnostic_context::m_print_path): Delete callback.
* tree-diagnostic-path.cc (default_tree_diagnostic_path_printer):
Convert to...
(diagnostic_context::print_path): ...this.
* tree-diagnostic.cc (tree_diagnostics_defaults): Delete
initialization of m_print_path.
* tree-diagnostic.h (default_tree_diagnostic_path_printer): Delete
decl.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
|
|
Eliminate a dependency on "tree" from the code used by
diagnostic_path handling.
No functional change intended.
gcc/ChangeLog:
* Makefile.in (OBJS): Add diagnostic-macro-unwinding.o.
gcc/c-family/ChangeLog:
* c-opts.cc: Replace include of "tree-diagnostic.h" with
"diagnostic-macro-unwinding.h".
gcc/ChangeLog:
* diagnostic-macro-unwinding.cc: New file, with material taken
from tree-diagnostic.cc.
* diagnostic-macro-unwinding.h: New file, with material taken
from tree-diagnostic.h.
* tree-diagnostic-path.cc: Repalce include of "tree-diagnostic.h"
with "diagnostic-macro-unwinding.h".
* tree-diagnostic.cc (struct loc_map_pair): Move to
diagnostic-macro-unwinding.cc.
(maybe_unwind_expanded_macro_loc): Likewise.
(virt_loc_aware_diagnostic_finalizer): Likewise.
* tree-diagnostic.h (virt_loc_aware_diagnostic_finalizer): Move
decl to diagnostic-macro-unwinding.h.
(maybe_unwind_expanded_macro_loc): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
|
|
Now that the path-handling code for json_output_format no longer
needs "tree", and thus can be in OBJS-libcommon we can move it
from tree-diagnostic-path.cc to diagnostic-format-json.cc where it
should have been all along.
No functional change intended.
gcc/ChangeLog:
* diagnostic-format-json.cc: Include "diagnostic-path.h" and
"logical-location.h".
(make_json_for_path): Move tree-diagnostic-path.cc's
default_tree_make_json_for_path here, renaming it and making it
static.
(json_output_format::on_end_diagnostic): Replace call of
m_context's m_make_json_for_path callback with a direct call to
make_json_for_path.
* diagnostic.h (diagnostic_context::m_make_json_for_path): Drop
field.
* tree-diagnostic-path.cc: Drop include of "json.h".
(default_tree_make_json_for_path): Rename to make_json_for_path
and move to diagnostic-format-json.cc.
* tree-diagnostic.cc (tree_diagnostics_defaults): Drop
initialization of m_make_json_for_path.
* tree-diagnostic.h (default_tree_make_json_for): Delete decl.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
|
|
No functional change intended.
gcc/ChangeLog:
* Makefile.in (OBJS): Add selftest-diagnostic-path.o and
selftest-logical-location.o.
* logical-location.h: Include "label-text.h".
(class logical_location): Update leading comment.
* selftest-diagnostic-path.cc: New file, adapted from
simple-diagnostic-path.cc and from material in
tree-diagnostic-path.cc.
* selftest-diagnostic-path.h: New file, adapted from
simple-diagnostic-path.h and from material in
tree-diagnostic-path.cc.
* selftest-logical-location.cc: New file.
* selftest-logical-location.h: New file.
* tree-diagnostic-path.cc: Remove includes of "tree-pretty-print.h",
"langhooks.h", and "simple-diagnostic-path.h". Add include of
"selftest-diagnostic-path.h".
(class test_diagnostic_path): Delete, in favor of new
implementation in selftest-diagnostic-path.{h,cc}, which is
directly derived from diagnostic_path, rather than from
simple_diagnostic_path.
(selftest::test_intraprocedural_path): Eliminate tree usage,
via change to test_diagnostic_path, using strings rather than
function_decls for identifying functions in the test.
(selftest::test_interprocedural_path_1): Likewise.
(selftest::test_interprocedural_path_2): Likewise.
(selftest::test_recursion): Likewise.
(selftest::test_control_flow_1): Likewise.
(selftest::test_control_flow_2): Likewise.
(selftest::test_control_flow_3): Likewise.
(selftest::assert_cfg_edge_path_streq): Likewise.
(selftest::test_control_flow_5): Likewise.
(selftest::test_control_flow_6): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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This patch eliminates the use of "tree" from diagnostic_{event,path} in
favor of const logical_location *.
No functional change intended.
gcc/analyzer/ChangeLog:
* checker-event.h (checker_event::fndecl): Drop "final" and
"override", converting from a vfunc implementation to a plain
accessor.
* checker-path.cc (checker_path::same_function_p): New.
* checker-path.h (checker_path::same_function_p): New decl.
gcc/ChangeLog:
* diagnostic.cc: Include "logical-location.h".
(diagnostic_path::get_first_event_in_a_function): Fix typo in
leading comment. Rewrite to use logical_location rather than
tree. Drop test on stack depth.
(diagnostic_path::interprocedural_p): Rewrite to use
logical_location rather than tree.
(logical_location::function_p): New.
* diagnostic-path.h (diagnostic_event::get_fndecl): Eliminate
vfunc.
(diagnostic_path::same_function_p): New pure virtual func.
* logical-location.h (logical_location::get_name_for_path_output):
New pure virtual func.
* simple-diagnostic-path.cc
(simple_diagnostic_path::same_function_p): New.
(simple_diagnostic_event::simple_diagnostic_event): Initialize
m_logical_loc.
* simple-diagnostic-path.h: Include "tree-logical-location.h".
(simple_diagnostic_event::get_fndecl): Convert from a vfunc
implementation to an accessor.
(simple_diagnostic_event::get_logical_location): Use
m_logical_loc.
(simple_diagnostic_event::m_logical_loc): New field.
(simple_diagnostic_path::same_function_p): New decl.
* tree-diagnostic-path.cc: Move pragma disabling -Wformat-diag to
cover the whole file.
(can_consolidate_events): Add params "path", "ev1_idx", and
"ev2_idx". Rewrite to use diagnostic_path::same_function_p rather
than tree.
(per_thread_summary::per_thread_summary): Add "path" param
(per_thread_summary::m_path): New field.
(event_range::event_range): Update for conversion of m_fndecl to
m_logical_loc.
(event_range::maybe_add_event): Rename param "idx" to
"new_ev_idx". Update call to can_consolidate_events to pass in
"m_path", "m_start_idx", and "new_ev_idx".
(event_range::m_fndecl): Replace with...
(event_range::m_logical_loc): ...this.
(path_summary::get_or_create_events_for_thread_id): Pass "path" to
per_thread_summary ctor.
(per_thread_summary::interprocedural_p): Rewrite to use
diagnostic_path::same_function_p rather than tree.
(print_fndecl): Delete.
(thread_event_printer::print_swimlane_for_event_range): Update for
conversion from tree to logical_location.
(default_tree_diagnostic_path_printer): Likewise.
(default_tree_make_json_for_path): Likewise.
* tree-logical-location.cc: Include "intl.h".
(compiler_logical_location::get_name_for_tree_for_path_output):
New.
(tree_logical_location::get_name_for_path_output): New.
(current_fndecl_logical_location::get_name_for_path_output): New.
* tree-logical-location.h
(compiler_logical_location::get_name_for_tree_for_path_output):
New decl.
(tree_logical_location::get_name_for_path_output): New decl.
(current_fndecl_logical_location::get_name_for_path_output): New
decl.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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As work towards eliminating the dependency on "tree" from
path-printing, move these classes to a new simple-diagnostic-path.h/cc.
No functional change intended.
gcc/analyzer/ChangeLog:
* checker-path.h: Include "simple-diagnostic-path.h".
gcc/ChangeLog:
* Makefile.in (OBJS): Add simple-diagnostic-path.o.
* diagnostic-path.h (class simple_diagnostic_event): Move to
simple-diagnostic-path.h.
(class simple_diagnostic_thread): Likewise.
(class simple_diagnostic_path): Likewise.
* diagnostic.cc (simple_diagnostic_path::simple_diagnostic_path):
Move to simple-diagnostic-path.cc.
(simple_diagnostic_path::num_events): Likewise.
(simple_diagnostic_path::get_event): Likewise.
(simple_diagnostic_path::num_threads): Likewise.
(simple_diagnostic_path::get_thread): Likewise.
(simple_diagnostic_path::add_thread): Likewise.
(simple_diagnostic_path::add_event): Likewise.
(simple_diagnostic_path::add_thread_event): Likewise.
(simple_diagnostic_path::connect_to_next_event): Likewise.
(simple_diagnostic_event::simple_diagnostic_event): Likewise.
(simple_diagnostic_event::~simple_diagnostic_event): Likewise.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::simple_diagnostic_path_cc_tests.
* selftest.h (selftest::simple_diagnostic_path_cc_tests): New
decl.
* simple-diagnostic-path.cc: New file, from the above material.
* simple-diagnostic-path.h: New file, from the above material
from diagnostic-path.h.
* tree-diagnostic-path.cc: Include "simple-diagnostic-path.h".
gcc/testsuite/ChangeLog
* gcc.dg/plugin/diagnostic_plugin_test_paths.c: Include
"simple-diagnostic-path.h".
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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When investigate the vectorization of .SAT_ADD, we notice there
are additional 2 forms, aka form 7 and 8 for .SAT_ADD.
Form 7:
#define DEF_SAT_U_ADD_FMT_7(T) \
T __attribute__((noinline)) \
sat_u_add_##T##_fmt_7 (T x, T y) \
{ \
return x > (T)(x + y) ? -1 : (x + y); \
}
Form 8:
#define DEF_SAT_U_ADD_FMT_8(T) \
T __attribute__((noinline)) \
sat_u_add_##T##_fmt_8 (T x, T y) \
{ \
return x <= (T)(x + y) ? (x + y) : -1; \
}
Thus, add above 2 forms to the match gimple_unsigned_integer_sat_add,
and then the vectorizer can try to recog the pattern like form 7 and
form 8.
The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add form 7 and 8 for the unsigned .SAT_ADD match.
Signed-off-by: Pan Li <pan2.li@intel.com>
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We missed one match pattern for the unsigned scalar .SAT_SUB, aka
form 11.
Form 11:
#define SAT_SUB_U_11(T) \
T sat_sub_u_11_##T (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Thus, add above form 11 to the match pattern gimple_unsigned_integer_sat_sub.
The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add form 11 match pattern for .SAT_SUB.
Signed-off-by: Pan Li <pan2.li@intel.com>
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The condition rejecting "multiple-type" SLP condition reduction lacks
handling EXTRACT_LAST reductions.
PR tree-optimization/115537
* tree-vect-loop.cc (vectorizable_reduction): Also reject
SLP condition reductions of EXTRACT_LAST kind when multiple
statement copies are involved.
* gcc.dg/vect/pr115537.c: New testcase.
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So more work in the ongoing effort to make better use of the Zbs
extension. This time we're trying to exploit knowledge of the shift
count/bit position to allow us to use a bset instruction.
Consider this expression in SImode
(1 << (pos & 0xf)
None of the resulting values will have bit 31 set. So if there's an
explicit zero or sign extension to DI we can drop that explicit
extension and generate a simple bset with x0 as the input value.
Or another example (which I think came from spec at some point and IIRC
was the primary motivation for this patch):
(1 << (7-(pos) % 8))
Before this change they'd generate something like this respectively:
li a5,1
andi a0,a0,15
sllw a0,a5,a0
li a5,7
andn a0,a5,a0
li a5,1
sllw a0,a5,a0
After this change they generate:
andi a0,a0,15 # 9 [c=4 l=4] *anddi3/1
bset a0,x0,a0 # 17 [c=8 l=4] *bsetdi_2
li a5,7 # 27 [c=4 l=4] *movdi_64bit/1
andn a0,a5,a0 # 28 [c=4 l=4] and_notdi3
bset a0,x0,a0 # 19 [c=8 l=4] *bsetdi_2
We achieve this with simple define_splits which target the bsetdi_2
pattern I recently added. Much better than the original implementation
I did a few months back :-) I've got a bclr/binv variant from a few
months back as well, but it needs to be updated to the simpler
implementation found here.
Just ran this through my tester. Will wait for the precommit CI to
render its verdict before moving forward.
gcc/
* config/riscv/bitmanip.md (bset splitters): New patterns for
generating bset when bit position is limited.
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