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2024-04-24i386: Fix behavior for both using AVX10.1-256 in options and function attributeHaochen Jiang2-0/+8
When we are using -mavx10.1-256 in command line and avx10.1-256 in target attribute together, zmm should never be generated. But current GCC will generate zmm since it wrongly enables EVEX512 for non-explicitly set AVX512. This patch will fix that issue. gcc/ChangeLog: * config/i386/i386-options.cc (ix86_valid_target_attribute_tree): Check whether AVX512F is explicitly enabled. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-24.c: New test.
2024-04-24RISC-V: Add xfail test case for highpart overlap of vext.vfPan Li4-1/+224
We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 62685890d88 RISC-V: Support highpart overlap for vext.vf The below test suites are passed for this patch * The rv64gcv fully regression test with isl build. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Adjust asm check cond. * gcc.target/riscv/rvv/base/pr112431-4.c: New test. * gcc.target/riscv/rvv/base/pr112431-5.c: New test. * gcc.target/riscv/rvv/base/pr112431-6.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-24Revert "RISC-V: Support highpart overlap for vext.vf"Pan Li5-234/+10
This reverts commit 62685890d8861b72f812bfe171a20332df08bd49.
2024-04-24Daily bump.GCC Administrator7-1/+196
2024-04-24c++: Fix ICE with xobj parms and maybe incomplete decl-specifiersNathaniel Shead2-2/+12
This fixes a null dereference issue when decl_specifiers.type is not yet provided. gcc/cp/ChangeLog: * parser.cc (cp_parser_parameter_declaration): Check if decl_specifiers.type is null. gcc/testsuite/ChangeLog: * g++.dg/cpp23/explicit-obj-basic7.C: New test. Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com>
2024-04-23i386: Avoid =&r,r,r andn double-word alternative for ia32 [PR114810]Jakub Jelinek2-4/+866
As discussed in the PR, on ia32 with its 8 GPRs, where 1 is always fixed and other 2 often are as well having an alternative which needs 3 double-word registers is just too much for RA. The following patch splits that alternative into two, one with o is used even on ia32, but one with the 3x r is used just for -m64/-mx32. Tried to reduce the testcase further, but it wasn't easily possible. 2024-04-23 Jakub Jelinek <jakub@redhat.com> PR target/114810 * config/i386/i386.md (*andn<dwi>3_doubleword_bmi): Split the =&r,r,ro alternative into =&r,r,r enabled only for x64 and =&r,r,o. * g++.target/i386/pr114810.C: New test.
2024-04-23Regenerate gcc.potJoseph Myers1-3383/+3415
* gcc.pot: Regenerate.
2024-04-23Fortran: check C_SIZEOF on additions from TS29113/F2018 [PR103496]Harald Anlauf1-0/+23
gcc/testsuite/ChangeLog: PR fortran/103496 * gfortran.dg/c_sizeof_8.f90: New test.
2024-04-23c++/modules: deduced return type merging [PR114795]Patrick Palka3-0/+38
When merging an imported function template specialization with an existing one, if the existing one has an undeduced return type and the imported one's is already deduced, we need to propagate the deduced type since once we install the imported definition we won't get a chance to deduce it by normal means. So this patch makes is_matching_decl propagate the deduced return type alongside our propagation of the exception specification. Another option would be to propagate it later when installing the imported definition from read_function_def, but it seems preferable to do it sooner rather than later. PR c++/114795 gcc/cp/ChangeLog: * module.cc (trees_in::is_matching_decl): Propagate deduced function return type. gcc/testsuite/ChangeLog: * g++.dg/modules/auto-4_a.H: New test. * g++.dg/modules/auto-4_b.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
2024-04-23testsuite: Adjust testsuite expectations for diagnostic spelling fixesJakub Jelinek2-2/+2
The nullability-00.m* tests unfortunately check the exact spelling of the diagnostics I've changed earlier today. 2024-04-23 Jakub Jelinek <jakub@redhat.com> * objc.dg/attributes/nullability-00.m: Adjust expected diagnostic spelling: recognised -> recognized. * obj-c++.dg/attributes/nullability-00.mm: Likewise.
2024-04-23Remove repeated information in -ftree-loop-distribute-patterns docJan Hubicka1-2/+0
We have: -ftree-loop-distribute-patterns Perform loop distribution of patterns that can be code generated with calls to a library. This flag is enabled by default at -O2 and higher, and by -fprofile-use and -fauto-profile. This pass distributes the initialization loops and generates a call to memset zero. For example, the loop ... and the initialization loop is transformed into a call to memset zero. This flag is enabled by default at -O3. It is also enabled by -fprofile-use and -fauto-profile. Which mentions optimizatoin flags twice and the repeated mention is out of date, since we enable this option at -O2 as well. gcc/ChangeLog: * doc/invoke.texi (-ftree-loop-distribute-patterns): Remove duplicated sentence about optimization flags implying this.
2024-04-23Further spelling fixes in translatable stringsJakub Jelinek3-5/+5
This addresses the non-Oxford British English vs. US English spelling nits in translatable strings. I see various similar cases in m2 and rust FEs where they don't make it into gcc.pot, guess those would be nice to get fixed too. 2024-04-23 Jakub Jelinek <jakub@redhat.com> * config/darwin.opt (init): Spelling fix: initialiser -> initializer. gcc/c-family/ * c-attribs.cc (handle_objc_nullability_attribute): Spelling fix: recognised -> recognized. gcc/m2/ * lang.opt (fdef=, fmod=): Spelling fix: recognise -> recognize.
2024-04-23Spelling fixes for translatable stringsJakub Jelinek6-6/+6
I've run aspell on gcc.pot (just quickly skimming, so pressing I key hundreds of times and just stopping when I catch something that looks like a misspelling). I plan to commit this tomorrow as obvious unless somebody finds some issues in it, you know, I'm not a native English speaker. Yes, I know favour is valid UK spelling, but we spell the US way I think. I've left some *ise* -> *ize* cases (recognise, initialise), those had too many hits, though in translatable strings just 4, so maybe worth changing too: msgid "recognise the specified suffix as a definition module filename" msgid "recognise the specified suffix as implementation and module filenames" "initialiser for a dylib." msgid "%qE attribute argument %qE is not recognised" 2024-04-23 Jakub Jelinek <jakub@redhat.com> * config/epiphany/epiphany.opt (may-round-for-trunc): Spelling fix: floatig -> floating. * config/riscv/riscv.opt (mcsr-check): Spelling fix: CRS -> CSR. * params.opt (-param=ipa-cp-profile-count-base=): Spelling fix: frequncy -> frequency. gcc/c-family/ * c.opt (Wstrict-flex-arrays): Spelling fix: inproper -> improper. gcc/cp/ * parser.cc (cp_parser_using_declaration): Spelling fix: favour -> favor. gcc/m2/ * lang.opt (fuse-list=): Spelling fix: finalializations -> finalizations.
2024-04-23s390: testsuite: Xfail forwprop-4{0,1}.cStefan Schulze Frielinghaus3-4/+18
The tests fail on s390 since can_vec_perm_const_p fails and therefore the bit insert/ref survive which r14-3381-g27de9aa152141e aims for. Strictly speaking, the tests only fail in case the target supports vectors, i.e., for targets prior z13 or in case of -mesa the emulated vector operations are optimized out. Set to xfail and tracked by PR114802. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/forwprop-40.c: Xfail for s390. * gcc.dg/tree-ssa/forwprop-41.c: Xfail for s390. * lib/target-supports.exp: Add target check s390_mvx.
2024-04-23Fortran: Check that the ICE does not reappear [PR102597]Paul Thomas1-0/+9
2024-04-23 Paul Thomas <pault@gcc.gnu.org> gcc/testsuite/ PR fortran/102597 * gfortran.dg/pr102597.f90: New test.
2024-04-23tree-optimization/114799 - SLP and patternsRichard Biener2-0/+22
The following plugs a hole with computing whether a SLP node has any pattern stmts which is important to know when we want to replace it by a CTOR from external defs. PR tree-optimization/114799 * tree-vect-slp.cc (vect_get_and_check_slp_defs): Properly update ->any_pattern when swapping operands. * gcc.dg/vect/bb-slp-pr114799.c: New testcase.
2024-04-23s390x: Fix vec_xl/vec_xst type aliasing [PR114676]Andreas Krebbel2-7/+28
The requirements of the vec_xl/vec_xst intrinsincs wrt aliasing of the pointer argument are not really documented. As it turns out, users are likely to get it wrong. With this patch we let the pointer argument alias everything in order to make it more robust for users. gcc/ChangeLog: PR target/114676 * config/s390/s390-c.cc (s390_expand_overloaded_builtin): Use a MEM_REF with an addend of type ptr_type_node. gcc/testsuite/ChangeLog: PR target/114676 * gcc.target/s390/zvector/pr114676.c: New test. Suggested-by: Jakub Jelinek <jakub@redhat.com>
2024-04-23c++: Copy over DECL_DISREGARD_INLINE_LIMITS flag to inheriting ctors [PR114784]Jakub Jelinek2-1/+59
The following testcase is rejected with error: inlining failed in call to 'always_inline' '...': call is unlikely and code size would grow errors. The problem is that starting with the r14-2149 change we try to copy most of the attributes from the inherited to inheriting ctor, but don't copy associated flags that decl_attributes sets. Now, the other clone_attrs user, cp/optimize.cc (maybe_clone_body) copies over DECL_COMDAT (clone) = DECL_COMDAT (fn); DECL_WEAK (clone) = DECL_WEAK (fn); if (DECL_ONE_ONLY (fn)) cgraph_node::get_create (clone)->set_comdat_group (cxx_comdat_group (clone)); DECL_USE_TEMPLATE (clone) = DECL_USE_TEMPLATE (fn); DECL_EXTERNAL (clone) = DECL_EXTERNAL (fn); DECL_INTERFACE_KNOWN (clone) = DECL_INTERFACE_KNOWN (fn); DECL_NOT_REALLY_EXTERN (clone) = DECL_NOT_REALLY_EXTERN (fn); DECL_VISIBILITY (clone) = DECL_VISIBILITY (fn); DECL_VISIBILITY_SPECIFIED (clone) = DECL_VISIBILITY_SPECIFIED (fn); DECL_DLLIMPORT_P (clone) = DECL_DLLIMPORT_P (fn); DECL_DISREGARD_INLINE_LIMITS (clone) = DECL_DISREGARD_INLINE_LIMITS (fn); The following patch just copies DECL_DISREGARD_INLINE_LIMITS to fix this exact bug, not really sure which other flags should be copied and which shouldn't. Plus there are tons of other flags, some of which might need to be copied too, some of which might not, perhaps in both places, like: DECL_UNINLINABLE, maybe DECL_PRESERVE_P, TREE_USED, maybe DECL_USER_ALIGN/DECL_ALIGN, maybe DECL_WEAK, maybe DECL_NO_INSTRUMENT_FUNCTION_ENTRY_EXIT, DECL_NO_LIMIT_STACK. TREE_READONLY, DECL_PURE_P, TREE_THIS_VOLATILE (for const, pure and noreturn attributes) probably makes no sense, DECL_IS_RETURNS_TWICE neither (returns_twice ctor?). What about TREE_NOTHROW? DECL_FUNCTION_SPECIFIC_OPTIMIZATION, DECL_FUNCTION_SPECIFIC_TARGET... Anyway, another problem is that if inherited_ctor is a TEMPLATE_DECL, as also can be seen in the using D<T>::D; case in the testcase, then DECL_ATTRIBUTES (fn) = clone_attrs (DECL_ATTRIBUTES (inherited_ctor)); attempts to copy the attributes from the TEMPLATE_DECL which doesn't have them. The following patch copies them from STRIP_TEMPLATE (inherited_ctor) which does. E.g. DECL_DECLARED_CONSTEXPR_P works fine as the macro itself uses STRIP_TEMPLATE too, but not 100% sure about other macros used on inherited_ctor earlier. 2024-04-23 Jakub Jelinek <jakub@redhat.com> PR c++/114784 * method.cc (implicitly_declare_fn): Call clone_attrs on DECL_ATTRIBUTES on STRIP_TEMPLATE (inherited_ctor) rather than inherited_ctor. Also copy DECL_DISREGARD_INLINE_LIMITS flag from it. * g++.dg/cpp0x/inh-ctor39.C: New test.
2024-04-23c++: Check if allocation functions are xobj members [PR114078]Nathaniel Shead2-0/+17
A class allocation member function is implicitly 'static' by [class.free] p3, so cannot have an explicit object parameter. PR c++/114078 gcc/cp/ChangeLog: * decl.cc (grokdeclarator): Check allocation functions for xobj parameters. gcc/testsuite/ChangeLog: * g++.dg/cpp23/explicit-obj-ops-alloc.C: New test. Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com>
2024-04-23LoongArch: Define builtin macros for ISA evolutionsYang Yujie11-95/+398
Detailed description of these definitions can be found at https://github.com/loongson/la-toolchain-conventions, which the LoongArch GCC port aims to conform to. gcc/ChangeLog: * config.gcc: Add loongarch-evolution.o. * config/loongarch/genopts/genstr.sh: Enable generation of loongarch-evolution.[cc,h]. * config/loongarch/t-loongarch: Likewise. * config/loongarch/genopts/gen-evolution.awk: New file. * config/loongarch/genopts/isa-evolution.in: Mark ISA version of introduction for each ISA evolution feature. * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins): Define builtin macros for enabled ISA evolutions and the ISA version. * config/loongarch/loongarch-cpu.cc: Use loongarch-evolution.h. * config/loongarch/loongarch.h: Likewise. * config/loongarch/loongarch-cpucfg-map.h: Delete. * config/loongarch/loongarch-evolution.cc: New file. * config/loongarch/loongarch-evolution.h: New file. * config/loongarch/loongarch-opts.h (ISA_HAS_FRECIPE): Define. (ISA_HAS_DIV32): Likewise. (ISA_HAS_LAM_BH): Likewise. (ISA_HAS_LAMCAS): Likewise. (ISA_HAS_LD_SEQ_SA): Likewise.
2024-04-23LoongArch: Define ISA versionsYang Yujie14-168/+300
These ISA versions are defined as -march= parameters and are recommended for building binaries for distribution. Detailed description of these definitions can be found at https://github.com/loongson/la-toolchain-conventions, which the LoongArch GCC port aims to conform to. gcc/ChangeLog: * config.gcc: Make la64v1.0 the default ISA preset of the lp64d ABI. * config/loongarch/genopts/loongarch-strings: Define la64v1.0, la64v1.1. * config/loongarch/genopts/loongarch.opt.in: Likewise. * config/loongarch/loongarch-c.cc (LARCH_CPP_SET_PROCESSOR): Likewise. (loongarch_cpu_cpp_builtins): Likewise. * config/loongarch/loongarch-cpu.cc (get_native_prid): Likewise. (fill_native_cpu_config): Likewise. * config/loongarch/loongarch-def.cc (array_tune): Likewise. * config/loongarch/loongarch-def.h: Likewise. * config/loongarch/loongarch-driver.cc (driver_set_m_parm): Likewise. (driver_get_normalized_m_opts): Likewise. * config/loongarch/loongarch-opts.cc (default_tune_for_arch): Likewise. (TUNE_FOR_ARCH): Likewise. (arch_str): Likewise. (loongarch_target_option_override): Likewise. * config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Likewise. (TARGET_uARCH_LA664): Likewise. * config/loongarch/loongarch-str.h (STR_CPU_ABI_DEFAULT): Likewise. (STR_ARCH_ABI_DEFAULT): Likewise. (STR_TUNE_GENERIC): Likewise. (STR_ARCH_LA64V1_0): Likewise. (STR_ARCH_LA64V1_1): Likewise. * config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width): Likewise. (loongarch_asm_code_end): Likewise. * config/loongarch/loongarch.opt: Likewise. * doc/invoke.texi: Likewise.
2024-04-23Daily bump.GCC Administrator4-1/+202
2024-04-23RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1Pan Li1-1/+1
After we reverted below 2 commits, the reference to attr need some adjustment as the group_overlap is no longer available. * RISC-V: Robostify the W43, W86, W87 constraint enabled attribute * RISC-V: Rename vconstraint into group_overlap The below tests are passed for this patch. * The rv64gcv fully regression tests. gcc/ChangeLog: * config/riscv/vector-crypto.md: Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-22PR modula2/114811 string set incl ICE bugfixGaius Mulley2-23/+27
This patch corrects gm2-torture.exp to recognize an ICE in the fail case as a negative result. The patch also fixes FoldBinarySet so that the types are only checked once the operands have been resolved. Without this patch gcc/testsuite/gm2/iso/fail/badexpression2.mod would cause an ICE. gcc/m2/ChangeLog: PR modula2/114811 * gm2-compiler/M2GenGCC.mod (FoldBinarySet): Add condition checking to ensure op2 and op3 are fully resolved before type checking is performed. gcc/testsuite/ChangeLog: PR modula2/114811 * lib/gm2-torture.exp: Correct regexp checking for internal compiler error strings in compiler output. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-22PR modula2/114807 badpointer3.mod causes an ICEGaius Mulley13-38/+143
This patch fixes an ICE caused when a constant string is built and attempted to be passed into a procedure with an opaque type. gcc/m2/ChangeLog: PR modula2/114807 * gm2-compiler/M2Check.mod (checkUnbounded): Remove unused local variables. (constCheckMeta): Include check for IsReallyPointer in the failure case. * gm2-compiler/M2Quads.mod (MoveWithMode): Remove CopyConstString. * gm2-compiler/SymbolTable.def (IsHiddenReallyPointer): Export. * gm2-compiler/SymbolTable.mod (SkipHiddenType): Remove. (IsReallyPointer): Include IsHiddenReallyPointer test. gcc/testsuite/ChangeLog: PR modula2/114807 * gm2/pim/fail/badproctype.mod: Change MYSHORTREAL to SHORTREAL. * gm2/pim/fail/badprocbool.mod: New test. * gm2/pim/fail/badproccard.mod: New test. * gm2/pim/fail/badprocint.mod: New test. * gm2/pim/fail/badprocint2.mod: New test. * gm2/pim/pass/goodproccard2.mod: New test. * gm2/pim/pass/goodprocint.mod: New test. * gm2/pim/pass/goodprocint3.mod: New test. * gm2/pim/run/pass/genconststr.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-22testsuite: prune -freport-bug outputMarek Polacek1-0/+1
When the compiler defaults to -freport-bug, a few dg-ice tests fail with: Excess errors: Preprocessed source stored into /tmp/cc6hldZ0.out file, please attach this to your bugreport. We could add -fno-report-bug to those tests. But it seems to me that a better fix would be to prune the "Preprocessed source stored..." message in prune_gcc_output. gcc/testsuite/ChangeLog: * lib/prune.exp (prune_gcc_output): Also prune -freport-bug output. Reviewed-by: Jakub Jelinek <jakub@redhat.com>
2024-04-22Revert "RISC-V: Rename vconstraint into group_overlap"Pan Li3-19/+16
This reverts commit e65aaf8efe1900f7bbf76235a078000bf2ec8b45.
2024-04-22Revert "RISC-V: Robostify the W43, W86, W87 constraint enabled attribute"Pan Li1-17/+2
This reverts commit d3544cea63d0a642b6357a7be55986f5562beaa0.
2024-04-22i386: Fix Sierra Forest auto dispatchHaochen Jiang1-1/+1
gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_alias_table): Let Sierra Forest map to CPU_TYPE enum.
2024-04-22s390x: Do not default to -mvx for -mesaAndreas Krebbel1-1/+1
We currently enable the vector extensions also for -march=z13 -m31 -mesa which is very wrong. gcc/ChangeLog: * config/s390/s390.cc (s390_option_override_internal): Check zarch flag before enabling -mvx.
2024-04-22RISC-V: Add xfail test case for highpart overlap floating-point widen insnPan Li9-0/+839
We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 8614cbb2534 RISC-V: Support highpart overlap for floating-point widen instructions The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-10.c: New test. * gcc.target/riscv/rvv/base/pr112431-11.c: New test. * gcc.target/riscv/rvv/base/pr112431-12.c: New test. * gcc.target/riscv/rvv/base/pr112431-13.c: New test. * gcc.target/riscv/rvv/base/pr112431-14.c: New test. * gcc.target/riscv/rvv/base/pr112431-15.c: New test. * gcc.target/riscv/rvv/base/pr112431-7.c: New test. * gcc.target/riscv/rvv/base/pr112431-8.c: New test. * gcc.target/riscv/rvv/base/pr112431-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-22Revert "RISC-V: Support highpart overlap for floating-point widen instructions"Pan Li10-882/+37
This reverts commit 8614cbb253484e28c3eb20cde4d1067aad56de58.
2024-04-22RISC-V: Add xfail test case for indexed load overlap with SRC EEW < DEST EEWPan Li7-1/+394
Update in v2: * Add change log to pr112431-34.c. Original log: We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 4418d55bcd1 RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST EEW The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-34.c: Remove xfail for vluxei8 check. * gcc.target/riscv/rvv/base/pr112431-28.c: New test. * gcc.target/riscv/rvv/base/pr112431-29.c: New test. * gcc.target/riscv/rvv/base/pr112431-30.c: New test. * gcc.target/riscv/rvv/base/pr112431-31.c: New test. * gcc.target/riscv/rvv/base/pr112431-32.c: New test. * gcc.target/riscv/rvv/base/pr112431-33.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-22Revert "RISC-V: Support highpart overlap for indexed load with SRC EEW < ↵Pan Li7-426/+30
DEST EEW" This reverts commit 4418d55bcd1b7e0ef823981b6a781d7de5c38cce.
2024-04-22s390: testsuite: Remove xfail for vpopct{b,h}Stefan Schulze Frielinghaus1-2/+2
Starting with r14-9316-g7890836de20912 patterns for vpopct{b,h} are also detected. Thus, remove xfails. gcc/testsuite/ChangeLog: * gcc.target/s390/vxe/popcount-1.c: Remove xfail.
2024-04-22RISC-V: Add xfail test case for highest-number regno ternary overlapPan Li2-0/+185
We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 27fde325d64 RISC-V: Support highest-number regno overlap for widen ternary The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-37.c: New test. * gcc.target/riscv/rvv/base/pr112431-38.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-22Revert "RISC-V: Support highest-number regno overlap for widen ternary"Pan Li3-245/+55
This reverts commit 27fde325d64447a3a0d5d550c5976e5f3fb6dc16.
2024-04-22RISC-V: Add xfail test case for widening register overlap of vf4/vf8Pan Li3-0/+170
We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 303195e2a6b RISC-V: Support widening register overlap for vf4/vf8 The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-16.c: New test. * gcc.target/riscv/rvv/base/pr112431-17.c: New test. * gcc.target/riscv/rvv/base/pr112431-18.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-22Revert "RISC-V: Support widening register overlap for vf4/vf8"Pan Li4-190/+18
This reverts commit 303195e2a6b6f0e8f42e0578b61f9f37c6250beb.
2024-04-22RISC-V: Add xfail test case for highpart register overlap of vx/vf widenPan Li6-0/+616
We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. a23415d7572 RISC-V: Support highpart register overlap for widen vx/vf instructions The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-22.c: New test. * gcc.target/riscv/rvv/base/pr112431-23.c: New test. * gcc.target/riscv/rvv/base/pr112431-24.c: New test. * gcc.target/riscv/rvv/base/pr112431-25.c: New test. * gcc.target/riscv/rvv/base/pr112431-26.c: New test. * gcc.target/riscv/rvv/base/pr112431-27.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-22Daily bump.GCC Administrator4-1/+46
2024-04-21Fortran: Detect 'no implicit type' error in right place [PR103471]Paul Thomas4-5/+33
2024-04-21 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/103471 * resolve.cc (resolve_actual_arglist): Catch variables silently set as untyped, resetting the flag so that gfc_resolve_expr can generate the no implicit type error. (gfc_resolve_index_1): Block index expressions of unknown type from being converted to default integer, avoiding the fatal error in trans-decl.cc. * symbol.cc (gfc_set_default_type): Remove '(symbol)' from the 'no IMPLICIT type' error message. * trans-decl.cc (gfc_get_symbol_decl): Change fatal error locus to that of the symbol declaration. (gfc_trans_deferred_vars): Remove two trailing tabs. gcc/testsuite/ PR fortran/103471 * gfortran.dg/pr103471.f90: New test.
2024-04-21Revert "RISC-V: Support highpart register overlap for widen vx/vf instructions"Pan Li7-650/+31
This reverts commit a23415d7572774701d7ec04664390260ab9a3f63.
2024-04-21RISC-V: Add xfail test case for incorrect overlap on v0Pan Li1-0/+101
We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 018ba3ac952 RISC-V: Fix overlap group incorrect overlap on v0 The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-34.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-21Daily bump.GCC Administrator4-1/+91
2024-04-20Revert "RISC-V: Fix overlap group incorrect overlap on v0"Pan Li2-235/+134
This reverts commit 018ba3ac952bed4ae01344c060360f13f7cc084a.
2024-04-20PR modula2/112893 full type checking between proctype and procedure not ↵Gaius Mulley8-16/+141
implemented This patch implements full type checking between proctype and procedures. The change implements an associated proc type built for each procedure. M2Check.mod will request GetProcedureProcType if it encounters a procedure. Before this patch a procedure was associated with the type ADDRESS in the type checking module M2Check. The gm2/pim/pass/proccard.mod have been corrected now this assumption has been removed. gcc/m2/ChangeLog: PR modula2/112893 * gm2-compiler/M2Check.mod (GetProcedureProcType): Import. (getType): Return value using GetProcedureProcType if sym is a procedure. * gm2-compiler/M2Range.mod (FoldTypeExpr): Remove quad if expression is type compatible. * gm2-compiler/SymbolTable.def (GetProcedureProcType): New procedure function. * gm2-compiler/SymbolTable.mod (Procedure): Add ProcedureType. (MakeProcedure): Initialize ProcedureType. (PutParam): Call AddProcedureProcTypeParam. (PutVarParam): Call AddProcedureProcTypeParam. (AddProcedureProcTypeParam): New procedure. (GetProcedureProcType): New procedure function. gcc/testsuite/ChangeLog: PR modula2/112893 * gm2/pim/pass/another.mod: Correct bug exposed by type checker. Swap ProcA and ProcB assignments. * gm2/pim/pass/proccard.mod: Use VAL to convert procedure into a cardinal. * gm2/iso/const/fail/castproctype.mod: New test. * gm2/pim/fail/badproctype.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-20RISC-V: Add xfail test case for wv insn highest overlapPan Li4-1/+315
We reverted below patch for wv insn overlap, add the related wv insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 7e854b58084 RISC-V: Support highest overlap for wv instructions The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: Xfail csr check. * gcc.target/riscv/rvv/base/pr112431-39.c: New test. * gcc.target/riscv/rvv/base/pr112431-40.c: New test. * gcc.target/riscv/rvv/base/pr112431-41.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-20Revert "RISC-V: Support highest overlap for wv instructions"Pan Li4-360/+42
This reverts commit 7e854b58084c131fceca9e8fa9dcc7469972e69d.
2024-04-20RISC-V: Add xfail test case for wv insn register overlapPan Li1-0/+30
We reverted below patch for wv insn overlap, add the related wv insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. b3b2799b872 RISC-V: Support one more overlap for wv instructions gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-42.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
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