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2020-09-30PR target/97150 AArch64: 2nd parameter of unsigned Neon scalar shift ↵Kyrylo Tkachov2-9/+23
intrinsics should be signed In this PR the second argument to the intrinsics should be signed but we use an unsigned one erroneously. The corresponding builtins are already using the correct types so it's just a matter of correcting the signatures in arm_neon.h gcc/ PR target/97150 * config/aarch64/arm_neon.h (vqrshlb_u8): Make second argument signed. (vqrshlh_u16): Likewise. (vqrshls_u32): Likewise. (vqrshld_u64): Likewise. (vqshlb_u8): Likewise. (vqshlh_u16): Likewise. (vqshls_u32): Likewise. (vqshld_u64): Likewise. (vshld_u64): Likewise. gcc/testsuite/ PR target/97150 * gcc.target/aarch64/pr97150.c: New test.
2020-09-30PR target/96313 AArch64: vqmovun* return types should be unsignedKyrylo Tkachov4-13/+21
In this PR we have the wrong return type for some intrinsics. It should be unsigned, but we implement it as signed. Fix this by adjusting the type qualifiers used when creating the builtins and fixing the type in the arm_neon.h intrinsic. With the adjustment in qualifiers we now don't need to cast the result when returning. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ PR target/96313 * config/aarch64/aarch64-simd-builtins.def (sqmovun): Use UNOPUS qualifiers. * config/aarch64/arm_neon.h (vqmovun_s16): Adjust builtin call. Remove unnecessary result cast. (vqmovun_s32): Likewise. (vqmovun_s64): Likewise. (vqmovunh_s16): Likewise. Fix return type. (vqmovuns_s32): Likewise. (vqmovund_s64): Likewise. gcc/testsuite/ PR target/96313 * gcc.target/aarch64/pr96313.c: New test. * gcc.target/aarch64/scalar_intrinsics.c (test_vqmovunh_s16): Adjust return type. (test_vqmovuns_s32): Likewise. (test_vqmovund_s64): Likewise.
2020-09-30aarch64: Tweak movti and movtf patternsRichard Sandiford4-10/+190
movti lacked an way of zeroing an FPR, meaning that we'd do: mov x0, 0 mov x1, 0 fmov d0, x0 fmov v0.d[1], x1 instead of just: movi v0.2d, #0 movtf had the opposite problem for GPRs: we'd generate: movi v0.2d, #0 fmov x0, d0 fmov x1, v0.d[1] instead of just: mov x0, 0 mov x1, 0 Also, there was an unnecessary earlyclobber on the GPR<-GPR movtf alternative (but not the movti one). The splitter handles overlap correctly. The TF splitter used aarch64_reg_or_imm, but the _imm part only accepts integer constants, not floating-point ones. The patch changes it to nonmemory_operand instead. gcc/ * config/aarch64/aarch64.c (aarch64_split_128bit_move_p): Add a function comment. Tighten check for FP moves. * config/aarch64/aarch64.md (*movti_aarch64): Add a w<-Z alternative. (*movtf_aarch64): Handle r<-Y like r<-r. Remove unnecessary earlyclobber. Change splitter predicate from aarch64_reg_or_imm to nonmemory_operand. gcc/testsuite/ * gcc.target/aarch64/movtf_1.c: New test. * gcc.target/aarch64/movti_1.c: Likewise.
2020-09-30arm: Fix ICEs in no-literal-pool.c on MVE [PR97251]Alex Coplan2-4/+4
This patch fixes ICEs when compiling gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool.c with -mfp16-format=ieee -mfloat-abi=hard -march=armv8.1-m.main+mve -mpure-code. The existing conditions in the movsf/movdf expanders (as well as the no_literal_pool patterns) were too restrictive, requiring TARGET_HARD_FLOAT instead of TARGET_VFP_BASE, which caused unrecognised insns when compiling this testcase with integer MVE and -mpure-code. gcc/ChangeLog: PR target/97251 * config/arm/arm.md (movsf): Relax TARGET_HARD_FLOAT to TARGET_VFP_BASE. (movdf): Likewise. * config/arm/vfp.md (no_literal_pool_df_immediate): Likewise. (no_literal_pool_sf_immediate): Likewise.
2020-09-30gcc/configure typo fixAlan Modra2-2/+2
* configure.ac (--with-long-double-format): Typo fix. * configure: Regenerate.
2020-09-30Re: rs6000: Use parameterized names for tablejumpAlan Modra1-14/+16
* config/rs6000/rs6000.md (@tablejump<mode>_normal): Don't use non-existent operands[]. (@tablejump<mode>_nospec): Likewise.
2020-09-30Daily bump.GCC Administrator6-1/+301
2020-09-30rs6000: Use parameterized names for tablejumpSegher Boessenkool1-60/+41
We have too many tablejump patterns. Using parameterized names simplifies the code a bit. 2020-09-29 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.md (tablejump): Simplify. (tablejumpsi): Merge this ... (tablejumpdi): ... and this ... (@tablejump<mode>_normal): ... into this. (tablejumpsi_nospec): Merge this ... (tablejumpdi_nospec): ... and this ... (@tablejump<mode>_nospec): ... into this. (*tablejump<mode>_internal1): Delete, rename to ... (@tablejump<mode>_insn_normal): ... this. (*tablejump<mode>_internal1_nospec): Delete, rename to ... (@tablejump<mode>_insn_nospec): ... this.
2020-09-29Correct and improve -Wnonnull for calls to functions with VLA arguments (PR ↵Martin Sebor3-39/+261
middle-end/97188). Resolves: PR middle-end/97188 - ICE passing a null VLA to a function expecting at least one element gcc/ChangeLog: PR middle-end/97188 * calls.c (maybe_warn_rdwr_sizes): Simplify warning messages. Correct handling of VLA argumments. gcc/testsuite/ChangeLog: PR middle-end/97188 * gcc.dg/Wstringop-overflow-23.c: Adjust text of expected warnings. * gcc.dg/Wnonnull-4.c: New test.
2020-09-29c++: Implement -Wrange-loop-construct [PR94695]Marek Polacek6-5/+318
This new warning can be used to prevent expensive copies inside range-based for-loops, for instance: struct S { char arr[128]; }; void fn () { S arr[5]; for (const auto x : arr) { } } where auto deduces to S and then we copy the big S in every iteration. Using "const auto &x" would not incur such a copy. With this patch the compiler will warn: q.C:4:19: warning: loop variable 'x' creates a copy from type 'const S' [-Wrange-loop-construct] 4 | for (const auto x : arr) { } | ^ q.C:4:19: note: use reference type 'const S&' to prevent copying 4 | for (const auto x : arr) { } | ^ | & As per Clang, this warning is suppressed for trivially copyable types whose size does not exceed 64B. The tricky part of the patch was how to figure out if using a reference would have prevented a copy. To that point, I'm using the new function called ref_conv_binds_directly_p. This warning is enabled by -Wall. Further warnings of similar nature should follow soon. gcc/c-family/ChangeLog: PR c++/94695 * c.opt (Wrange-loop-construct): New option. gcc/cp/ChangeLog: PR c++/94695 * call.c (ref_conv_binds_directly_p): New function. * cp-tree.h (ref_conv_binds_directly_p): Declare. * parser.c (warn_for_range_copy): New function. (cp_convert_range_for): Call it. gcc/ChangeLog: PR c++/94695 * doc/invoke.texi: Document -Wrange-loop-construct. gcc/testsuite/ChangeLog: PR c++/94695 * g++.dg/warn/Wrange-loop-construct.C: New test.
2020-09-29testsuite: Remove unnecessary DWARF2 xfails on AIXDavid Edelsohn33-52/+52
A number of DWARF2 testsuite xfails no longer trigger on AIX. This patch removes the unnecessary XFAIL decorations that cause extraneous notices that clutter the testsuite output. gcc/testsuite/ChangeLog: 2020-09-29 David Edelsohn <dje.gcc@gmail.com> * g++.dg/debug/dwarf2/align-1.C: Remove AIX XFAIL. * g++.dg/debug/dwarf2/align-2.C: Same. * g++.dg/debug/dwarf2/align-3.C: Same. * g++.dg/debug/dwarf2/align-4.C: Same. * g++.dg/debug/dwarf2/align-5.C: Same. * g++.dg/debug/dwarf2/align-6.C: Same. * g++.dg/debug/dwarf2/defaulted-member-function-1.C: Same. * g++.dg/debug/dwarf2/defaulted-member-function-2.C: Same. * g++.dg/debug/dwarf2/defaulted-member-function-3.C: Same. * g++.dg/debug/dwarf2/inline-var-1.C: Same. * g++.dg/debug/dwarf2/inline-var-2.C: Same. * g++.dg/debug/dwarf2/inline-var-3.C: Same. * g++.dg/debug/dwarf2/noreturn-function.C: Same. * g++.dg/debug/dwarf2/ptrdmem-1.C: Same. * g++.dg/debug/dwarf2/ref-2.C: Same. * g++.dg/debug/dwarf2/ref-3.C: Same. * g++.dg/debug/dwarf2/ref-4.C: Same. * g++.dg/debug/dwarf2/refqual-1.C: Same. * g++.dg/debug/dwarf2/refqual-2.C: Same. * gcc.dg/debug/dwarf2/align-1.c: Same. * gcc.dg/debug/dwarf2/align-2.c: Same. * gcc.dg/debug/dwarf2/align-3.c: Same. * gcc.dg/debug/dwarf2/align-4.c: Same. * gcc.dg/debug/dwarf2/align-5.c: Same. * gcc.dg/debug/dwarf2/align-6.c: Same. * gcc.dg/debug/dwarf2/align-as-1.c: Same. * gcc.dg/debug/dwarf2/dwarf2-macro.c: Same. * gcc.dg/debug/dwarf2/dwarf2-macro2.c: Same. * gcc.dg/debug/dwarf2/lang-c89.c: Same. * gcc.dg/debug/dwarf2/noreturn-function-attribute.c: Same. * gcc.dg/debug/dwarf2/noreturn-function-keyword.c: Same. * gcc.dg/debug/dwarf2/pr71855.c: Same. * gcc.dg/debug/dwarf2/inline5.c: Add XFAIL on AIX.
2020-09-29analyzer: fix signal-handler registration location [PR95188]David Malcolm2-6/+39
PR analyzer/95188 reports that diagnostics from -Wanalyzer-unsafe-call-within-signal-handler use the wrong source location when reporting the signal-handler registration event in the diagnostic_path. The diagnostics erroneously use the location of the first stmt in the basic block containing the call to "signal", rather than that of the call itself. Fixed thusly. gcc/analyzer/ChangeLog: PR analyzer/95188 * engine.cc (stmt_requires_new_enode_p): Split enodes before "signal" calls. gcc/testsuite/ChangeLog: PR analyzer/95188 * gcc.dg/analyzer/signal-registration-loc.c: New test.
2020-09-29Fix GCC 10+ build failure with zstd version 1.2.0 or older.Jim Wilson2-4/+14
Extends the configure check for zstd.h to also verify the zstd version, since gcc requires features that only exist in 1.3.0 and newer. Without this patch we get a build error for lto-compress.c when using an old zstd version. gcc/ PR bootstrap/97183 * configure.ac (gcc_cv_header_zstd_h): Check ZSTD_VERISON_NUMBER. * configure: Regenerated.
2020-09-29arm: add support for Cortex-X1Przemyslaw Wirkus4-5/+19
This adds support for the Arm Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gcc/ChangeLog: * config/arm/arm-cpus.in: Add Cortex-X1 core. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * doc/invoke.texi: Update docs.
2020-09-29aarch64: add support for Cortex-X1Przemyslaw Wirkus3-2/+3
This adds support for the Arm Cortex-X1 CPU in AArch64 GCC. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gcc/ChangeLog: * config/aarch64/aarch64-cores.def: Add Cortex-X1 Arm core. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi: Add -mtune=cortex-x1 docs.
2020-09-29analyzer: silence -Wsign-compare warningsDavid Malcolm2-4/+4
gcc/analyzer/ChangeLog: * constraint-manager.cc (constraint_manager::add_constraint_internal): Whitespace fixes. Silence -Wsign-compare warning. * engine.cc (maybe_process_run_of_before_supernode_enodes): Silence -Wsign-compare warning.
2020-09-29c++: Hiddenness is a property of the symbol tableNathan Sidwell5-136/+213
This patch moves the handling of decl-hiddenness entirely into the name lookup machinery, where it belongs. We need a few new flags, because pressing the existing OVL_HIDDEN_P into play for non-function decls doesn't work well. For a local binding we only need one marker, as there cannot be both a hidden implicit typedef and a hidden function. That's not true for namespace-scope, where they could both be hidden. The name-lookup machinery maintains the existing decl_hidden and co flags, and asserts have been sprinkled around to make sure they are consistent. The next series of patches will remove those old markers. (we'll need to keep one, as there are some special restrictions on redeclaring friend functions with in-class definitions or default args.) gcc/cp/ * cp-tree.h (ovl_insert): Change final parm to hidden-or-using indicator. * name-lookup.h (HIDDEN_TYPE_BINDING_P): New. (struct cxx_binding): Add type_is_hidden flag. * tree.c (ovl_insert): Change using_p parm to using_or_hidden, adjust. (ovl_skip_hidden): Assert we never see a naked hidden decl. * decl.c (xref_tag_1): Delete unhiding friend from here (moved to lookup_elaborated_type_1). * name-lookup.c (STAT_TYPE_HIDDEN_P, STAT_DECL_HIDDEN_P): New. (name_lookup::search_namespace_only): Check new hidden markers. (cxx_binding_make): Clear HIDDEN_TYPE_BINDING_P. (update_binding): Update new hidden markers. (lookup_name_1): Check HIDDEN_TYPE_BINDING_P and simplify friend ignoring. (lookup_elaborated_type_1): Use new hidden markers. Reveal the decl here.
2020-09-29x86: Replace <enqcmdntrin.h> with <enqcmdintrin.h>H.J. Lu1-4/+4
Fix 2 typos in config/i386/enqcmdintrin.h by replacing <enqcmdntrin.h> with <enqcmdintrin.h>: [hjl@gnu-cfl-2 x86-gcc]$ echo "#include <enqcmdintrin.h>" | gcc -S -o /dev/null -x c - In file included from <stdin>:1: /usr/lib/gcc/x86_64-redhat-linux/10/include/enqcmdintrin.h:25:3: error: #error "Never use <enqcmdntrin.h> directly; include <x86intrin.h> instead." 25 | # error "Never use <enqcmdntrin.h> directly; include <x86intrin.h> instead." | ^~~~~ [hjl@gnu-cfl-2 x86-gcc]$ and _ENQCMDINTRIN_H_INCLUDED with _ENQCMDINTRIN_H_INCLUDED. gcc/ PR target/97247 * config/i386/enqcmdintrin.h: Replace <enqcmdntrin.h> with <enqcmdintrin.h>. Replace _ENQCMDNTRIN_H_INCLUDED with _ENQCMDINTRIN_H_INCLUDED.
2020-09-29c++: Name lookup simplificationsNathan Sidwell2-77/+98
Here are a few cleanups, prior to landing the hidden decl changes. 1) Clear cxx_binding flags in the allocator, not at each user of the allocator. 2) Refactor update_binding. The logic was getting too convoluted. 3) Set friendliness and anticipatedness before pushing a template decl (not after). gcc/cp/ * name-lookup.c (create_local_binding): Do not clear INHERITED_VALUE_BINDING_P here. (name_lookup::process_binding): Move done hidden-decl triage to ... (name_lookup::search_namespace_only): ... here, its only caller. (cxx_binding_make): Clear flags here. (push_binding): Not here. (pop_local_binding): RAII. (update_binding): Refactor. (do_pushdecl): Assert we're never revealing a local binding. (do_pushdecl_with_scope): Directly call do_pushdecl. (get_class_binding): Do not clear LOCAL_BINDING_P here. * pt.c (push_template_decl): Set friend & anticipated before pushing.
2020-09-29testsuite: Prevent spellcheck-inttypes failures on AIX.David Edelsohn2-1/+4
AIX stdio.h implicitly includes sys/types.h, which implicitly includes inttypes.h. With a recent AIX header fixincludes change to unilaterally define STDC Macros, the GCC testsuite uses of inttypes now fails. This patch explicitly defines the _STD_TYPES_T macro when the test is run on AIX so that the inttypes.h header behaves as the testcase requires. gcc/testsuite/ChangeLog: 2020-09-29 David Edelsohn <dje.gcc@gmail.com> * g++.dg/spellcheck-inttypes.C: Define _STD_TYPES_T on AIX. * gcc.dg/spellcheck-inttypes.c: Same.
2020-09-29c++: Identifier type value should not update bindingNathan Sidwell1-28/+22
This simplification removes some unneeded behaviour in set_identifier_type_value_with_scope, which was updating the namespace binding. And causing update_binding to have to deal with meeting two implicit typedefs. But the typedef is already there, and there's no other way to have two such typedef's collide (we'll already have dealt with that in lookup_elaborated_type). So, let's kill this crufty code. gcc/cp/ * name-lookup.c (update_binding): We never meet two implicit typedefs. (do_pushdecl): Adjust set_identifier_type_value_with_scope calls. (set_identifier_type_value_with_scope): Do not update binding in the namespace-case. Assert it is already there.
2020-09-29tree-optimization/97241 - fix ICE in reduction vectorizationRichard Biener2-12/+24
The following moves an ad-hoc attempt at discovering the SLP node for a stmt to the place where we can find it in lock-step when we find the stmt itself. 2020-09-29 Richard Biener <rguenther@suse.de> PR tree-optimization/97241 * tree-vect-loop.c (vectorizable_reduction): Move finding the SLP node for the reduction stmt to a better place. * gcc.dg/vect/pr97241.c: New testcase.
2020-09-29move permute optimization to optimize-slpRichard Biener2-10/+10
This moves optimizing permutes of SLP reductions to vect_optimize_slp, eliding the global slp_loads array. 2020-09-29 Richard Biener <rguenther@suse.de> * tree-vect-slp.c (vect_analyze_slp): Move SLP reduction re-arrangement and SLP graph load gathering... (vect_optimize_slp): ... here. * tree-vectorizer.h (vec_info::slp_loads): Remove.
2020-09-29Add missing FSF copyright notes for x86 intrinsic headers.Hongyu Wang8-0/+184
gcc/ChangeLog: PR target/97231 * config/i386/amxbf16intrin.h: Add FSF copyright notes. * config/i386/amxint8intrin.h: Ditto. * config/i386/amxtileintrin.h: Ditto. * config/i386/avx512vp2intersectintrin.h: Ditto. * config/i386/avx512vp2intersectvlintrin.h: Ditto. * config/i386/pconfigintrin.h: Ditto. * config/i386/tsxldtrkintrin.h: Ditto. * config/i386/wbnoinvdintrin.h: Ditto.
2020-09-29tree-optimization/97238 - fix typo causing ICERichard Biener2-1/+13
This fixes a typo causing a NULL dereference. 2020-09-29 Richard Biener <rguenther@suse.de> PR tree-optimization/97238 * tree-ssa-reassoc.c (ovce_extract_ops): Fix typo. * gcc.dg/pr97238.c: New testcase.
2020-09-29arm: Add new vector mode macrosRichard Sandiford5-97/+61
The AArch32 port now has three vector extensions: iwMMXt, Neon and MVE. We already have some named expanders that are shared by all three, and soon we'll need more. One way of handling this would be to use define_mode_iterators that specify the condition for each mode. For example, (V16QI "TARGET_NEON || TARGET_HAVE_MVE") (V8QI "TARGET_NEON || TARGET_REALLY_IWMXXT") ... (V2SF "TARGET_NEON && flag_unsafe_math_optimizations") etc. However, we'll need several mode iterators, and it would be repetitive to specify the mode condition every time. This patch therefore introduces per-mode macros that say whether we can perform general arithmetic on the mode. Initially there are two sets of macros: ARM_HAVE_NEON_<MODE>_ARITH true if Neon can handle general arithmetic on <MODE> ARM_HAVE_<MODE>_ARITH true if any vector extension can handle general arithmetic on <MODE> The macro definitions themselves are undeniably ugly, but hopefully they're justified by the simplifications they allow. The patch converts the addition patterns to use this scheme. Previously there were three copies of the V8HF and V4HF addition patterns for Neon: (1) *add<VDQ:mode>3_neon, which provided plus:VnHF even without TARGET_NEON_FP16INST. This was probably harmless since all the named patterns had an appropriate guard, but it is possible that something could have tried to generate the plus directly, such as by using a REG_EQUAL note to generate a new pattern. (2) addv8hf3_neon and addv4hf3, which had the correct TARGET_NEON_FP16INST target condition, but unnecessarily required flag_unsafe_math_optimizations. Unlike VnSF operations, VnHF operations do not force flush to zero. (3) add<VH:mode>3_fp16, which provided plus:VnHF with the correct conditions (TARGET_NEON_FP16INST, with no flag_unsafe_math_optimizations test). The patch in essence renames add<VH:mode>3_fp16 to *add<VH:mode>3_neon (part of *add<VDQ:mode>3_neon) and removes the other two patterns. gcc/ * config/arm/arm.h (ARM_HAVE_NEON_V8QI_ARITH, ARM_HAVE_NEON_V4HI_ARITH) (ARM_HAVE_NEON_V2SI_ARITH, ARM_HAVE_NEON_V16QI_ARITH): New macros. (ARM_HAVE_NEON_V8HI_ARITH, ARM_HAVE_NEON_V4SI_ARITH): Likewise. (ARM_HAVE_NEON_V2DI_ARITH, ARM_HAVE_NEON_V4HF_ARITH): Likewise. (ARM_HAVE_NEON_V8HF_ARITH, ARM_HAVE_NEON_V2SF_ARITH): Likewise. (ARM_HAVE_NEON_V4SF_ARITH, ARM_HAVE_V8QI_ARITH, ARM_HAVE_V4HI_ARITH) (ARM_HAVE_V2SI_ARITH, ARM_HAVE_V16QI_ARITH, ARM_HAVE_V8HI_ARITH) (ARM_HAVE_V4SI_ARITH, ARM_HAVE_V2DI_ARITH, ARM_HAVE_V4HF_ARITH) (ARM_HAVE_V2SF_ARITH, ARM_HAVE_V8HF_ARITH, ARM_HAVE_V4SF_ARITH): Likewise. * config/arm/iterators.md (VNIM, VNINOTM): Delete. * config/arm/vec-common.md (add<VNIM:mode>3, addv8hf3) (add<VNINOTM:mode>3): Replace with... (add<VDQ:mode>3): ...this new expander. * config/arm/neon.md (*add<VDQ:mode>3_neon): Use the new ARM_HAVE_NEON_<MODE>_ARITH macros as the C condition. (addv8hf3_neon, addv4hf3, add<VFH:mode>3_fp16): Delete in favor of the above. (neon_vadd<VH:mode>): Use gen_add<mode>3 instead of gen_add<mode>3_fp16. gcc/testsuite/ * gcc.target/arm/armv8_2-fp16-arith-2.c: Expect FP16 vectorization even without -ffast-math.
2020-09-29RISC-V: Define __riscv_cmodel_medany for PIC mode.Kito Cheng3-9/+12
- According the conclusion in RISC-V C API document, we decide to deprecat the __riscv_cmodel_pic marco - __riscv_cmodel_pic is deprecated and will removed in next GCC release. [1] https://github.com/riscv/riscv-c-api-doc/pull/11 gcc/ChangeLog: * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define __riscv_cmodel_medany when PIC mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-3.c: Update testcase. * gcc.target/riscv/predef-6.c: Ditto.
2020-09-29aarch64: Fix ordering of aarch64-cores.defAlex Coplan2-4/+4
This patch moves the entry for Neoverse N2 (an Armv8.5-A CPU) after Saphira (an Armv8.4-A CPU) to preserve the overall ordering in the file. Committing as obvious. gcc/ChangeLog: * config/aarch64/aarch64-cores.def: Move neoverse-n2 after saphira. * config/aarch64/aarch64-tune.md: Regenerate.
2020-09-29switch conversion: make a rapid speed upMartin Liska3-13/+79
gcc/ChangeLog: PR tree-optimization/96979 * tree-switch-conversion.c (jump_table_cluster::can_be_handled): Make a fast bail out. (bit_test_cluster::can_be_handled): Likewise here. * tree-switch-conversion.h (get_range): Use wi::to_wide instead of a folding. gcc/testsuite/ChangeLog: PR tree-optimization/96979 * g++.dg/tree-ssa/pr96979.C: New test.
2020-09-29Revert "switch lowering: limit number of cluster attemps"Martin Liska4-75/+0
This reverts commit c6df6039e9180c580945266302ec14047d358364.
2020-09-28testsuite: Skip symver1 on AIX.David Edelsohn1-1/+1
symver1.c only is valid on ELF targets. Add AIX to the skip list. gcc/testsuite/ChangeLog 2020-09-28 David Edelsohn <dje.gcc@gmail.com> * gcc.dg/ipa/symver1.c: Skip on AIX.
2020-09-29Daily bump.GCC Administrator6-1/+177
2020-09-28analyzer: add some missing FINAL OVERRIDEsDavid Malcolm1-4/+16
Spotted by cppcheck. gcc/analyzer/ChangeLog: * region-model.h (binop_svalue::dyn_cast_binop_svalue): Remove redundant "virtual". Add FINAL OVERRIDE. (widening_svalue::dyn_cast_widening_svalue): Add FINAL OVERRIDE. (compound_svalue::dyn_cast_compound_svalue): Likewise. (conjured_svalue::dyn_cast_conjured_svalue): Likewise.
2020-09-28analyzer: remove unused fieldDavid Malcolm1-1/+0
I added this field (and the struct itself) in the rewrite of region and value-handling (808f4dfeb3a95f50f15e71148e5c1067f90a126d), but the field was never used. Found by cppcheck. gcc/analyzer/ChangeLog: * diagnostic-manager.cc (null_assignment_sm_context::m_visitor): Remove unused field.
2020-09-28analyzer: fix ICE on non-pointer longjmp [PR97233]David Malcolm3-1/+13
gcc/analyzer/ChangeLog: PR analyzer/97233 * analyzer.cc (is_longjmp_call_p): Require the initial argument to be a pointer. * engine.cc (exploded_node::on_longjmp): Likewise. gcc/testsuite/ChangeLog: PR analyzer/97233 * gcc.dg/analyzer/pr97233.c: New test.
2020-09-28analyzer: fix sm_state_map::printDavid Malcolm1-1/+1
In 10fc42a8396072912e9d9d940fba25950b3fdfc5 I converted state_t from unsigned to const state *, but missed this comparison against 0. gcc/analyzer/ChangeLog: * program-state.cc (sm_state_map::print): Update check for m_global_state being the start state.
2020-09-28net: add hurd build tagIan Lance Taylor1-1/+1
Patch from Svante Signell. Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/257857
2020-09-29irange_allocator classAldy Hernandez1-0/+65
This is the irange storage class. It is used to allocate the minimum amount of storage needed for a given irange. Storage is automatically freed at destruction of the storage class. It is meant for long term storage, as opposed to int_range_max which is meant for intermediate temporary results on the stack. The general gist is: irange_allocator alloc; // Allocate an irange of 5 sub-ranges. irange *p = alloc.allocate (5); // Allocate an irange of 3 sub-ranges. irange *q = alloc.allocate (3); // Allocate an irange with as many sub-ranges as are currently // used in "some_other_range". irange *r = alloc.allocate (some_other_range); gcc/ChangeLog: * value-range.h (class irange): Add irange_allocator friend. (class irange_allocator): New.
2020-09-28OpenMP: Handle cpp_implicit_alias in declare-target discovery (PR96390)Tobias Burnus1-6/+38
gcc/ChangeLog: PR middle-end/96390 * omp-offload.c (omp_discover_declare_target_tgt_fn_r): Handle alias nodes. libgomp/ChangeLog: PR middle-end/96390 * testsuite/libgomp.c++/pr96390.C: New test. * testsuite/libgomp.c-c++-common/pr96390.c: New test.
2020-09-28rs6000: Add tests for _mm_insert_epi{8,32,64}Paul A. Clarke3-0/+250
Copied from gcc.target/i386. 2020-09-23 Paul A. Clarke <pc@us.ibm.com> gcc/testsuite/ChangeLog: * gcc.target/powerpc/sse4_1-pinsrb.c: New test. * gcc.target/powerpc/sse4_1-pinsrd.c: New test. * gcc.target/powerpc/sse4_1-pinsrq.c: New test.
2020-09-28rs6000: Support _mm_insert_epi{8,32,64}Paul A. Clarke1-0/+30
Add compatibility implementations for SSE4.1 intrinsics _mm_insert_epi8, _mm_insert_epi32, _mm_insert_epi64. 2020-09-23 Paul A. Clarke <pc@us.ibm.com> gcc/ * config/rs6000/smmintrin.h (_mm_insert_epi8): New. (_mm_insert_epi32): New. (_mm_insert_epi64): New.
2020-09-28Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16.liuhongt39-13/+1032
AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud AMX-BF16:tdpbf16ps gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET, OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET, OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET, OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET): New marcos. (ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16. * common/config/i386/cpuinfo.h (XSTATE_TILECFG, XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro. (get_available_features): Enable AMX features only if their states are suoorited by OSXSAVE. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-tile, amx-int8, amx-bf16. * config.gcc: Add amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h to extra headers. * config/i386/amxbf16intrin.h: New file. * config/i386/amxint8intrin.h: Ditto. * config/i386/amxtileintrin.h: Ditto. * config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8): New macro. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AMX_TILE__, __AMX_INT8__, AMX_BF16__. * config/i386/i386-options.c (ix86_target_string): Add -mamx-tile, -mamx-int8, -mamx-bf16. (ix86_option_override_internal): Handle AMX-TILE, AMX-INT8, AMX-BF16. * config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P, TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P, PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros. * config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16. * config/i386/immintrin.h: Include amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h. * doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16. * doc/extend.texi: Document amx-tile, amx-int8, amx-bf16. * doc/sourcebuild.texi ((Effective-Target Keywords, Other hardware attributes): Document amx_int8, amx_tile, amx_bf16. gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_amx_tile, check_effective_target_amx_int8, check_effective_target_amx_bf16): New proc. * g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: New header file. * gcc.target/i386/amxbf16-asmatt-1.c: New test. * gcc.target/i386/amxint8-asmatt-1.c: New test. * gcc.target/i386/amxtile-asmatt-1.c: Ditto. * gcc.target/i386/amxbf16-asmintel-1.c: Ditto. * gcc.target/i386/amxint8-asmintel-1.c: Ditto. * gcc.target/i386/amxtile-asmintel-1.c: Ditto. * gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto. * gcc.target/i386/amxtile-2.c: Ditto.
2020-09-28aarch64: Do not alter force_reg returned rtx expanding pauth builtinsAndrea Corallo1-11/+2
2020-09-21 Andrea Corallo <andrea.corallo@arm.com> * config/aarch64/aarch64-builtins.c (aarch64_general_expand_builtin): Do not alter value on a force_reg returned rtx.
2020-09-28Revert "Fortran : ICE in build_field PR95614"Mark Eggleston6-26/+8
This reverts commit e5a76af3a2f3324efc60b4b2778ffb29d5c377bc.
2020-09-28Add missing end location informationEric Botcazou1-6/+5
In some cases we would fail to put the end location information on the outermost BIND_EXPR of a function, which is problematic when there is a dynamic stack allocation. gcc/ada/ChangeLog: * gcc-interface/trans.c (Subprogram_Body_to_gnu): Set the end locus of body and declaration earlier.
2020-09-28Fix bogus alignment warning on address clauseEric Botcazou3-8/+43
The compiler gives a bogus alignment warning on an address clause and a discriminated record type with variable size. gcc/ada/ChangeLog: * gcc-interface/decl.c (maybe_saturate_size): Add ALIGN parameter and round down the result to ALIGN. (gnat_to_gnu_entity): Adjust calls to maybe_saturate_size. gcc/testsuite/ChangeLog: * gnat.dg/addr16.adb: New test. * gnat.dg/addr16_pkg.ads: New helper.
2020-09-28Revert recent changes to lower_try_finally_dup_blockEric Botcazou1-10/+2
This reverts the recent changes made to lower_try_finally_dup_block and aimed at tweaking the souce location info for __builtin_stack_restore. gcc/ChangeLog: * tree-eh.c (lower_try_finally_dup_block): Revert latest change.
2020-09-28Daily bump.GCC Administrator4-1/+54
2020-09-27Fix handling of stores in modref_summary::useful_pJan Hubicka1-1/+1
* ipa-modref.c (modref_summary::useful_p): Fix testing of stores.
2020-09-27optabs: Don't reuse target for multi-word expansions if it overlaps ↵Jakub Jelinek2-1/+34
operand(s) [PR97073] The following testcase is miscompiled on i686-linux, because we try to expand a double-word bitwise logic operation with op0 being a (mem:DI u) and target (mem:DI u+4), i.e. partial overlap, and thus end up with: movl 4(%esp), %eax andl u, %eax movl %eax, u+4 ! movl u+4, %eax optimized out andl 8(%esp), %eax movl %eax, u+8 rather than with the desired: movl 4(%esp), %edx movl 8(%esp), %eax andl u, %edx andl u+4, %eax movl %eax, u+8 movl %edx, u+4 because the store of the first word to target overwrites the second word of the operand. expand_binop for this (and several similar places) already check for target == op0 or target == op1, this patch just adds reg_overlap_mentioned_p calls next to it. Pedantically, at least for some of these it might be sufficient to force a different target if there is overlap but target is not rtx_equal_p to the operand (e.g. in this bitwise logical case, but e.g. not in the shift cases where there is reordering), though that would go against the preexisting target == op? checks and the rationale that REG_EQUAL notes in that case isn't correct. 2020-09-27 Jakub Jelinek <jakub@redhat.com> PR middle-end/97073 * optabs.c (expand_binop, expand_absneg_bit, expand_unop, expand_copysign_bit): Check reg_overlap_mentioned_p between target and operand(s) and if it returns true, force a pseudo as target. * gcc.c-torture/execute/pr97073.c: New test.
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