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2020-11-04Daily bump.GCC Administrator6-1/+618
2020-11-04Add testcase for pr97695Jan Hubicka1-0/+20
* gcc.c-torture/execute/pr97695.c: New test.
2020-11-04Fix copying of clone_info while reshaping clone tree.Jan Hubicka6-28/+21
2020-11-04 Jan Hubicka <hubicka@ucw.cz> PR ipa/97695 * cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): Fix ICE with in dumping code. (cgraph_node::remove): Save clone info before releasing it and pass it to unregister. * cgraph.h (symtab_node::unregister): Add clone_info parameter. (cgraph_clone::unregister): Likewise. * cgraphclones.c (cgraph_node::find_replacement): Copy clone info * symtab-clones.cc (clone_infos_t::duplicate): Remove. (clone_info::get_create): Simplify. * symtab.c (symtab_node::unregister): Pass around clone info. * varpool.c (varpool_node::remove): Update.
2020-11-03c++: Not all character types are byte-access types.Jason Merrill2-3/+211
The patch for 94923 that introduced is_byte_access_type wrongly changed build_cplus_array_type to treat even arrays of char16_t as typeless storage, which is wrong; only arrays of char and unsigned char have the special alias semantics in C++. G++ used to treat signed char the same way, as C does, but C++ has always omitted it. gcc/cp/ChangeLog: * tree.c (is_byte_access_type): Don't use char_type_p. gcc/testsuite/ChangeLog: * g++.dg/Wclass-memaccess.C: Check that signed char and char16_t aren't treated as byte-access types.
2020-11-03[OpenACC] Use proper location to 'inform' of enclosing parent compute constructThomas Schwinge3-11/+104
Bug fix for recent commit beddd1762ad2bbe84dd776c54489153f83f21e56 "[OpenACC] More precise diagnostics for 'gang', 'worker', 'vector' clauses with arguments on 'loop' only allowed in 'kernels' regions": > [...], and 'inform' at the location of the enclosing parent > compute construct/[...]. Now really. gcc/ * omp-low.c (scan_omp_for) <OpenACC>: Use proper location to 'inform' of enclosing parent compute construct. gcc/testsuite/ * c-c++-common/goacc/pr92793-1.c: Extend. * gfortran.dg/goacc/pr92793-1.f90: Likewise.
2020-11-03c++: Don't try to parse a function declaration as deduction guide [PR97663]Jakub Jelinek2-0/+16
While these function declarations have NULL decl_specifiers->type, they have still type specifiers specified from which the default int in the return type is added, so we shouldn't try to parse those as deduction guides. 2020-11-03 Jakub Jelinek <jakub@redhat.com> PR c++/97663 * parser.c (cp_parser_init_declarator): Don't try to parse C++17 deduction guides if there are any type specifiers even when type is NULL. * g++.dg/cpp1z/class-deduction75.C: New test.
2020-11-03c++: DR2303, ambiguous base deduction [PR97453]kamlesh kumar2-2/+51
When there are two possible matches and one is a base of the other, choose the derived class rather than fail. gcc/cp/ChangeLog 2020-10-21 Kamlesh Kumar <kamleshbhalui@gmail.com> Jason Merrill <jason@redhat.com> PR c++/97453 DR2303 * pt.c (get_template_base): Consider closest base in template deduction when base of base also matches. gcc/testsuite/ChangeLog 2020-10-21 Kamlesh Kumar <kamleshbhalui@gmail.com> * g++.dg/DRs/dr2303.C: New test.
2020-11-03Add missing non-NULL check in cgraphclonesJan Hubicka1-1/+1
2020-11-03 Jan Hubicka <hubicka@ucw.cz> PR ipa/97698 * cgraphclones.c (duplicate_thunk_for_node): Check that info is non-NULL.
2020-11-03c++: using-decl instantiationNathan Sidwell1-4/+11
In streaming using decls I needed to check some assumptions. This adds those checks to the instantiation machinery. gcc/cp/ * pt.c (tsubst_expr): Simplify using decl instantiation, add asserts.
2020-11-03c++: Refactor clone copyingNathan Sidwell1-17/+20
This patch sets copy_fndecl_with_name to always inform rest_of_decl_compilation that it is not a top-level decl (it's a member function). I also refactor build_cdtor_clones to conditionally do the method vector updating. That happens to be a better interface for modules to use. gcc/cp/ * class.c (copy_fndecl_with_name): Always not top level. (build_cdtor_clones): Add update_methods parm, use it to conditionally update the method vec. Return void (clone_cdtor): Adjust. (clone_constructors_and_destructors): Adjust comment.
2020-11-03i386: Fix ix86_function_arg_regno_p to return correct SSE regno for 32bit ↵Uros Bizjak2-15/+9
TARGET_MACHO Use up to SSE_REGPARM_MAX registers to pass function parameters for 32bit Mach-O targets. Also, define X86_32_MMX_REGPARM_MAX to return 0 for 32bit Mach-O targets. 2020-11-03 Uroš Bizjak <ubizjak@gmail.com> gcc/ * config/i386/i386.c (ix86_function_arg_regno_p): Use up to SSE_REGPARM_MAX registers to pass function parameters for 32bit Mach-O targets. * config/i386/i386.h (X86_32_MMX_REGPARM_MAX): New macro. (MMX_REGPARM_MAX): Use it.
2020-11-03c++: Small pt.c cleanupsNathan Sidwell1-3/+2
Now I know about VAR_OR_FUNCTION_DECL_P I found a place to use it. Also positively checking for a function_decl is clearer than negatively checking for things that are not. gcc/cp/ * pt.c (primary_template_specialization_p): Use VAR_OR_FUNCTION_DECL_P. (tsubst_template_decl): Check for FUNCTION_DECL, not !TYPE && !VAR for registering a specialization.
2020-11-03Add dg-require-effective-target fpic to gcc.target/powerpc testsOlivier Hainque3-1/+4
This helps powerpc-vxworks kernel mode. 2020-11-03 Olivier Hainque <hainque@adacore.com> gcc/testsuite/ * gcc.target/powerpc/pr67789.c: Add dg-require-effective-target fpic. * gcc.target/powerpc/pr83629.c: Likewise. * gcc.target/powerpc/pr84112.c: Likewise. Remove a superflous target test in the dg-do compile directive while at it.
2020-11-03aarch64: intrinsics extract half of bf16 vectorDennis Zhang7-0/+107
This patch implements ACLE intrinsics vget_low_bf16 and vget_high_bf16 to extract lower or higher half from a bfloat16x8 vector. The vget_high_bf16 is done by 'dup' instruction. The vget_low_bf16 is just to return the lower half of a vector register. Tests include both big- and little-endian cases. gcc/ChangeLog: 2020-11-03 Dennis Zhang <dennis.zhang@arm.com> * config/aarch64/aarch64-simd-builtins.def (vget_lo_half): New entry. (vget_hi_half): Likewise. * config/aarch64/aarch64-simd.md (aarch64_vget_lo_halfv8bf): New entry. (aarch64_vget_hi_halfv8bf): Likewise. * config/aarch64/arm_neon.h (vget_low_bf16): New intrinsic. (vget_high_bf16): Likewise. gcc/testsuite/ChangeLog * gcc.target/aarch64/advsimd-intrinsics/bf16_get.c: New test. * gcc.target/aarch64/advsimd-intrinsics/bf16_get-be.c: New test.
2020-11-03c++: Directly fixup deferred eh-specsNathan Sidwell3-12/+61
eh-specifiers in a class definition are complete-definition contexts, and we sometimes need to deferr their parsing. We create a deferred eh specifier, which can end up persisting in the type system due to variants being created before the deferred parse. This causes problems in modules handling. This patch adds fixup_deferred_exception_variants, which directly modifies the variants of such an eh spec once parsed. As commented, the general case is quite hard, so it doesn't deal with everything. But I do catch the cases I encountered (from the std library). gcc/cp/ * cp-tree.h (fixup_deferred_exception_variants): Declare. * parser.c (cp_parser_class_specifier_1): Call it when completing deferred parses rather than creating a variant. (cp_parser_member_declaration): Move comment from ... (cp_parser_noexcept_specification_opt): ... here. Refactor the deferred parse. * tree.c (fixup_deferred_exception_variants): New.
2020-11-03c++: A couple of template instantiation cleanupsNathan Sidwell1-13/+11
I noticed that we were handling lambda extra scope during template instantiation in a different order to how we handle the non-template case. Reordered that for consistency. Also some more RAII during template instantiation. gcc/cp/ * pt.c (tsubst_lambda_expr): Reorder extra-scope handling to match the non-template case. (instantiate_body): Move a couple of declarations to their initializers.
2020-11-03c++: Make extern-C mismatch an errorNathan Sidwell1-1/+1
duplicate_decls was being lenient about extern-c mismatches, allowing you to have two declarations in the symbol table after emitting an error. This resulted in duplicate error messages in modules, when we find the same problem multiple times. Let's just not let that happen. gcc/cp/ * decl.c (duplicate_decls): Return error_mark_node fo extern-c mismatch.
2020-11-03PR target/96342 Change field "simdlen" into poly_uint64Yang Yang8-64/+159
This is the first patch of PR96342. In order to add support for "omp declare simd", change the type of the field "simdlen" of struct cgraph_simd_clone from unsigned int to poly_uint64 and related adaptation. Since the length might be variable for the SVE cases. 2020-11-03 Yang Yang <yangyang305@huawei.com> gcc/ChangeLog: * cgraph.h (struct cgraph_simd_clone): Change field "simdlen" of struct cgraph_simd_clone from unsigned int to poly_uint64. * config/aarch64/aarch64.c (aarch64_simd_clone_compute_vecsize_and_simdlen): adaptation of operations on "simdlen". * config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Printf formats update. * gengtype.c (main): Handle poly_uint64. * omp-simd-clone.c (simd_clone_mangle): Likewise.Re (simd_clone_adjust_return_type): Likewise. (create_tmp_simd_array): Likewise. (simd_clone_adjust_argument_types): Likewise. (simd_clone_init_simd_arrays): Likewise. (ipa_simd_modify_function_body): Likewise. (simd_clone_adjust): Likewise. (expand_simd_clones): Likewise. * poly-int-types.h (vector_unroll_factor): New macro. * poly-int.h (constant_multiple_p): Add two-argument versions. * tree-vect-stmts.c (vectorizable_simd_clone_call): Likewise.
2020-11-03tree-optimization/97623 - limit PRE hoist insertionRichard Biener3-2/+14
This limits insert iteration caused by PRE insertions generating hoist insertion opportunities and vice versa. The patch limits the hoist insertion iterations to three by default. 2020-11-03 Richard Biener <rguenther@suse.de> PR tree-optimization/97623 * params.opt (-param=max-pre-hoist-insert-iterations): New. * doc/invoke.texi (max-pre-hoist-insert-iterations): Document. * tree-ssa-pre.c (insert): Do at most max-pre-hoist-insert-iterations hoist insert iterations.
2020-11-03middle-end/97579 - fix VEC_COND_EXPR ISEL optab queryRichard Biener1-2/+3
This fixes a mistake in the optab query done by ISEL. It doesn't fix the PR but shifts the ICE elsewhere. 2020-11-03 Richard Biener <rguenther@suse.de> PR middle-end/97579 * gimple-isel.cc (gimple_expand_vec_cond_expr): Use the correct types for the vcond_mask/vec_cmp optab queries.
2020-11-03More Ranger cache tweaksAndrew MacLeod2-45/+79
This patch splits the individual value propagation out from fill_block_cache, and calls it from set_global_value when the global value is updated. This ensures the "current" global value is reflected in the on-entry cache. * gimple-range-cache.cc (ssa_global_cache::get_global_range): Return true if there was a previous range set. (ranger_cache::ranger_cache): Take a gimple_ranger parameter. (ranger_cache::set_global_range): Propagate the value if updating. (ranger_cache::propagate_cache): Renamed from iterative_cache_update. (ranger_cache::propagate_updated_value): New. Split from: (ranger_cache::fill_block_cache): Split out value propagator. * gimple-range-cache.h (ssa_global_cache): Update prototypes. (ranger_cache): Update prototypes.
2020-11-03Tweaks to ranger cacheAndrew MacLeod3-25/+86
Add some bounds checking to ssa_block_ranges, and privatize the ranges block cache and global cache, adding API points for accessing them. * gimple-range-cache.h (block_range_cache): Add new entry point. (ranger_cache): Privatize global abnd block cache members. * gimple-range-cache.cc (ssa_block_ranges::set_bb_range): Add bounds check. (ssa_block_ranges::set_bb_varying): Ditto. (ssa_block_ranges::get_bb_range): Ditto. (ssa_block_ranges::bb_range_p): Ditto. (block_range_cache::get_block_ranges): Fix formatting. (block_range_cache::query_block_ranges): New. (block_range_cache::get_bb_range): Use Query_block_ranges. (block_range_cache::bb_range_p): Ditto. (ranger_cache::dump): New. (ranger_cache::get_global_range): New. (ranger_cache::set_global_range): New. * gimple-range.cc (gimple_ranger::range_of_expr): Use new API. (gimple_ranger::range_of_stmt): Ditto. (gimple_ranger::export_global_ranges): Ditto. (gimple_ranger::dump): Ditto.
2020-11-03c++: Tweaks for value_dependent_expression_p.Marek Polacek2-2/+8
We may not call value_dependent_expression_p on expressions that are not potential constant expressions, otherwise value_d could crash, as I saw recently (in C++98). So beef up the checking in i_d_e_p. This revealed a curious issue: when we have __PRETTY_FUNCTION__ in a template function, we set its DECL_VALUE_EXPR to error_mark_node (cp_make_fname_decl), so potential_c_e returns false when it gets it, but value_dependent_expression_p handles it specially and says true. This broke lambda-generic-pretty1.C. So take care of that. And then also tweak uses_template_parms. gcc/cp/ChangeLog: * constexpr.c (potential_constant_expression_1): Treat __PRETTY_FUNCTION__ inside a template function as potentially-constant. * pt.c (uses_template_parms): Call instantiation_dependent_expression_p instead of value_dependent_expression_p. (instantiation_dependent_expression_p): Check potential_constant_expression before calling value_dependent_expression_p.
2020-11-03c++: Disable -Winit-list-lifetime in unevaluated operand [PR97632]Marek Polacek2-1/+16
Jon suggested turning this warning off when we're not actually evaluating the operand. This patch does that. gcc/cp/ChangeLog: PR c++/97632 * init.c (build_new_1): Disable -Winit-list-lifetime for an unevaluated operand. gcc/testsuite/ChangeLog: PR c++/97632 * g++.dg/warn/Winit-list4.C: New test.
2020-11-03Cleanup of a merge mistake in fold-const.cBernd Edlinger1-5/+0
This removes a duplicated statement. It was apparently introduced due to a merge mistake. 2020-11-03 Bernd Edlinger <bernd.edlinger@hotmail.de> * fold-const.c (getbyterep): Remove duplicated statement.
2020-11-03Fix PR97205Bernd Edlinger4-17/+45
This makes sure that stack allocated SSA_NAMEs are at least MODE_ALIGNED. Also increase the MEM_ALIGN for the corresponding rtl objects. gcc: 2020-11-03 Bernd Edlinger <bernd.edlinger@hotmail.de> PR target/97205 * cfgexpand.c (align_local_variable): Make SSA_NAMEs at least MODE_ALIGNED. (expand_one_stack_var_at): Increase MEM_ALIGN for SSA_NAMEs. gcc/testsuite: 2020-11-03 Bernd Edlinger <bernd.edlinger@hotmail.de> PR target/97205 * gcc.c-torture/compile/pr97205.c: New test.
2020-11-03AArch64: Add FLAG for AES/SHA/SM3/SM4 intrinsics [PR94442]zhengnannan1-27/+27
2020-11-03 Zhiheng Xie <xiezhiheng@huawei.com> Nannan Zheng <zhengnannan@huawei.com> gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def: Add proper FLAG for AES/SHA/SM3/SM4 intrinsics.
2020-11-03AArch64: Add FLAG for compare intrinsics [PR94442]zhengnannan1-9/+9
2020-11-03 Zhiheng Xie <xiezhiheng@huawei.com> Nannan Zheng <zhengnannan@huawei.com> gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def: Add proper FLAG for compare intrinsics.
2020-11-03Save some memory at debug stream-in timeRichard Biener1-0/+1
This allows us to release references to BLOCKs by not keeping them rooted in the external_die_map but instead remove it from there as soon as we created the corresponding stub DIE. For decls it doesn't help since we still keep the decl_die_table. 2020-11-03 Richard Biener <rguenther@suse.de> * dwarf2out.c (maybe_create_die_with_external_ref): Remove hashtable entry.
2020-11-03arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisicsAndrea Corallo9-12/+133
gcc/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * config/arm/arm_neon.h (vst2_lane_bf16, vst2q_lane_bf16) (vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16) (vst4q_lane_bf16): New intrinsics. * config/arm/arm_neon_builtins.def: Touch it for: __builtin_neon_vst2_lanev4bf, __builtin_neon_vst2_lanev8bf, __builtin_neon_vst3_lanev4bf, __builtin_neon_vst3_lanev8bf, __builtin_neon_vst4_lanev4bf,__builtin_neon_vst4_lanev8bf. gcc/testsuite/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_bf16_indices_1.c: Run it also for arm-*-*. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_bf16_indices_1.c: Likewise. * gcc.target/arm/simd/vstn_lane_bf16_1.c: New test.
2020-11-03arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisicsAndrea Corallo10-13/+148
gcc/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16) (vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16) (vld4q_lane_bf16): Add intrinsics. * config/arm/arm_neon_builtins.def: Touch for: __builtin_neon_vld2_lanev4bf, __builtin_neon_vld2_lanev8bf, __builtin_neon_vld3_lanev4bf, __builtin_neon_vld3_lanev8bf, __builtin_neon_vld4_lanev4bf, __builtin_neon_vld4_lanev8bf. * config/arm/iterators.md (VQ_HS): Add V8BF to the iterator. gcc/testsuite/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_bf16_indices_1.c: Run it also for the arm backend. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_bf16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_bf16_indices_1.c: Likewise. * gcc.target/arm/simd/vldn_lane_bf16_1.c: New test.
2020-11-03arm: Add vst1_bf16 + vst1q_bf16 intrinsicsAndrea Corallo3-2/+46
gcc/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * config/arm/arm_neon.h (vst1_bf16, vst1q_bf16): Add intrinsics. * config/arm/arm_neon_builtins.def : Touch for: __builtin_neon_vst1v4bf, __builtin_neon_vst1v8bf. gcc/testsuite/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/arm/simd/vst1_bf16_1.c: New test.
2020-11-03arm: Add vld1_bf16 + vld1q_bf16 intrinsicsAndrea Corallo4-2/+49
gcc/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * config/arm/arm-builtins.c (VAR14): Define macro. * config/arm/arm_neon_builtins.def: Touch for: __builtin_neon_vld1v4bf, __builtin_neon_vld1v8bf. * config/arm/arm_neon.h (vld1_bf16, vld1q_bf16): Add intrinsics. gcc/testsuite/ChangeLog 2020-10-29 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/arm/simd/vld1_bf16_1.c: New test.
2020-11-03arm: Add vst1_lane_bf16 + vstq_lane_bf16 intrinsicsAndrea Corallo5-2/+67
gcc/ChangeLog 2020-10-23 Andrea Corallo <andrea.corallo@arm.com> * config/arm/arm_neon.h (vst1_lane_bf16, vst1q_lane_bf16): Add intrinsics. * config/arm/arm_neon_builtins.def (STORE1LANE): Add v4bf, v8bf. gcc/testsuite/ChangeLog 2020-10-23 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/arm/simd/vst1_lane_bf16_1.c: New testcase. * gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise. * gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
2020-11-03arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsicsAndrea Corallo5-2/+71
gcc/ChangeLog 2020-10-21 Andrea Corallo <andrea.corallo@arm.com> * config/arm/arm_neon_builtins.def: Add to LOAD1LANE v4bf, v8bf. * config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add intrinsics. gcc/testsuite/ChangeLog 2020-10-21 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/arm/simd/vld1_lane_bf16_1.c: New testcase. * gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise. * gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
2020-11-03c++: cp_tree_equal cleanupsNathan Sidwell1-22/+26
A couple of small fixes. I noticed bind_template_template_parms was not marking the parm a template parm (this broke some module handling). Debugging CALL_EXPR comparisons led me to refactor cp_tree_equal's CALL_EXPR code (and my recent fix to debug printing of same). Finally TREE_VECS are best compared by comp_template_args. I recall that last piece being a left over from fixes during gcc-10. I've been using it on the modules branch since then. gcc/cp/ * tree.c (bind_template_template_parm): Mark the parm as a template parm. (cp_tree_equal): Refactor CALL_EXPR. Use comp_template_args for TREE_VECs.
2020-11-03c++: rtti cleanupsNathan Sidwell1-40/+48
Here are a few cleanups from the modules branch. Generally some RAII, and a bit of lazy namespace pushing. gcc/cp/ * rtti.c (init_rtti_processing): Move var decl to its init. (get_tinfo_decl): Likewise. Break out creation to called helper ... (get_tinfo_decl_direct): ... here. (build_dynamic_cast_1): Move var decls to their initializers. (tinfo_base_init): Set decl's location to BUILTINS_LOCATION. (get_tinfo_desc): Only push ABI namespace when needed. Set type's context.
2020-11-03libcpp: dependency emission tidyingNathan Sidwell2-6/+8
This patch cleans up the interface to the dependency generation a little. We now only check the option in one place, and the cpp_get_deps function returns nullptr if there are no dependencies. I also reworded the -MT and -MQ help text to be make agnostic -- as there are ideas about emitting, say, JSON. libcpp/ * include/mkdeps.h: Include cpplib.h (deps_write): Adjust first parm type. * mkdeps.c: Include internal.h (make_write): Adjust first parm type. Check phony option directly. (deps_write): Adjust first parm type. * init.c (cpp_read_main_file): Use get_deps. * directives.c (cpp_get_deps): Check option before initializing. gcc/c-family/ * c.opt (MQ,MT): Reword description to be make-agnostic. gcc/fortran/ * cpp.c (gfc_cpp_add_dep): Only add dependency if we're recording them. (gfc_cpp_init): Likewise for target.
2020-11-03aarch64: ACLE intrinsics convert BF16 to Float32Dennis Zhang7-0/+117
This patch enables intrinsics to convert BFloat16 scalar and vector operands to Float32 modes. The intrinsics are implemented by shifting each BFloat16 item 16 bits to left using shl/shll/shll2 instructions. gcc/ChangeLog: 2020-11-03 Dennis Zhang <dennis.zhang@arm.com> * config/aarch64/aarch64-simd-builtins.def(vbfcvt): New entry. (vbfcvt_high, bfcvt): Likewise. * config/aarch64/aarch64-simd.md(aarch64_vbfcvt<mode>): New entry. (aarch64_vbfcvt_highv8bf, aarch64_bfcvtsf): Likewise. * config/aarch64/arm_bf16.h (vcvtah_f32_bf16): New intrinsic. * config/aarch64/arm_neon.h (vcvt_f32_bf16): Likewise. (vcvtq_low_f32_bf16, vcvtq_high_f32_bf16): Likewise. gcc/testsuite/ChangeLog * gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c (test_vcvt_f32_bf16, test_vcvtq_low_f32_bf16): New tests. (test_vcvtq_high_f32_bf16, test_vcvth_f32_bf16): Likewise.
2020-11-03bootstrap/97666 - fix array of bool allocationRichard Biener1-1/+1
This fixes the bad assumption that sizeof (bool) == 1 2020-11-03 Richard Biener <rguenther@suse.de> PR bootstrap/97666 * tree-vect-slp.c (vect_build_slp_tree_2): Scale allocation of skip_args by sizeof (bool).
2020-11-03tree-optimization/80928 - SLP vectorize nested loop inductionRichard Biener3-65/+164
This adds SLP vectorization of nested inductions. 2020-11-03 Richard Biener <rguenther@suse.de> PR tree-optimization/80928 * tree-vect-loop.c (vectorizable_induction): SLP vectorize nested inductions. * gcc.dg/vect/vect-outer-slp-2.c: New testcase. * gcc.dg/vect/vect-outer-slp-3.c: Likewise.
2020-11-03testsuite: Fix gcc.target/i386/zero-scratch-regs-*.c scan-asm directivesUros Bizjak29-159/+163
Improve zero-scratch-regs-*.c scan-asm regexps and add target selectors for 32bit targets. 2020-11-03 Uroš Bizjak <ubizjak@gmail.com> gcc/testsuite/ChangeLog: * gcc.target/i386/zero-scratch-regs-1.c: Add ia32 target selector where appropriate. Improve scan-assembler regexp. * gcc.target/i386/zero-scratch-regs-2.c: Ditto. * gcc.target/i386/zero-scratch-regs-3.c: Ditto. * gcc.target/i386/zero-scratch-regs-4.c: Ditto. * gcc.target/i386/zero-scratch-regs-5.c: Ditto. * gcc.target/i386/zero-scratch-regs-6.c: Ditto. * gcc.target/i386/zero-scratch-regs-7.c: Ditto. * gcc.target/i386/zero-scratch-regs-8.c: Ditto. * gcc.target/i386/zero-scratch-regs-9.c: Ditto. * gcc.target/i386/zero-scratch-regs-10.c: Ditto. * gcc.target/i386/zero-scratch-regs-13.c: Ditto. * gcc.target/i386/zero-scratch-regs-14.c: Ditto. * gcc.target/i386/zero-scratch-regs-15.c: Ditto. * gcc.target/i386/zero-scratch-regs-16.c: Ditto. * gcc.target/i386/zero-scratch-regs-17.c: Ditto. * gcc.target/i386/zero-scratch-regs-18.c: Ditto. * gcc.target/i386/zero-scratch-regs-19.c: Ditto. * gcc.target/i386/zero-scratch-regs-20.c: Ditto. * gcc.target/i386/zero-scratch-regs-21.c: Ditto. * gcc.target/i386/zero-scratch-regs-22.c: Ditto. * gcc.target/i386/zero-scratch-regs-23.c: Ditto. * gcc.target/i386/zero-scratch-regs-24.c: Ditto. * gcc.target/i386/zero-scratch-regs-25.c: Ditto. * gcc.target/i386/zero-scratch-regs-26.c: Ditto. * gcc.target/i386/zero-scratch-regs-27.c: Ditto. * gcc.target/i386/zero-scratch-regs-28.c: Ditto. * gcc.target/i386/zero-scratch-regs-29.c: Ditto. * gcc.target/i386/zero-scratch-regs-30.c: Ditto. * gcc.target/i386/zero-scratch-regs-31.c: Ditto.
2020-11-03Add missing require-effective-target ltoOlivier Hainque1-0/+1
This prevents failure of an lto test in configurations missing LTO support, such as VxWorks for kernel mode. 2020-11-02 Olivier Hainque <hainque@adacore.com> gcc/testsuite/ * gcc.dg/tree-ssa/pr71077.c: Add dg-require-effective-target lto.
2020-11-03Add dg-require-effective-target fpic to gcc i386 testsOlivier Hainque14-0/+14
This change adds /* { dg-require-effective-target fpic } */ to tests in gcc.target/i386 that do use -fpic or -fPIC but don't currently query the target support. This corresponds to what many other fpic tests do and helps the vxWorks ports at least, as -fpic is typically not supported in at least one of the two major modes of such port (kernel vs RTP). 2020-11-03 Olivier Hainque <hainque@adacore.com> gcc/testsuite/ * gcc.target/i386/pr45352-1.c: Add dg-require-effective-target fpic. * gcc.target/i386/pr47602.c: Likewise. * gcc.target/i386/pr55151.c: Likewise. * gcc.target/i386/pr55458.c: Likewise. * gcc.target/i386/pr56348.c: Likewise. * gcc.target/i386/pr57097.c: Likewise. * gcc.target/i386/pr65753.c: Likewise. * gcc.target/i386/pr65915.c: Likewise. * gcc.target/i386/pr66232-5.c: Likewise. * gcc.target/i386/pr66334.c: Likewise. * gcc.target/i386/pr66819-2.c: Likewise. * gcc.target/i386/pr67265.c: Likewise. * gcc.target/i386/pr81481.c: Likewise. * gcc.target/i386/pr83994.c: Likewise.
2020-11-03Avoid recursion in tree-inlineJan Hubicka2-0/+38
gcc/ChangeLog: 2020-11-03 Jan Hubicka <hubicka@ucw.cz> PR ipa/97578 * ipa-inline-transform.c (maybe_materialize_called_clones): New function. (inline_transform): Use it. gcc/testsuite/ChangeLog: 2020-11-03 Jan Hubicka <hubicka@ucw.cz> * gcc.c-torture/compile/pr97578.c: New test.
2020-11-03testsuite/97688 - fix check_vect () with __AVX2__Richard Biener1-1/+1
This fixes the cpuid check to always specify a subleaf zero which is required to detect AVX2 and doesn't hurt for level one. Without this fix we get zero runtime coverage when -mavx2 is specified. 2020-11-03 Richard Biener <rguenther@suse.de> PR testsuite/97688 * gcc.dg/vect/tree-vect.h (check_vect): Fix the x86 cpuid check to always specify subleaf zero.
2020-11-03tree-optimization/97678 - fix SLP induction epilogue vectorizationRichard Biener3-7/+79
This restores not tracking SLP nodes for induction initial values in not nested context because this interferes with peeling and epilogue vectorization. 2020-11-03 Richard Biener <rguenther@suse.de> PR tree-optimization/97678 * tree-vect-slp.c (vect_build_slp_tree_2): Do not track the initial values of inductions when not nested. * tree-vect-loop.c (vectorizable_induction): Look at PHI node initial values again for SLP and not nested inductions. Handle LOOP_VINFO_MASK_SKIP_NITERS and cost invariants. * gcc.dg/vect/pr97678.c: New testcase.
2020-11-03Fortran: Add !GCC$ attributes DEPRECATEDTobias Burnus6-1/+56
gcc/fortran/ChangeLog: * decl.c (ext_attr_list): Add EXT_ATTR_DEPRECATED. * gfortran.h (ext_attr_id_t): Ditto. * gfortran.texi (GCC$ ATTRIBUTES): Document it. * resolve.c (resolve_variable, resolve_function, resolve_call, resolve_values): Show -Wdeprecated-declarations warning. * trans-decl.c (add_attributes_to_decl): Skip those with no middle_end_name. gcc/testsuite/ChangeLog: * gfortran.dg/attr_deprecated.f90: New test.
2020-11-03x86: Optimize aes<aeswideklvariant>u8 a bit, fix whitespaceUros Bizjak1-32/+35
2020-11-03 Uroš Bizjak <ubizjak@gmail.com> gcc/ * config/i386/sse.md (aes<aeswideklvariant>u8): Do not use xmm_regs array. Fix whitespace.
2020-11-03x86: Fix comment in ix86_expand_builtinUros Bizjak1-4/+4
2020-11-03 Uroš Bizjak <ubizjak@gmail.com> gcc/ * config/i386/i386-expand.c (ix86_expand_builtin): Fix comment.
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