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2025-08-12testsuite: fix jit.dg/test-error-impossible-must-tail-call.c [PR119783]David Malcolm1-2/+4
I added this test back in r7-934-g15c671a79ca66d, but it looks like r15-2125-g81824596361cf4 changed the error message. gcc/testsuite/ChangeLog: PR testsuite/119783 jit.dg/test-error-impossible-must-tail-call.c * jit.dg/test-error-impossible-must-tail-call.c (verify_code): Check that we get a suitable-looking error message, but don't try to specify exactly what the message is. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2025-08-12x86: Convert integer constant to mode of moveH.J. Lu1-0/+18
For (set (reg/v:DI 106 [ k ]) (const_int 3000000000 [0xb2d05e00])) ... (set (reg:V4SI 115 [ _13 ]) (vec_duplicate:V4SI (subreg:SI (reg/v:DI 106 [ k ]) 0))) ... (set (reg:V2SI 118 [ _9 ]) (vec_duplicate:V2SI (subreg:SI (reg/v:DI 106 [ k ]) 0))) we should generate (set (reg:SI 125) (const_int -1294967296 [0xffffffffb2d05e00])) (set (reg:V4SI 124) (vec_duplicate:V4SI (reg:VSI 125)) ... (set (reg:V4SI 115 [ _13 ]) (reg:V4SI 124) ... (set (reg:V2SI 118 [ _9 ]) (subreg:V2SI (reg:V4SI 124)) by converting integer constant to mode of move. gcc/ PR target/121497 * config/i386/i386-features.cc (ix86_broadcast_inner): Convert integer constant to mode of move gcc/testsuite/ PR target/121497 * gcc.target/i386/pr121497.c: New test. Co-authored-by: Liu, Hongtao <hongtao.liu@intel.com> Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-08-13Daily bump.GCC Administrator1-0/+65
2025-08-13RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR ↵Pan Li18-0/+398
cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vmerge.vvm combine to vmerge.vxm, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2025-08-12RISC-V: Expand const_vector with 2 elts per pattern.Robin Dapp1-0/+10
Hi, In PR121334 we are asked to expand a const_vector of size 4 with poly_int elements. It has 2 elts per pattern so is neither a const_vector_duplicate nor a const_vector_stepped. We don't allow this kind of constant in legitimate_constant_p but expr apparently still wants us to expand it under certain conditions. This patch implements a basic expander for such kinds of patterns. As slide1up is used to build the individual vectors it also adds a helper function expand_slide1up. I regtested on rv64gcv_zvl512b but unfortunately the newly created pattern is not even executed. I tried some variations of the original code but didn't manage to trigger it. Regards Robin PR target/121334 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_slide1up): New function. (expand_vector_init_trailing_same_elem): Use new function. (expand_const_vector_onestep): New function. (expand_const_vector): Uew expand_slide1up. (expand_vector_init_merge_repeating_sequence): Ditto. (shuffle_off_by_one_patterns): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr121334.c: New test.
2025-08-12fwprop: Don't propagate asms [PR121253]Richard Sandiford1-0/+16
For the reasons explained in the comment, fwprop shouldn't even try to propagate an asm definition. gcc/ PR rtl-optimization/121253 * fwprop.cc (forward_propagate_into): Don't propagate asm defs. gcc/testsuite/ PR rtl-optimization/121253 * gcc.target/aarch64/pr121253.c: New test.
2025-08-12tree-optimization/121509 - failure to detect unvectorizable loopRichard Biener1-0/+42
With the hybrid stmt detection no longer working as a gate-keeper to detect unhandled stmts we have to, and can, detect those earlier. The appropriate place is vect_mark_stmts_to_be_vectorized where for trivially relevant PHIs we can stop analyzing when the PHI wasn't classified as a known def during vect_analyze_scalar_cycles. PR tree-optimization/121509 * tree-vect-stmts.cc (vect_mark_stmts_to_be_vectorized): Fail early when we detect a relevant but not handled PHI. * gcc.dg/vect/pr121509.c: New testcase.
2025-08-12tree-optimization/121514 - ICE with recent VN improvementRichard Biener1-0/+20
When inserting a compensation stmt during VN we are making sure to register the result for the original stmt into the hashtable so VN iteration has the chance to converge and we avoid inserting another copy each time. But the implementation doesn't work for non-SSA name values, and is also not necessary for constants since we did not insert anything for them. The following appropriately guards the calls to vn_nary_op_insert_stmt as was already done in one place. PR tree-optimization/121514 * tree-ssa-sccvn.cc (visit_nary_op): Only call vn_nary_op_insert_stmt for SSA name result. * gcc.dg/torture/pr121514.c: New testcase.
2025-08-12tree-optimization/121493 - another missed VN with aggregate copyRichard Biener1-0/+23
This is another case where opportunistically handling a first aggregate copy where we failed to match up the refs exactly (as we don't insert missing handling components) yields to a failure in the second aggregate copy that we visit. Add another fixup to deal with such situations, in-line with that present opportunistic handling. PR tree-optimization/121493 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Opportunistically strip components with known offset. * gcc.dg/tree-ssa/ssa-fre-109.c: New testcase.
2025-08-12fortran: add optional lower arg to c_f_pointerYuao Ma3-0/+76
This patch adds support for the optional lower argument in intrinsic c_f_pointer specified in Fortran 2023. Test cases and documentation have also been updated. gcc/fortran/ChangeLog: * check.cc (gfc_check_c_f_pointer): Check lower arg legitimacy. * intrinsic.cc (add_subroutines): Teach c_f_pointer about lower arg. * intrinsic.h (gfc_check_c_f_pointer): Add lower arg. * intrinsic.texi: Update lower arg for c_f_pointer. * trans-intrinsic.cc (conv_isocbinding_subroutine): Add logic handle lower. gcc/testsuite/ChangeLog: * gfortran.dg/c_f_pointer_shape_tests_7.f90: New test. * gfortran.dg/c_f_pointer_shape_tests_8.f90: New test. * gfortran.dg/c_f_pointer_shape_tests_9.f90: New test. Signed-off-by: Yuao Ma <c8ef@outlook.com>
2025-08-11Improve initial code generation for addsi/adddiShreya Munnangi1-0/+40
This is a patch primarily from Shreya, though I think she cribbed some code from Philipp that we had internally within Ventana and I made some minor adjustments as well. So the basic idea here is similar to her work on logical ops -- specifically when we can generate more efficient code at expansion time, then do so. In some cases the net is better code; in other cases we lessen reliance on mvconst_internal and finally it provides infrastructure that I think will help address an issue Paul Antoine reported a little while back. The most obvious case is using paired addis from initial code generation for some constants. It will also use a shNadd insn when the cost to synthesize the original value is higher than the right-shifted value. Finally it will negate the constant and use "sub" if the negated constant is cheaper than the original constant. There's more work to do in here, particularly WRT 32 bit objects for rv64. Shreya is looking at that right now. There may also be cases where another shNadd or addi would be profitable. We haven't really explored those cases in any detail, while there may be cases to handle, it's unclear how often they occur in practice. I don't want to remove the define_insn_and_split for the paired addi cases yet. I think that likely happens as a side effect of fixing Paul Antoine's issue. Bootstrapped and regression tested on a BPI & Pioneer box. Will obviously wait for the pre-commit tester before moving forward. Jeff PR target/120603 gcc/ * config/riscv/riscv-protos.h (synthesize_add): Add prototype. * config/riscv/riscv.cc (synthesize_add): New function. * config/riscv/riscv.md (addsi3): Allow any constant as operands[2] in the expander. Force the constant into a register as needed for TARGET_64BIT. Use synthesize_add for !TARGET_64BIT. (*adddi3): Renamed from adddi3. (adddi3): New expander. Use synthesize_add. gcc/testsuite * gcc.target/riscv/add-synthesis-1.c: New test. Co-authored-by: Jeff Law <jlaw@ventanamicro.com> Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2025-08-11cobol: Bring EBCDIC NumericDisplay variables into IBM compliance.Robert Dubner1-3/+3
The internal representation of Numeric Display (ND) zoned decimal variables when operating in EBCDIC mode has been brought into compliance with IBM conventions. This requires changes to data input, data output, internal conversion of zoned decimal to binary, and variable assignment. gcc/cobol/ChangeLog: * genapi.cc (compare_binary_binary): Formatting. (cobol_compare): Formatting. (mh_numeric_display): Rewrite "move ND to ND" algorithm. (initial_from_initial): Proper initialization of EBCDIC ND variables. * genmath.cc (fast_add): Delete comment. * genutil.cc (get_binary_value): Modify for updated EBCDIC. libgcobol/ChangeLog: * common-defs.h (NUMERIC_DISPLAY_SIGN_BIT): New comment; new constant. (EBCDIC_MINUS): New constant. (EBCDIC_PLUS): Likewise. (EBCDIC_ZERO): Likewise. (EBCDIC_NINE): Likewise. (PACKED_NYBBLE_PLUS): Likewise. (PACKED_NYBBLE_MINUS): Likewise. (PACKED_NYBBLE_UNSIGNED): Likewise. (NUMERIC_DISPLAY_SIGN_BIT_ASCII): Likewise. (NUMERIC_DISPLAY_SIGN_BIT_EBCDIC): Likewise. (SEPARATE_PLUS): Likewise. (SEPARATE_MINUS): Likewise. (ZONED_ZERO): Likewise. (ZONE_SIGNED_EBCDIC): Likewise. * configure: Regenerate. * libgcobol.cc (turn_sign_bit_on): Handle new EBCDIC sign convention. (turn_sign_bit_off): Likewise. (is_sign_bit_on): Likewise. (int128_to_field): EBCDIC NumericDisplay conversion. (get_binary_value_local): Likewise. (format_for_display_internal): Likewise. (normalize_id): Likewise. (__gg__inspect_format_1): Convert EBCDIC negative numbers to positive. * stringbin.cc (packed_from_combined): Quell cppcheck warning. gcc/testsuite/ChangeLog: * cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.out: Change test for updated handling of Numeric Display variables.
2025-08-12Daily bump.GCC Administrator1-0/+148
2025-08-11aarch64: Fix condition accepted by mov<ALLI>ccRichard Henderson2-3/+16
Reject QI/HImode conditions, which would require extension in order to compare. Fixes z.c:10:1: error: unrecognizable insn: 10 | } | ^ (insn 23 22 24 2 (set (reg:CC 66 cc) (compare:CC (reg:HI 128) (reg:HI 127))) "z.c":6:6 -1 (nil)) during RTL pass: vregs gcc: * config/aarch64/aarch64.md (mov<ALLI>cc): Accept MODE_CC conditions directly; reject QI/HImode conditions. gcc/testsuite: * gcc.target/aarch64/cmpbr-3.c: New. * gcc.target/aarch64/ifcvt_multiple_sets_rewire.c: Simplify test for csel by ignoring the actual registers used.
2025-08-11aarch64: CMPBR branches must be invertableRichard Henderson2-4/+114
Restrict the immediate range to the intersection of LT/GE and GT/LE so that cfglayout can invert the condition to redirect any branch. gcc: PR target/121388 * config/aarch64/aarch64.cc (aarch64_cb_rhs): Restrict the range of LT/GE and GT/LE to their intersections. * config/aarch64/aarch64.md (*aarch64_cb<INT_CMP><GPI>): Unexport. Use cmpbr_imm_predicate instead of aarch64_cb_rhs. * config/aarch64/constraints.md (Uc1): Accept 0..62. (Uc2): Remove. * config/aarch64/iterators.md (cmpbr_imm_predicate): New. (cmpbr_imm_constraint): Update to match aarch64_cb_rhs. * config/aarch64/predicates.md (aarch64_cb_reg_i63_operand): New. (aarch64_cb_reg_i62_operand): New. gcc/testsuite: PR target/121388 * gcc.target/aarch64/cmpbr.c (u32_x0_ult_64): XFAIL. (i32_x0_slt_64, u64_x0_ult_64, i64_x0_slt_64): XFAIL. * gcc.target/aarch64/cmpbr-2.c: New.
2025-08-11aarch64: Fix gcc.target/aarch64/cmpbr.c enableRichard Henderson1-1/+0
gcc/testsuite: * gcc.target/aarch64/cmpbr.c: Only compile, not assemble, since we want to scan the assembly.
2025-08-11aarch64: Remove cc clobber from *aarch64_tbz<LTGE><ALLI>1Richard Henderson1-0/+25
There is a conflict between aarch64_tbzltdi1 and aarch64_cbltdi with respect to pnum_clobbers, resulting in a recog failure: 0xa1fffe fancy_abort(char const*, int, char const*) ../../gcc/diagnostics/context.cc:1640 0x81340e patch_jump_insn ../../gcc/cfgrtl.cc:1303 0xc0eafe redirect_branch_edge ../../gcc/cfgrtl.cc:1330 0xc0f372 cfg_layout_redirect_edge_and_branch ../../gcc/cfgrtl.cc:4736 0xbfb6b9 redirect_edge_and_branch(edge_def*, basic_block_def*) ../../gcc/cfghooks.cc:391 0x1fa9310 try_forward_edges ../../gcc/cfgcleanup.cc:561 0x1fa9310 try_optimize_cfg ../../gcc/cfgcleanup.cc:2931 0x1fa9310 cleanup_cfg(int) ../../gcc/cfgcleanup.cc:3143 0x1fe11e8 rest_of_handle_cse ../../gcc/cse.cc:7591 0x1fe11e8 execute ../../gcc/cse.cc:7622 The simplest solution is to remove the clobber from aarch64_tbz. This removes the possibility of expansion via TST+B.cond, which will merely fall back to TBNZ+B on shorter branches. gcc: PR target/121385 * config/aarch64/aarch64.md (*aarch64_tbz<LTGE><ALLI>1): Remove cc clobber and expansion via TST+Bcond. gcc/testsuite: PR target/121385 * gcc.target/aarch64/cmpbr-1.c: New.
2025-08-11aarch64: Fix gcs save/restore_stack_nonlocalRichard Henderson1-1/+1
The save/restore_stack_nonlocal patterns passed a DImode rtx to gen_tbranch_neqi3 for a QImode compare. But since we're seeding r16 with 1, GCSEnabled will clear the only set bit in r16, so we can use CBNZ instead of TBNZ. gcc: * config/aarch64/aarch64.md (tbranch_<EQL><SHORT>3): Remove. (save_stack_nonlocal): Use aarch64_gen_compare_zero_and_branch. (restore_stack_nonlocal): Likewise. gcc/testsuite: * gcc.target/aarch64/gcs-nonlocal-3.c: Match cbnz.
2025-08-11Fortran: gfortran rejects procedure binding on PDT [PR121398]Paul Thomas1-0/+94
2025-08-11 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/121398 * resolve.cc (check_pdt_args): New function. (check_generic_tbp_ambiguity): Use it to ensure that args to typebound procedures that do not have the same declared type as the containing derived type have 'pass1/2' set to null. This avoids false ambiguity errors. (resolve_typebound_procedure): Do not generate a wrong type error for typebound procedures marked as pass if they are of a different declared type to the containing pdt_type. gcc/testsuite/ PR fortran/121398 * gfortran.dg/pdt_generic_1.f90: New test.
2025-08-11forwprop: Recongize a store of integral zero for optimize_aggr_zeroprop.Andrew Pinski5-0/+134
While looking into the gimple level after optimization of the highway code from google, I noticed in .optimized we still have: ``` MEM <vector(8) short int> [(short int *)&a] = { 0, 0, 0, 0, 0, 0, 0, 0 }; D.4398 = a; a ={v} {CLOBBER(eos)}; D.4389 = D.4398; D.4390 = D.4389; D.4361 = D.4390; D.4195 = D.4361; return D.4195; ``` Note this is with SRA disabled since I noticed there is better code generation with SRA disabled but that is a different story and I will get to that later on. Which could be just optimized to a single store of `{}` . The reason why the optimize_agr_copyprop does not handle the above is there was clobbers inbetween the store in the last forwprop pass and currently don't copy after the first use. While optimize_aggr_zeroprop does handle copying over clobbers just fine. So this allows the recognization of the store to a to be like a memset to optimize_aggr_zeroprop and then the result just falls through. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-forwprop.cc (optimize_aggr_zeroprop): Recognize stores of integer_zerop as memset of 0. gcc/testsuite/ChangeLog: * gcc.dg/torture/copy-prop-aggr-zero-1.c: New test. * gcc.dg/torture/copy-prop-aggr-zero-2.c: New test. * gcc.dg/tree-ssa/copy-prop-aggregate-zero-1.c: New test. * gcc.dg/tree-ssa/copy-prop-aggregate-zero-2.c: New test. * gcc.dg/tree-ssa/copy-prop-aggregate-zero-3.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-08-11Don't run tests requiring "B" on designs without "B"Jeff Law5-5/+30
So I resurrected our milkv pioneer over the weekend. While we had the tell-tale signs of PCIE switch issues, it actually appears that the NMVE drive was failing. I had an NVME that was going to be installed in a different system, so I threw it into the Pioneer as a last ditch effort to get it functional again. Voila! It's a happy camper (so far). Naturally I don't like manual testing, so cobbled together a new target for my tester. I forgot to update one field when doing that and as a result it picked up testsuite prior test results from the job that runs on the BPI. So comparing test results from a BPI to the Pioneer wouldn't normally be interesting. We'd expect to see a whole bunch of tests disappear as the Pioneer doesn't have all kinds of extensions that the BPI does (and that does indeed happen). As it turns out we have a handful of tests which need bitmanip to run, but which don't restrict themselves to only run on appropriate hardware. So we might as well fix that. Given the Pioneer/BPI take 6/24 hours to cycle through respectively I just spot checked the testsuite changes. Pushing to the trunk. gcc/ * doc/sourcebuild.texi: Add riscv_b_ok and riscv_v_ok target selectors. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_riscv_b_ok): New. * gcc.target/riscv/pr116085.c: Use new target selector. * gcc.target/riscv/pr117690.c: Use new target selector. * gcc.target/riscv/pr120333.c: Use new target selector. * gcc.target/riscv/zba-shNadd-10.c: Use new target selector.
2025-08-11tree-optimization/121488 - improve BIT_FIELD_REF lookup in VNRichard Biener1-0/+30
When a BIT_FIELD_REF lookup combined with a defining load RHS results in a wrongly typed result, try looking up or inserting a VIEW_CONVERT_EXPR to the desired type. PR tree-optimization/121488 * tree-ssa-sccvn.cc (visit_nary_op): If the BIT_FIELD_REF result is of wrong type, try a VIEW_CONVERT_EXPR around it. * gcc.dg/tree-ssa/ssa-fre-108.c: New testcase.
2025-08-11RISC-V: Add testcase for scalar unsigned SAT_MUL form 2Pan Li9-0/+119
Add run and asm check test cases for scalar unsigned SAT_MUL form 2. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat/sat_u_mul-3-u16.c: New test. * gcc.target/riscv/sat/sat_u_mul-3-u32.c: New test. * gcc.target/riscv/sat/sat_u_mul-3-u64.c: New test. * gcc.target/riscv/sat/sat_u_mul-3-u8.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-3-u16.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-3-u32.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-3-u64.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-3-u8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2025-08-11RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost paramPan Li48-127/+127
The previous cost value for vec_duplicate almost bases on the operators like add/minus. The rtx_cost function try to match them case by case and find if it has vec_duplicate, then update the cost values. It is Ok when we initially add it but looks confused/redundant as more and more operators are involved. As Robin's suggestion, we only care about the sub-rtx has vec_duplicate or not, instead of take care of it by operators. Thus, this PR would like to refactor that and get rid of the operators when compute the vec_duplicate cost. The below test suites are passed for this patch series. * The rv64gcv fully regression test. gcc/ChangeLog: * config/riscv/riscv.cc (get_vector_binary_rtx_cost): Remove. (riscv_rtx_costs): Refactor to serach vec_duplicate on the sub rtx. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Update asm check due to above change. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2025-08-11arm: Fix operand check for __arm_{mrrc{2},mcrr{2]} intrinsics [PR 121464]Andre Vieira4-6/+77
Fix the bound checking for the opc1 operand of the following intrinsics: __arm_mcrr __arm_mcrr2 __arm_mrrc __arm_mrrc2 gcc/ChangeLog: PR target/121464 * config/arm/arm.md (arm_<mrrc>, arm_<mcrr>): Fix operand check. gcc/testsuite/ChangeLog: PR target/121464 * gcc.target/arm/acle/mcrr.c: Update testcase. * gcc.target/arm/acle/mcrr2.c: Likewise. * gcc.target/arm/acle/mrrc.c: Likewise. * gcc.target/arm/acle/mrrc2.c: Likewise.
2025-08-11Fix comment typosJakub Jelinek3-3/+3
This patch fixes some comment typos, singe -> single and unsinged -> unsigned. 2025-08-11 Jakub Jelinek <jakub@redhat.com> gcc/ * tree-cfg.cc (find_case_label_for_value): Fix comment typo, singe-valued -> single-valued. * config/arc/arc.md: Fix comment typos, unsinged -> unsigned. gcc/fortran/ * gfortran.h (gfc_case): Fix comment typo, singe -> single. gcc/testsuite/ * g++.dg/warn/template-1.C: Fix comment typo, unsinged -> unsigned. * gcc.target/powerpc/builtins-2-p9-runnable.c (main): Likewise. * gcc.dg/graphite/id-30.c: Likewise.
2025-08-11c++: Fix up handling of name independent structured binding packs [PR117783]Jakub Jelinek1-0/+129
I've realized I haven't added testsuite coverage for name independent structured binding packs. And the auto [i, ..._, j] = T {}; auto [k, ..._, l] = T {}; case shows a problem with that. The elements of the structured binding pack have #i appended to their names, so for the _ case e.g. _#0, _#1 etc. (to print something useful in diagnostics, perhaps debug info later on). The above is valid though as long as one doesn't use _ (which is ambiguous), but we were emitting errors on redeclaration of _#0, _#1 etc. The following patch uses DECL_NAME (decl) = NULL_TREE; for the name independent decl case so that the false positive redeclaration errors aren't emitted. 2025-08-11 Jakub Jelinek <jakub@redhat.com> PR c++/117783 * decl.cc (set_sb_pack_name): For name independent decls just clear DECL_NAME instead of appending #i to it. * g++.dg/cpp26/name-independent-decl11.C: New test.
2025-08-11c++: Implement mangling for structured binding packs [PR117783]Jakub Jelinek2-2/+77
On Wed, Aug 06, 2025 at 11:53:55AM -0700, Jason Merrill wrote: > The Clang mangling of the underlying variable seems fine, just mentioning > the bound names; we can't get mangling collisions between pack and non-pack > versions of the same name. > > But It looks like they use .N discriminators for the individual elements, > which is wrong because . is reserved for implementation details. But I'd > think it should be fine to use [<discriminator>] instead. If you want the whole structured bindings to be mangled normally as if the pack isn't a pack and the individual vars of the structured binding pack mangled as multiple occurrences of the named entities, the following patch does that. 2025-08-11 Jakub Jelinek <jakub@redhat.com> PR c++/117783 * decl.cc (cp_finish_decomp): Don't sorry on tuple static structured bindings with a pack, instead temporarily reset DECL_NAME of the individual vars in the pack to the name of the pack for cp_finish_decl time and force mangling. * g++.dg/cpp26/decomp19.C: Don't expect sorry on tuple static structured bindings with a pack. * g++.dg/cpp26/decomp26.C: New test.
2025-08-11c++: Fix structured binding redeclaration error recovery [PR121442]Jakub Jelinek1-0/+13
My C++26 P2686R4 PR117784 caused ICE on the following testcase. While the earlier conditions guarantee decl2 is not error_mark_node, decl can be (that is used when something erroneous has been seen earlier and the whole structured bindings will be ignored after parsing). So, the following patch avoids the copying of constexpr/constinit flags if decl is error_mark_node. 2025-08-11 Jakub Jelinek <jakub@redhat.com> PR c++/121442 * parser.cc (cp_parser_decomposition_declaration): Don't copy DECL_DECLARED_CONST{EXPR,INIT}_P bits from decl to decl2 if decl is error_mark_node. * g++.dg/cpp1z/decomp65.C: New test.
2025-08-11Daily bump.GCC Administrator1-0/+38
2025-08-10asm-hard-reg-6.c: Adjust scan for x86 with ia32, lp64 and x32H.J. Lu1-4/+6
Since i?86 and x86_64 GCC can generate codes for ia32, x32 and lp64, adjust asm-hard-reg-6.c scan for x86 with ia32, lp64 and x32. PR testsuite/121205 * gcc.dg/asm-hard-reg-6.c: Adjust scan for x86 with ia32, lp64 and x32. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-08-10asm-hard-reg-5.c: Compile for x86 !ia32H.J. Lu1-1/+1
Since i?86 and x86_64 GCC can generate codes for ia32, x32 and lp64, compile asm-hard-reg-5.c for x86 !ia32. PR testsuite/121205 * gcc.dg/asm-hard-reg-5.c: Compile for x86 !ia32. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-08-10asm-hard-reg-4.c: Compile for x86 with -msse2 and scan x86H.J. Lu1-3/+4
Since i?86 and x86_64 GCC can generate codes for ia32, x32 and lp64, compile asm-hard-reg-4.c for x86 with -msse2 and scan x86 PR testsuite/121205 * gcc.dg/asm-hard-reg-4.c: Compile with -msse2 for x86 and scan x86. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-08-10asm-hard-reg-2.c: Compile for x86 !ia32 and scan x86H.J. Lu1-2/+2
Since i?86 and x86_64 GCC can generate codes for ia32, x32 and lp64, compile asm-hard-reg-2.c for x86 !ia32 and scan x86. PR testsuite/121205 * gcc.dg/asm-hard-reg-2.c: Compile for x86 !ia32 and scan x86. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-08-10asm-hard-reg-1.c: Adjust scan for x86 with ia32, x32 and lp64H.J. Lu1-4/+5
Since i?86 and x86_64 GCC can generate codes for ia32, x32 and lp64, adjust asm-hard-reg-1.c scan for x86 with ia32, x32 and lp64. PR testsuite/121205 * gcc.dg/asm-hard-reg-1.c: Adjust scan for x86 with ia32, x32 and lp64. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-08-10testsuite: i386: Fix gcc.target/i386/pr90579.c when PIE is enabled [PR118885]Harish Sadineni1-1/+1
When gcc build with --enable-deafult-pie the following tests were getting failed: FAIL: gcc.target/i386/pr90579.c scan-assembler vaddsd\tr\\+40 FAIL: gcc.target/i386/pr90579.c scan-assembler vaddsd\tr\\+32 FAIL: gcc.target/i386/pr90579.c scan-assembler vaddsd\tr\\+24 FAIL: gcc.target/i386/pr90579.c scan-assembler vaddsd\tr\\+16 PR target/118885 gcc/testsuite/ChangeLog: * gcc.target/i386/pr90579.c: add -fno-pie to dg-options to fix tests when PIE is enabled. Signed-off-by: Harish Sadineni <Harish.Sadineni@windriver.com>
2025-08-10testsuite: handle-multiline-outputs must allow both cc1 and cc1.exeTorbjörn SVENSSON1-0/+3
Prior to 14-2027-g985d6480fe5, the input text had the file extensions pruned. In 14-2027-g985d6480fe5, due to the move of the call, the pruning is never done. This change restores the pruning of the file extension to allow multiline test to pass on both Windows and other platforms like Linux. gcc/testsuite/ChangeLog: * lib/multiline.exp: Added pruning of .exe. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
2025-08-10Daily bump.GCC Administrator1-0/+25
2025-08-09asm-hard-reg-2.c: Use long long on z to trigger RA errorH.J. Lu1-1/+1
Use long long on z to trigger error: 'asm' operand has impossible constraints or there are not enough registers for -m32 on asm statements like: __asm__ __volatile__ ("" : "=A" (z), "={rax}" (y)); PR testsuite/121205 * gcc.target/i386/asm-hard-reg-2.c (z): Use long long for -m32 to trigger RA error. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-08-09Fortran: Correct wrong PR numbersPaul Thomas1-1/+1
2025-08-09testsuite: Skip class-11_a.H for default_packed targetsDimitar Dimitrov2-0/+2
The g++.dg/modules/class-11_a.H test expects structs to have a padding. Skip this test for targets which have packed structs by default. This patch fixes the test for pru-unknown-elf from FAIL to UNSUPPORTED. The test still passes on x86_64-linux-gnu. gcc/testsuite/ChangeLog: * g++.dg/modules/class-11_a.H: Skip test for effective default_packed targets. * g++.dg/modules/class-11_b.C: Ditto. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2025-08-09Fortran: F2018 GENERIC statement is missing [PR121182]Paul Thomas4-0/+420
2025-08-09 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/121182 * decl.cc (match_generic_stmt): New function based on original gfc_match_generic but feeding namespace rather than typebound generics. (match_typebound_generic): Renamed original gfc_match_generic. (gfc_match_generic): New function that selects between type bound generic and other generic statements and calls one of the above two functions as appropriate. * parse.cc (decode_specification_statement): Allow generic statements. (parse_spec): Accept a generic statement in a specification block. gcc/testsuite/ PR fortran/121182 * gfortran.dg/generic_stmt_1.f90: New test. * gfortran.dg/generic_stmt_2.f90: New test. * gfortran.dg/generic_stmt_3.f90: New test. * gfortran.dg/generic_stmt_4.f90: New test.
2025-08-09testsuite: Require atomic operations for hardbool-ai.cDimitar Dimitrov1-0/+1
The test uses _Atomic int type, so add a filter to ensure the target supports it. This fixes a spurious test failure on pru-unknown-elf, which lacks atomic ops. The test still passes on x86_64-linux-gnu. gcc/testsuite/ChangeLog: * gcc.dg/torture/hardbool-ai.c: Require target that supports atomic operations on int types. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2025-08-09Daily bump.GCC Administrator1-0/+60
2025-08-08forwprop: Don't do copy-prop-aggregates from statements that could throw ↵Andrew Pinski1-0/+26
[PR120599] In the testcase provided, currently we lose the landing pad for the exception that could throw from the aggregate load as we remove one copy and the second statement where load happens was not marked as throwable before so the landing pad for that internal throw is now gone. The fix is to ignore statements that could throw (internally or externally). PR tree-optimization/120599 gcc/ChangeLog: * tree-ssa-forwprop.cc (optimize_agr_copyprop): Don't try to copy from statements that throw. gcc/testsuite/ChangeLog: * g++.dg/torture/noncall-eh-1.C: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-08-08forwprop: Change proping memset into memcpy into a forwprop rather than a ↵Andrew Pinski3-0/+86
backwalk One thing I noticed while working on copy prop for aggregates is that we start with a memcpy like statement and then walk backwards. This means we could have a few walks backwards to see there was no statement for zeroing. Instead this changes the walk backwards into a true forwprop. In the future we can expand to forwprop the zeroing into say an function argument or something more than memcpy like statement. This should speed up slightly the compile time performance since there will be less memsets like statements than memcpy and there is only one walk forwards for memset like staments instead of multiple walk backwards to find the memset. Note this does add one extra improvement, the memcpy now does not need to have an address as its dest argument; this could have been done before too but it was even more noticable now because of the variable became only set so it was removed and the check was removed as well. There is also a fix on how ao_ref for the memset/memcpy is done, before it was just using ao_ref_init which is wrong since it should instead of used ao_ref_init_from_ptr_and_size. This part fixes PR 121422. Changes since v1: * v2: Add back limit on the walk which was missed in v1. Move the call to get_addr_base_and_unit_offset outside of the vuse loop. * v3: Remove extra check before the call to optimize_aggr_zeroprop_1. Fix setting up of ao_ref for memset (PR121422). PR tree-optimization/118946 PR tree-optimization/121422 gcc/ChangeLog: * tree-ssa-forwprop.cc (optimize_memcpy_to_memset): Remove. (optimize_aggr_zeroprop_1): New function. (optimize_aggr_zeroprop): New function. (simplify_builtin_call): Don't call optimize_memcpy_to_memset for memcpy but call optimize_aggr_zeroprop for memset. (pass_forwprop::execute): Don't call optimize_memcpy_to_memset for aggregate copies but rather call optimize_aggr_zeroprop for aggregate stores. gcc/testsuite/ChangeLog: * gcc.dg/pr118946-1.c: New test. * gcc.dg/torture/pr121422-1.c: New test. * gcc.dg/torture/pr121422-2.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-08-08diagnostics: enable nested diagnostics by default [PR116253]David Malcolm9-6/+41
In GCC 15 I added an experimental nesting view in text sinks for hierarchical diagnostics, such as C++ template problems. This patch enables it for text sinks by default. The old behavior can be restored via -fno-diagnostics-show-nesting, which the patch also adds to -fdiagnostics-plain-output. The patch does not yet enable it for text sinks in sarif-replay. gcc/ChangeLog: PR diagnostics/116253 * common.opt (fdiagnostics-show-nesting): New option. (fdiagnostics-show-nesting-locations): New option. (fdiagnostics-show-nesting-levels): New option. * common.opt.urls: Regenerate. * diagnostics/context.cc (context::set_show_nesting): New. (context::set_show_nesting_locations): New. (context::set_show_nesting_levels): New. * diagnostics/context.h (context::set_show_nesting): New decl. (context::set_show_nesting_locations): New decl. (context::set_show_nesting_levels): New decl. * diagnostics/html-sink.cc: Tweak comment. * diagnostics/output-spec.cc (text_scheme_handler::make_sink): Rename "experimental-nesting" to "show-nesting" and enable by default. Rename "experimental-nesting-show-locations" to "show-nesting-locations". Rename "experimental-nesting-show-levels" to "show-nesting-levels". * diagnostics/sink.h (sink::dyn_cast_text_sink): New. * diagnostics/text-sink.h (text_sink::dyn_cast_text_sink): New. * doc/invoke.texi: Add -fdiagnostics-show-nesting, -fdiagnostics-show-nesting-locations, and -fdiagnostics-show-nesting-levels. Update for changes to output-spec.cc above. * lto-wrapper.cc (merge_and_complain): Ignore OPT_fdiagnostics_show_nesting, OPT_fdiagnostics_show_nesting_locations, and OPT_fdiagnostics_show_nesting_levels. (append_compiler_options): Likewise. (append_diag_options): Likewise. * opts-common.cc (decode_cmdline_options_to_array): Add "-fno-diagnostics-show-nesting" to -fdiagnostics-plain-output. * opts.cc (common_handle_option): Handle the new options. (gen_command_line_string): Ignore the new options. * toplev.cc (general_init): Call set_show_nesting, set_show_nesting_locations, and set_show_nesting_levels on global_dc. gcc/testsuite/ChangeLog: PR diagnostics/116253 * g++.dg/concepts/nested-diagnostics-1-truncated.C: Update for renamed keys to -fdiagnostics-set-output=text * g++.dg/concepts/nested-diagnostics-1.C: Likewise. * g++.dg/concepts/nested-diagnostics-2.C: Likewise. * gcc.dg/plugin/diagnostic-test-nesting-no-show-nesting.c: New test. * gcc.dg/plugin/diagnostic-test-nesting-show-nesting.c: New test. * gcc.dg/plugin/diagnostic-test-nesting-text-indented-show-levels.c: Update for renamed keys to -fdiagnostics-set-output=text. * gcc.dg/plugin/diagnostic-test-nesting-text-indented-unicode.c: Likewise. * gcc.dg/plugin/diagnostic-test-nesting-text-indented.c: Likewise. * gcc.dg/plugin/plugin.exp: Add the new tests. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2025-08-08arm: Fix CMSE nonecure calls [PR 120977]Christophe Lyon2-3/+18
As discussed in https://gcc.gnu.org/pipermail/gcc-patches/2025-June/685733.html the operand of the call should be a mem rather than an unspec. This patch moves the unspec to an additional argument of the parallel and adjusts cmse_nonsecure_call_inline_register_clear accordingly. The scan-rtl-dump in cmse-18.c needs a fix since we no longer emit the 'unspec' part. In addition, I noticed that since arm_v8_1m_mve_ok is always true in the context of the test (we know we support CMSE as per cmse.exp, and arm_v8_1m_mve_ok finds the adequate options), we actually only use the more permissive regex. To improve that, the patch duplicates the test, such that cmse-18.c forces -march=armv8-m.main+fp (so FPCXP is disabled), and cmse-19.c forces -march=armv8.1-m.main+mve (so FPCXP is enabled). Each test uses the appropriate scan-rtl-dump, and also checks we are using UNSPEC_NONSECURE_MEM (we need to remove -slim for that). The tests enable an FPU via -march so that the test passes whether the testing harness forces -mfloat-abi or not. 2025-07-08 Christophe Lyon <christophe.lyon@linaro.org> PR target/120977 gcc/ * config/arm/arm.md (call): Move unspec parameter to parallel. (nonsecure_call_internal): Likewise. (call_value): Likewise. (nonsecure_call_value_internal): Likewise. * config/arm/thumb1.md (nonsecure_call_reg_thumb1_v5): Likewise. (nonsecure_call_value_reg_thumb1_v5): Likewise. * config/arm/thumb2.md (nonsecure_call_reg_thumb2_fpcxt): Likewise. (nonsecure_call_reg_thumb2): Likewise. (nonsecure_call_value_reg_thumb2_fpcxt): Likewise. (nonsecure_call_value_reg_thumb2): Likewise. * config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear): Likewise. gcc/testsuite * gcc.target/arm/cmse/cmse-18.c: Check only the case when FPCXT is not enabled. * gcc.target/arm/cmse/cmse-19.c: New test.
2025-08-08AArch64: Fix invalid immediate offsets in SVE gather/scatter [PR121449]Pengfei Li1-0/+44
This patch fixes incorrect constraints in RTL patterns for AArch64 SVE gather/scatter with type widening/narrowing and vector-plus-immediate addressing. The bug leads to below "immediate offset out of range" errors during assembly, eventually causing compilation failures. /tmp/ccsVqBp1.s: Assembler messages: /tmp/ccsVqBp1.s:54: Error: immediate offset out of range 0 to 31 at operand 3 -- `ld1b z1.d,p0/z,[z1.d,#64]' Current RTL patterns for such instructions incorrectly use vgw or vgd constraints for the immediate operand, base on the vector element type in Z registers (zN.s or zN.d). However, for gather/scatter with type conversions, the immediate range for vector-plus-immediate addressing is determined by the element type in memory, which differs from that in vector registers. Using the wrong constraint can produce out-of-range offset values that cannot be encoded in the instruction. This patch corrects the constraints used in these patterns. A test case that reproduces the issue is also included. Bootstrapped and regression-tested on aarch64-linux-gnu. gcc/ChangeLog: PR target/121449 * config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>): Use vg<Vesize> constraints for alternatives with immediate offset. (mask_scatter_store<mode><v_int_container>): Likewise. gcc/testsuite/ChangeLog: PR target/121449 * g++.target/aarch64/sve/pr121449.C: New test.
2025-08-08aarch64: Relax fpm_t assert to allow const_ints [PR120986]Alex Coplan1-0/+7
This relaxes an overzealous assert that required the fpm_t argument to be in DImode when expanding FP8 intrinsics. Of course this fails to account for modeless const_ints. gcc/ChangeLog: PR target/120986 * config/aarch64/aarch64-sve-builtins.cc (function_expander::expand): Relax fpm_t assert to allow modeless const_ints. gcc/testsuite/ChangeLog: PR target/120986 * gcc.target/aarch64/torture/pr120986-2.c: New test.
generated by cgit v1.1 at 2025-09-19 16:38:13 +0000