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AgeCommit message (Expand)AuthorFilesLines
2023-05-09aarch64: Improve register allocation for lane instructionsRichard Sandiford247-367/+367
2023-05-09aarch64: Fix cut-&-pasto in aarch64-sve2-acle-asm.expRichard Sandiford1-1/+1
2023-05-09aarch64: Avoid hard-coding specific register allocationsRichard Sandiford33-272/+269
2023-05-09aarch64: Relax FP/vector register matchesRichard Sandiford22-82/+82
2023-05-09aarch64: Relax predicate register matchesRichard Sandiford21-449/+449
2023-05-09aarch64: Relax ordering requirements in SVE dup testsRichard Sandiford6-0/+384
2023-05-09aarch64: Allow moves after tied-register intrinsicsRichard Sandiford38-0/+360
2023-05-09aarch64: Fix move-after-intrinsic function-body testsRichard Sandiford5-7/+7
2023-05-09ira: Don't create copies for earlyclobbered pairsRichard Sandiford18-18/+18
2023-05-08[x86_64] Introduce insvti_highpart define_insn_and_split.Roger Sayle1-0/+12
2023-05-08RISC-V: Improve portability of testcasesKito Cheng3-2/+13
2023-05-08RISC-V: Fix ugly && incorrect codes of RVV auto-vectorizationJuzhe-Zhong1-2/+2
2023-05-07rs6000: Load high and low part of 64bit constant independentlyJiufu Guo1-0/+27
2023-05-07Don't call emit_clobber in lower-subreg.cc's resolve_simple_move.Roger Sayle1-0/+11
2023-05-07LoongArch: Enable shrink wrappingXi Ruoyao1-0/+19
2023-05-06RISC-V: Enable basic RVV auto-vectorization support.Juzhe-Zhong34-0/+425
2023-05-06RISC-V: Fix incorrect demand info merge in local vsetvli optimization [PR109748]Juzhe-Zhong1-0/+36
2023-05-06CRIS: peephole2 an add into two addq or subqHans-Peter Nilsson1-0/+52
2023-05-06CRIS: peephole2 a move of constant followed by and of same registerHans-Peter Nilsson1-0/+17
2023-05-06CRIS: peephole2 a lsrq into a lslq+lsrq pairHans-Peter Nilsson2-0/+38
2023-05-05RISC-V: Legitimise the const0_rtx for RVV indexed load/storePan Li1-1/+2
2023-05-05RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSETPan Li1-5/+1
2023-05-05RISC-V: Fix PR109615Juzhe-Zhong3-3/+36
2023-05-05i386: Introduce mulv2si3 instructionUros Bizjak1-0/+27
2023-05-04[1/2] aarch64: Reimplement (R){ADD,SUB}HN intrinsics with RTL codesKyrylo Tkachov1-0/+35
2023-05-04aarch64: PR target/99195 annotate simple ternary ops for vec-concat with zeroKyrylo Tkachov1-0/+68
2023-05-04aarch64: PR target/99195 annotate more simple binary ops for vec-concat with ...Kyrylo Tkachov2-8/+16
2023-05-04CRIS: peephole2 an "and" with a contiguous "one-sided" sequences of 1sHans-Peter Nilsson5-11/+36
2023-05-03aarch64: Fix ABI handling of aligned enums [PR109661]Richard Sandiford1-0/+11
2023-05-03arm: [MVE intrinsics] Rework vreinterpretqChristophe Lyon2-0/+40
2023-05-03RISC-V: Add tuple types supportJu-Zhe Zhong45-0/+5391
2023-05-03aarch64: PR target/99195 annotate HADDSUB patterns for vec-concat with zeroKyrylo Tkachov1-6/+10
2023-05-03aarch64: PR target/99195 annotate simple floating-point patterns for vec-conc...Kyrylo Tkachov2-0/+83
2023-05-02target: [PR109657] (a ? -1 : 0) | b could be optimized better for aarch64Andrew Pinski1-0/+26
2023-05-02RISC-V: Table A.6 conformance testsPatrick O'Neill28-0/+360
2023-05-02RISC-V: Strengthen atomic storesPatrick O'Neill1-0/+9
2023-05-02RISC-V: ICE for vlmul_ext_v intrinsic APIYanzhang Wang1-0/+14
2023-05-02[i386] Fix testcases for emulated scatterRichard Biener4-5/+8
2023-04-30[Committed] Update xstormy16's neghi2 pattern to not clobber the carry flag.Roger Sayle1-1/+1
2023-04-29[xstormy16] Efficient HImode rotate left by a single bit.Roger Sayle2-0/+18
2023-04-29[xstormy16] Recognize/support swpn (swap nibbles) instruction.Roger Sayle4-0/+77
2023-04-29Adjust mips test for recent ifcvt costing changesJeff Law2-4/+4
2023-04-29RISC-V: decouple stack allocation for rv32e w/o save-restoreFei Gao1-0/+14
2023-04-28RISC-V: Add divmod expansion supportMatevos Mehrabyan2-0/+27
2023-04-28RISC-V: Added support clmul[r,h] instructions for Zbc extension.Karen Sargsyan2-0/+46
2023-04-28RISC-V: Eliminate redundant zero extension of minu/maxu operandsJivan Hakobyan2-2/+15
2023-04-28PR rtl-optimization/109476: Use ZERO_EXTEND instead of zeroing a SUBREG.Roger Sayle1-0/+11
2023-04-28Adjust costing of emulated vectorized gather/scatterRichard Biener3-2/+25
2023-04-28RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLRPan Li1-0/+291
2023-04-28aarch64: PR target/99195 annotate more integer unary patterns for vec-concat ...Kyrylo Tkachov1-2/+24
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