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2023-06-26GIMPLE_FOLD: Fix gimple fold for LEN_{MASK}_{LOAD,STORE}Ju-Zhe Zhong1-0/+43
2023-06-26RISC-V: Fix one test failure of dg config.Juzhe-Zhong1-1/+1
2023-06-25RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE}Juzhe-Zhong2-1/+29
2023-06-25RISC-V: fix expand function of vlmul_ext RVV intrinsicLi Xu1-0/+8
2023-06-25RISC-V: Enable len_mask{load, store} and remove len_{load, store}Juzhe-Zhong6-0/+241
2023-06-25Revert "RISC-V:Add float16 tuple type abi"Pan Li8-612/+4
2023-06-25Revert "RISC-V:Add float16 tuple type support"Pan Li5-222/+0
2023-06-25RISC-V:Add float16 tuple type abiyulong8-4/+612
2023-06-24RISC-V: Support RVV floating-point auto-vectorizationJuzhe-Zhong36-20/+1162
2023-06-20RISC-V: testsuite: Add missing -mabi=lp64d.Robin Dapp9-9/+9
2023-06-20RISC-V: Set the natural size of constant vector mask modes to one RVV data ve...Li Xu1-0/+11
2023-06-20RISC-V: Optimize codegen of VLA SLPJuzhe-Zhong3-0/+92
2023-06-20RISC-V: testsuite: Add -Wno-psabi to vec_set/vec_extract testcases.Robin Dapp10-10/+10
2023-06-20RISC-V: testsuite: Fix vmul test expectation and fix -ffast-math.Robin Dapp5-3/+5
2023-06-20RISC-V: Fix fails of testcasesJuzhe-Zhong4-4/+4
2023-06-20RISC-V: Add tuple vector mode psABI checking and simplify codeLehua Ding40-38/+87
2023-06-19RISC-V: Save and restore FCSR in interrupt functions to avoid program errors.Jin Ma3-0/+44
2023-06-19RISC-V: Bugfix for RVV widenning reduction in ZVE32/64Pan Li8-0/+90
2023-06-19RISC-V: Bugfix for RVV float reduction in ZVE32/64Pan Li4-0/+86
2023-06-19RISC-V: Add autovec FP unary operations.Robin Dapp16-34/+249
2023-06-19RISC-V: Add autovec FP binary operations.Robin Dapp31-35/+396
2023-06-19RISC-V: Add sign-extending variants for vmv.x.s.Robin Dapp4-0/+8
2023-06-19RISC-V: Implement vec_set and vec_extract.Robin Dapp12-0/+1191
2023-06-19RISC-V: Add (u)int8_t to binop tests.Robin Dapp44-70/+171
2023-06-18RISC-V:Add float16 tuple type supportyulong5-0/+222
2023-06-17RISC-V: Bugfix for RVV integer reduction in ZVE32/64.Pan Li5-0/+163
2023-06-15RISC-V: Use merge approach to optimize vector permutationJuzhe-Zhong14-0/+1364
2023-06-15RISC-V: Ensure vector args and return use function stack to pass [PR110119]Lehua Ding2-0/+52
2023-06-13RISC-V: Add more SLP testsJuzhe-Zhong10-0/+393
2023-06-13RISC-V: Fix bug of VLA SLP auto-vectorizationJuzhe-Zhong2-0/+67
2023-06-13RISC-V: Add vector psabi checking.Yanzhang Wang21-15/+109
2023-06-13RISC-V: Fix one typo in full-vec-movel testPan Li1-1/+1
2023-06-13RISC-V: Fix V_WHOLE && V_FRACT iterator requirementJuzhe-Zhong1-0/+23
2023-06-13RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operationJuzhe-Zhong4-0/+121
2023-06-12RISC-V: Fix one potential test failure for RVV vsetvlPan Li1-1/+1
2023-06-12RISC-V: Support RVV FP16 MISC vget/vset intrinsic APIPan Li2-10/+37
2023-06-12RISC-V: Add RVV narrow shift right lowering auto-vectorizationJuzhe-Zhong6-0/+236
2023-06-12RISC-V: Add ZVFHMIN block autovec testcaseJuzhe-Zhong1-0/+35
2023-06-12RISC-V: Add test cases for RVV FP16 undefined and vlmul truncPan Li2-16/+78
2023-06-12RISC-V: Support RVV FP16 MISC vlmul ext intrinsic APIPan Li2-8/+64
2023-06-11RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASSJuzhe-Zhong6-3/+82
2023-06-10RISC-V: Add test cases for RVV FP16 vreinterpretPan Li2-2/+50
2023-06-10RISC-V: Enable select_vl for RVV auto-vectorizationJuzhe-Zhong3-2/+28
2023-06-09RISC-V: Refactor requirement of ZVFH and ZVFHMIN.Pan Li1-2/+13
2023-06-08RISC-V: Add more test cases for RVV FP16Pan Li2-2/+57
2023-06-07RISC-V: Eliminate extension after for *w instructionsJeff Law4-3/+105
2023-06-07RISC-V: Support RVV VLA SLP auto-vectorizationJuzhe-Zhong23-14/+616
2023-06-06RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmizationJuzhe-Zhong6-0/+185
2023-06-05RISC-V] add TC for save-restore cfi directives.Fei Gao1-0/+17
2023-06-06RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic APIPan Li1-2/+56