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path: root/gcc/testsuite/gcc.target/aarch64/sve
AgeCommit message (Expand)AuthorFilesLines
2024-04-08aarch64: Fix expansion of svsudot [PR114607]Richard Sandiford1-4/+4
2024-04-05aarch64: Fix bogus cnot optimisation [PR114603]Richard Sandiford1-0/+23
2024-04-04aarch64: Recognise svundef idiom [PR114577]Richard Sandiford2-0/+140
2024-03-05asan: Handle poly-int sizes in ASAN_MARK [PR97696]Richard Sandiford1-0/+29
2024-01-31match: Fix vcond into conditional op folding [PR113607].Robin Dapp1-1/+1
2024-01-31AArch64: relax cbranch tests to accepted inverted branches [PR113502]Tamar Christina1-6/+6
2024-01-29PR112950: Use #pragma GCC for including arm_sve.h.Prathamesh Kulkarni1-1/+1
2024-01-25aarch64: Fix out-of-bounds ENCODED_ELT access [PR113572]Richard Sandiford1-0/+12
2024-01-24AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636]Tamar Christina2-0/+26
2024-01-12aarch64: Use a separate group for SME builtins [PR112989]Richard Sandiford1-1/+1
2024-01-05aarch64: Extend VECT_COMPARE_COSTS to !SVE [PR113104]Richard Sandiford32-32/+32
2024-01-03Update copyright years.Jakub Jelinek4-4/+4
2023-12-29AArch64: Update costing for vector conversions [PR110625]Tamar Christina2-2/+2
2023-12-24AArch64: Add implementation for vector cbranch for Advanced SIMDTamar Christina1-0/+108
2023-12-15aarch64, testsuite: Allow ldp/stp on SVE regs with -msve-vector-bits=128Alex Coplan2-0/+61
2023-12-15aarch64: Handle autoinc addresses in ld1rq splitter [PR112906]Alex Coplan1-0/+17
2023-12-14aarch64: Improve handling of accumulators in early-raRichard Sandiford4-84/+349
2023-12-13aarch64: SVE/NEON Bridging intrinsicsRichard Ball40-1/+1122
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford2-3/+31
2023-12-07aarch64: add -fno-stack-protector to testsMarek Polacek1-1/+1
2023-12-05aarch64: Add support for SME2 intrinsicsRichard Sandiford42-26/+1881
2023-12-05aarch64: Add svboolx2_tRichard Sandiford2-3/+138
2023-12-05aarch64: Add svcount_tRichard Sandiford9-2/+278
2023-12-05aarch64: Add support for <arm_sme.h>Richard Sandiford10-3/+320
2023-12-05aarch64: Mark relevant SVE instructions as non-streamingRichard Sandiford190-2/+198
2023-12-05aarch64: Add tuple forms of svreinterpretRichard Sandiford13-0/+758
2023-12-05aarch64: Tweak error message for (tuple,vector) pairsRichard Sandiford3-6/+6
2023-12-05aarch64: Replace vague "previous arguments" messageRichard Sandiford26-98/+98
2023-12-05aarch64: Generalise some SVE ACLE error messagesRichard Sandiford79-137/+137
2023-12-05aarch64: Use SVE's RDVL instructionRichard Sandiford10-63/+83
2023-12-05lra: Updates of biggest mode for hard regs [PR112278]Richard Sandiford1-0/+15
2023-12-01c: Turn -Wincompatible-pointer-types into a permerrorFlorian Weimer19-53/+53
2023-12-01c: Turn -Wimplicit-function-declaration into a permerrorFlorian Weimer12-12/+12
2023-12-01c: Turn int-conversion warnings into permerrorsFlorian Weimer6-6/+6
2023-11-27PR111754: Rework encoding of result for VEC_PERM_EXPR with constant input vec...Prathamesh Kulkarni2-26/+8
2023-11-27aarch64: Remove redundant zeroing/merging in SVE intrinsics [PR106326]Richard Sandiford1-0/+378
2023-11-21AArch64: Add new generic-armv8-a CPU and make it the default.Tamar Christina4-4/+4
2023-11-13C99 testsuite readiness: -fpermissive testsFlorian Weimer1-1/+1
2023-11-09AArch64: Add SVE implementation for cond_copysign.Tamar Christina1-0/+36
2023-11-09AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD ineffici...Tamar Christina3-15/+7
2023-11-09middle-end: optimize fneg (fabs (x)) to copysign (x, -1) [PR109154]Tamar Christina4-0/+137
2023-11-05aarch64: Rework aarch64_modes_tieable_p [PR112105]Richard Sandiford1-2/+2
2023-10-19aarch64, testsuite: Tweak sve/pcs/args_9.c to allow stpsAlex Coplan1-2/+2
2023-10-18middle-end: Fold vec_cond into conditional ternary or binary operation when s...Tamar Christina1-0/+132
2023-10-17aarch64: Use vecs to store register save orderRichard Sandiford6-18/+18
2023-09-14aarch64: Restore SVE WHILE costingRichard Sandiford1-0/+13
2023-09-14aarch64: Coerce addresses to be suitable for LD1RQRichard Sandiford1-0/+33
2023-09-12aarch64: Explicitly record probe registers in frame infoRichard Sandiford1-4/+2
2023-09-04testsuite: aarch64: Adjust SVE ACLE tests to new generated codeThiago Jung Bauermann2-4/+2
2023-08-21MATCH: [PR111002] Sink view_convert for vec_condAndrew Pinski1-0/+22
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