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2024-02-16testsuite: Add support for scanning assembly with comparitorEdwin Lu1-0/+4
There is currently no support for matching at least x lines of assembly (only scan-assembler-times). This patch would allow setting upper or lower bounds. Use case: using different scheduler descriptions and/or cost models will change assembler output. Testing common functionality across tunes would require a separate testcase per tune since each assembly output would be different. If we know a base number of lines should appear across all tunes (i.e. testing return values: we expect at minimum n stores into register x), we can lower-bound the test to search for scan-assembler-bound {RE for storing into register x} >= n. This avoids artificially inflating the scan-assembler-times expected count due to the assembler choosing to perform extra stores into register x (using it as a temporary register). The testcase would be more robust to cpu/tune changes at the cost of not being as granular towards specific cpu tuning. gcc/ChangeLog: * doc/sourcebuild.texi: add scan-assembler-bound gcc/testsuite/ChangeLog: * lib/scanasm.exp: add scan-assembler-bound Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-02-16testsuite: Require lto-plugin support in gcc.dg/lto/modref-3 etc. [PR98237]Rainer Orth1-0/+7
gcc.dg/lto/modref-3 etc. FAIL on Solaris with the native linker: FAIL: gcc-dg-lto-modref-3-01.exe scan-wpa-ipa-dump modref "parm 1 flags: no_direct_clobber no_direct_escape" FAIL: gcc-dg-lto-modref-4-01.exe scan-wpa-ipa-dump modref "parm 1 flags: no_direct_clobber no_direct_escape" FAIL: gcc.dg/lto/modref-3 c_lto_modref-3_0.o-c_lto_modref-3_1.o execute -O2 -flto-partition=max -fdump-ipa-modref -fno-ipa-sra -fno-ipa-cp -flto FAIL: gcc.dg/lto/modref-4 c_lto_modref-4_0.o-c_lto_modref-4_1.o execute -O2 -flto-partition=max -fdump-ipa-modref -fno-ipa-sra -flto The issue is that the tests require the linker plugin, which isn't available with Solaris ld. Thus, it also FAILs when gcc is configured with --disable-lto-plugin. This patch thus declares the requirement. As it turns out, there's an undocumented dg-require-linker-plugin already, but I introduce and use the corresponding effective-target keyword and document both. Given that the effective-target form is more flexible, I'm tempted to remove dg-require-* with an empty arg as already mentioned in sourcebuild.texi. That is not this patch, however. Tested on i386-pc-solaris2.11 with ld and gld. 2024-02-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> gcc/testsuite: PR ipa/98237 * lib/target-supports.exp (is-effective-target): Handle linker_plugin. * gcc.dg/lto/modref-3_0.c: Require linker_plugin support. * gcc.dg/lto/modref-4_0.c: Likewise. gcc: * doc/sourcebuild.texi (Effective-Target Keywords, Other attribugs): Document linker_plugin. (Require Support): Document dg-require-linker-plugin.
2024-02-16RISC-V: Add new option -march=help to print all supported extensionsKito Cheng1-1/+2
The output of -march=help is like below: ``` All available -march extensions for RISC-V: Name Version i 2.0, 2.1 e 2.0 m 2.0 a 2.0, 2.1 f 2.0, 2.2 d 2.0, 2.2 ... ``` Also support -print-supported-extensions and --print-supported-extensions for clang compatibility. gcc/ChangeLog: PR target/109349 * common/config/riscv/riscv-common.cc (riscv_arch_help): New. * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. (RISCV_MINOR_VERSION_BASE): Ditto. (RISCV_REVISION_VERSION_BASE): Ditto. * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum rather than magic number. * config/riscv/riscv.h (riscv_arch_help): New. (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and --print-supported-extensions. * config/riscv/riscv.opt (march=help): New. (print-supported-extensions): New. (-print-supported-extensions): New. * doc/invoke.texi (RISC-V Options): Document -march=help. Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-02-15AVR: target 113927 - Simple code triggers stack frame for Reduced Tiny.Georg-Johann Lay1-4/+7
The -mmcu=avrtiny cores have no ADIW and SBIW instructions. This was implemented by clearing all regs out of regclass ADDW_REGS so that constraint "w" never matched. This corrupted the subset relations of the register classes as they appear in enum reg_class. This patch keeps ADDW_REGS like for all other cores, i.e. it contains R24...R31. Instead of tests like test_hard_reg_class (ADDW_REGS, *) the code now uses avr_adiw_reg_p (*). And all insns with constraint "w" get "isa" insn attribute value of "adiw". Plus, a new built-in macro __AVR_HAVE_ADIW__ is provided, which is more specific than __AVR_TINY__. gcc/ PR target/113927 * config/avr/avr.h (AVR_HAVE_ADIW): New macro. * config/avr/avr-protos.h (avr_adiw_reg_p): New proto. * config/avr/avr.cc (avr_adiw_reg_p): New function. (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS. Replace test_hard_reg_class (ADDW_REGS, ...) with calls to * config/avr/avr.md: Same. (attr "isa") <tiny, no_tiny>: Remove. <adiw, no_adiw>: Add. (define_insn, define_insn_and_split): When an alternative has constraint "w", then set attribute "isa" to "adiw". * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]: Built-in define __AVR_HAVE_ADIW__. * doc/invoke.texi (AVR Options): Document it.
2024-02-15doc: Add documentation of which operand matches the mode of the standard ↵Andrew Pinski1-0/+9
pattern name [PR113508] In some of the standard pattern names, it is not obvious which mode is being used in the pattern name. Is it operand 0, 1, or 2? Is it the wider mode or the narrower mode? This fixes that so there is no confusion by adding a sentence to some of them. Built the documentation to make sure that it builds. gcc/ChangeLog: PR middle-end/113508 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m}, usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3, smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3): Add sentence about what the mode m is. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-02-15doc: Fix some standard named pattern documentation modesAndrew Pinski1-16/+16
Currently these use `@var{m3}` but the 3 here is a literal 3 and not part of the mode itself so it should not be inside the var. Fixed as such. Built the documentation to make sure it looks correct now. gcc/ChangeLog: * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs, smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the var. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-02-14install: Update gettext linkGerald Pfeifer1-2/+2
gcc: * doc/install.texi (Prerequisites): Update gettext link.
2024-02-10c++: DR2237, cdtor and template-id tweaks [PR107126]Marek Polacek1-1/+18
Since my r11-532 changes to implement DR2237, for this test: template<typename T> struct S { S<T>(); }; in C++20 we emit the ugly: q.C:3:8: error: expected unqualified-id before ')' token 3 | S<T>(); which doesn't explain what the problem is. This patch improves that diagnostic, reduces the error to a pedwarn, and adds a -Wc++20-compat diagnostic. We now say: q.C:3:7: warning: template-id not allowed for constructor in C++20 [-Wtemplate-id-cdtor] 3 | S<T>(); q.C:3:7: note: remove the '< >' This patch also fixes <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97202#c8> where the C++20 diagnostic was missing altogether: The problem was that I checked for CPP_TEMPLATE_ID too early, at a point at which cp_parser_template_id may not have been called yet. So let's check for it at the end of the function, after the tentative parse and rollback. -Wc++20-compat triggered in libitm/; I sent a patch for that. DR 2237 PR c++/107126 PR c++/97202 gcc/c-family/ChangeLog: * c-opts.cc (c_common_post_options): In C++20 or with -Wc++20-compat, turn on -Wtemplate-id-cdtor. * c.opt (Wtemplate-id-cdtor): New. gcc/cp/ChangeLog: * parser.cc (cp_parser_unqualified_id): Downgrade the DR2237 error to a pedwarn. (cp_parser_constructor_declarator_p): Likewise. gcc/ChangeLog: * doc/invoke.texi: Document -Wtemplate-id-cdtor. gcc/testsuite/ChangeLog: * g++.dg/DRs/dr2237.C: Adjust dg-error. * g++.dg/parse/constructor2.C: Likewise. * g++.dg/template/error34.C: Likewise. * g++.old-deja/g++.pt/ctor2.C: Likewise. * g++.dg/DRs/dr2237-2.C: New test. * g++.dg/DRs/dr2237-3.C: New test. * g++.dg/DRs/dr2237-4.C: New test. * g++.dg/DRs/dr2237-5.C: New test. * g++.dg/warn/Wtemplate-id-cdtor-1.C: New test. * g++.dg/warn/Wtemplate-id-cdtor-2.C: New test. * g++.dg/warn/Wtemplate-id-cdtor-3.C: New test. * g++.dg/warn/Wtemplate-id-cdtor-4.C: New test.
2024-02-08AVR: target/113824 - Fix multilib set for ATA5795.Georg-Johann Lay1-2/+2
gcc/ PR target/113824 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4. * doc/avr-mmcu.texi: Rebuild.
2024-02-04RISC-V: Add sifive-p450, sifive-p67 to -mcpuMonk Chiang1-1/+2
gcc/ChangeLog: * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670. * doc/invoke.texi (RISC-V Options): Add sifive-p450, sifive-p670. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-sifive-p450.c: New test. * gcc.target/riscv/mcpu-sifive-p670.c: New test.
2024-02-04RISC-V: Support scheduling for sifive p400 seriesMonk Chiang1-2/+2
Add sifive p400 series scheduler module. For more information see https://www.sifive.com/cores/performance-p450-470. gcc/ChangeLog: * config/riscv/riscv.md: Include sifive-p400.md. * config/riscv/sifive-p400.md: New file. * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add sifive_p400. * config/riscv/riscv.cc (sifive_p400_tune_info): New. * config/riscv/riscv.h (TARGET_SFB_ALU): Update. * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2024-02-02doc: Fix typo in description of hardbool attributeJonathan Wakely1-1/+1
gcc/ChangeLog: * doc/extend.texi (Common Type Attributes): Fix typo in description of hardbool.
2024-02-01c++: -Wdangling-reference tweak to unbreak aarch64Marek Polacek1-1/+1
My recent -Wdangling-reference change to not warn on std::span-like classes unfortunately caused a new warning: extending reference_like_class_p also opens the door to new warnings since we use reference_like_class_p for checking the return type of the function: either it must be a reference or a reference_like_class_p. We can consider even non-templates as std::span-like to get rid of the warning here. gcc/cp/ChangeLog: * call.cc (reference_like_class_p): Consider even non-templates for std::span-like classes. gcc/ChangeLog: * doc/invoke.texi: Update -Wdangling-reference documentation. gcc/testsuite/ChangeLog: * g++.dg/warn/Wdangling-reference21.C: New test.
2024-02-01RISC-V: Support scheduling for sifive p600 seriesMonk Chiang1-1/+2
Add sifive p600 series scheduler module. For more information see https://www.sifive.com/cores/performance-p650-670. Add sifive-p650, sifive-p670 for mcpu option will come in separate patches. gcc/ChangeLog: * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type attribute, and include sifive-p600.md. * config/riscv/generic-ooo.md: Update type attribute. * config/riscv/generic.md: Update type attribute. * config/riscv/sifive-7.md: Update type attribute. * config/riscv/sifive-p600.md: New file. * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add sifive_p600. * config/riscv/riscv.cc (sifive_p600_tune_info): New. * config/riscv/riscv.h (TARGET_SFB_ALU): Update. * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
2024-02-01RISC-V: Add minimal support for 7 new unprivileged extensionsMonk Chiang1-0/+28
The RISC-V Profiles specification here: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions These extensions don't add any new features but describe existing features. So this patch only adds parsing. Za64rs: Reservation set size of 64 bytes Za128rs: Reservation set size of 128 bytes Ziccif: Main memory supports instruction fetch with atomicity requirement Ziccrse: Main memory supports forward progress on LR/SC sequences Ziccamoa: Main memory supports all atomics in A Zicclsm: Main memory supports misaligned loads/stores Zic64b: Cache block size isf 64 bytes gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items. * config/riscv/riscv.opt: New macro for 7 new unprivileged extensions. * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/za-ext.c: New test. * gcc.target/riscv/zi-ext.c: New test.
2024-01-31c++: add deprecation notice for -fconcepts-tsMarek Polacek1-1/+3
We plan to remove -fconcepts-ts in GCC 15 and thus remove the flag_concepts_ts code. This note is an admonishing reminder to convert the Concepts TS code to C++20 Concepts. gcc/c-family/ChangeLog: * c-opts.cc (c_common_post_options): Add an inform saying that -fconcepts-ts is deprecated and will be removed in GCC 15. gcc/ChangeLog: * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
2024-01-31AVR: Add AVR64DU and some older devices.Georg-Johann Lay1-3/+3
gcc/ * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787, ATA5835, ATtiny64AUTO, ATA5700M322. * doc/avr-mmcu.texi: Rebuild.
2024-01-310From: Alexandre Oliva <oliva@adacore.com>Alexandre Oliva3-1/+59
strub: introduce STACK_ADDRESS_OFFSET Since STACK_POINTER_OFFSET is not necessarily at the boundary between caller- and callee-owned stack, as desired by __builtin_stack_address(), and using it as if it were or not causes problems, introduce a new macro so that ports can define it suitably, without modifying STACK_POINTER_OFFSET. for gcc/ChangeLog PR middle-end/112917 PR middle-end/113100 * builtins.cc (expand_builtin_stack_address): Use STACK_ADDRESS_OFFSET. * doc/extend.texi (__builtin_stack_address): Adjust. * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define. * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document. * doc/tm.texi: Rebuilt.
2024-01-30i386: Add "Ws" constraint for symbolic address/label reference [PR105576]Fangrui Song1-0/+4
Printing the raw symbol is useful in inline asm (e.g. in C++ to get the mangled name). Similar constraints are available in other targets (e.g. "S" for aarch64/riscv, "Cs" for m68k). There isn't a good way for x86 yet, e.g. "i" doesn't work for PIC/-mcmodel=large. This patch adds "Ws". Here are possible use cases: ``` namespace ns { extern int var; } asm (".pushsection .xxx,\"aw\"; .dc.a %0; .popsection" :: "Ws"(&var)); asm (".reloc ., BFD_RELOC_NONE, %0" :: "Ws"(&var)); ``` gcc/ChangeLog: PR target/105576 * config/i386/constraints.md: Define constraint "Ws". * doc/md.texi: Document it. gcc/testsuite/ChangeLog: PR target/105576 * gcc.target/i386/asm-raw-symbol.c: New testcase.
2024-01-30c++: avoid -Wdangling-reference for std::span-like classes [PR110358]Marek Polacek1-0/+14
Real-world experience shows that -Wdangling-reference triggers for user-defined std::span-like classes a lot. We can easily avoid that by considering classes like template<typename T> struct Span { T* data_; std::size len_; }; to be std::span-like, and not warning for them. Unlike the previous patch, this one considers a non-union class template that has a pointer data member and a trivial destructor as std::span-like. PR c++/110358 PR c++/109640 gcc/cp/ChangeLog: * call.cc (reference_like_class_p): Don't warn for std::span-like classes. gcc/ChangeLog: * doc/invoke.texi: Update -Wdangling-reference description. gcc/testsuite/ChangeLog: * g++.dg/warn/Wdangling-reference18.C: New test. * g++.dg/warn/Wdangling-reference19.C: New test. * g++.dg/warn/Wdangling-reference20.C: New test.
2024-01-29install.texi: For gcn, recommend LLVM 15, unless gfx1100 is disabledTobias Burnus1-3/+4
gcc/ChangeLog: * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+, but keep requiring only newlib 4.3+ and, if gfx1100 is disabled, LLVM 13.0.1+. Signed-off-by: Tobias Burnus <tburnus@baylibre.com>
2024-01-28Fix __builtin_nested_func_ptr_{created,deleted} symbol versions [PR113402]Iain Sandoe1-2/+2
The symbols for the functions supporting heap-based trampolines were exported at an incorrect symbol version, the following patch fixes that. As requested in the PR, this also renames __builtin_nested_func_ptr* to __gcc_nested_func_ptr*. In carrying our the rename, we move the builtins to use DEF_EXT_LIB_BUILTIN. PR libgcc/113402 gcc/ChangeLog: * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED. * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED, BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and rename the library fallbacks to __gcc_nested_func_ptr_created and __gcc_nested_func_ptr_deleted. * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created and __gcc_nested_func_ptr_deleted. * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED. * tree.cc (build_common_builtin_nodes): Build the BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local builtins only for non-explicit. libgcc/ChangeLog: * config/aarch64/heap-trampoline.c: Rename __builtin_nested_func_ptr_created to __gcc_nested_func_ptr_created and __builtin_nested_func_ptr_deleted to __gcc_nested_func_ptr_deleted. * config/i386/heap-trampoline.c: Likewise. * libgcc2.h: Likewise. * libgcc-std.ver.in (GCC_7.0.0): Likewise and then move __gcc_nested_func_ptr_created and __gcc_nested_func_ptr_deleted from this symbol version to ... (GCC_14.0.0): ... this one. Signed-off-by: Iain Sandoe <iain@sandoe.co.uk> Co-authored-by: Jakub Jelinek <jakub@redhat.com>
2024-01-28doc/invoke: Remove duplicate explicit-relocs entry of MIPSYunQiang Su1-23/+12
When add new style -mexplicit-relocs=, the old style was not removed. gcc * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
2024-01-27x86: Add no_callee_saved_registers function attributeH.J. Lu1-0/+8
When an interrupt handler is implemented by an assembly stub which does: 1. Save all registers. 2. Call a C function. 3. Restore all registers. 4. Return from interrupt. it is completely unnecessary to save and restore any registers in the C function called by the assembly stub, even if they would normally be callee-saved. Add no_callee_saved_registers function attribute, which is complementary to no_caller_saved_registers function attribute, to mark a function which doesn't have any callee-saved registers. Such a function won't save and restore any registers. Classify function call-saved register handling type with: 1. Default call-saved registers. 2. No caller-saved registers with no_caller_saved_registers attribute. 3. No callee-saved registers with no_callee_saved_registers attribute. Disallow sibcall if callee is a no_callee_saved_registers function and caller isn't a no_callee_saved_registers function. Otherwise, callee-saved registers won't be preserved. After a no_callee_saved_registers function is called, all registers may be clobbered. If the calling function isn't a no_callee_saved_registers function, we need to preserve all registers which aren't used by function calls. gcc/ PR target/103503 PR target/113312 * config/i386/i386-expand.cc (ix86_expand_call): Replace no_caller_saved_registers check with call_saved_registers check. Clobber all registers that are not used by the callee with no_callee_saved_registers attribute. * config/i386/i386-options.cc (ix86_set_func_type): Set call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for noreturn function. Disallow no_callee_saved_registers with interrupt or no_caller_saved_registers attributes together. (ix86_set_current_function): Replace no_caller_saved_registers check with call_saved_registers check. (ix86_handle_no_caller_saved_registers_attribute): Renamed to ... (ix86_handle_call_saved_registers_attribute): This. (ix86_gnu_attributes): Add ix86_handle_call_saved_registers_attribute. * config/i386/i386.cc (ix86_conditional_register_usage): Replace no_caller_saved_registers check with call_saved_registers check. (ix86_function_ok_for_sibcall): Don't allow callee with no_callee_saved_registers attribute when the calling function has callee-saved registers. (ix86_comp_type_attributes): Also check no_callee_saved_registers. (ix86_epilogue_uses): Replace no_caller_saved_registers check with call_saved_registers check. (ix86_hard_regno_scratch_ok): Likewise. (ix86_save_reg): Replace no_caller_saved_registers check with call_saved_registers check. Don't save any registers for TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with no_callee_saved_registers attribute is called. (find_drap_reg): Replace no_caller_saved_registers check with call_saved_registers check. * config/i386/i386.h (call_saved_registers_type): New enum. (machine_function): Replace no_caller_saved_registers with call_saved_registers. * doc/extend.texi: Document no_callee_saved_registers attribute. gcc/testsuite/ PR target/103503 PR target/113312 * gcc.dg/torture/no-callee-saved-run-1a.c: New file. * gcc.dg/torture/no-callee-saved-run-1b.c: Likewise. * gcc.target/i386/no-callee-saved-1.c: Likewise. * gcc.target/i386/no-callee-saved-2.c: Likewise. * gcc.target/i386/no-callee-saved-3.c: Likewise. * gcc.target/i386/no-callee-saved-4.c: Likewise. * gcc.target/i386/no-callee-saved-5.c: Likewise. * gcc.target/i386/no-callee-saved-6.c: Likewise. * gcc.target/i386/no-callee-saved-7.c: Likewise. * gcc.target/i386/no-callee-saved-8.c: Likewise. * gcc.target/i386/no-callee-saved-9.c: Likewise. * gcc.target/i386/no-callee-saved-10.c: Likewise. * gcc.target/i386/no-callee-saved-11.c: Likewise. * gcc.target/i386/no-callee-saved-12.c: Likewise. * gcc.target/i386/no-callee-saved-13.c: Likewise. * gcc.target/i386/no-callee-saved-14.c: Likewise. * gcc.target/i386/no-callee-saved-15.c: Likewise. * gcc.target/i386/no-callee-saved-16.c: Likewise. * gcc.target/i386/no-callee-saved-17.c: Likewise. * gcc.target/i386/no-callee-saved-18.c: Likewise.
2024-01-26amdgcn: config.gcc - enable gfx1030 and gfx1100 multilib; add them to the docsTobias Burnus2-6/+12
gcc/ChangeLog: * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to TM_MULTILIB_CONFIG. * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100. * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to -march/-mtune. libgomp/ChangeLog: * testsuite/libgomp.c/declare-variant-4.h: Add variant functions for gfx1030 and gfx1100. * testsuite/libgomp.c/declare-variant-4-gfx1030.c: New test. * testsuite/libgomp.c/declare-variant-4-gfx1100.c: New test. Signed-off-by: Tobias Burnus <tburnus@baylibre.com>
2024-01-25RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2-0/+889
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVbitmanip. * config/riscv/constraints.md: Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/predicates.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. * doc/extend.texi: Add XCVbitmanip builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-simd-abs-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-abs-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxconj-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-march-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-packhi-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-packlo-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c: New test. * lib/target-supports.exp: Add proc for XCVsimd extension.
2024-01-25docs: Fix 2 typosJakub Jelinek2-2/+2
When looking into PR113572, I've noticed a typo in VECTOR_CST documentation and grep found pasto of it elsewhere. 2024-01-25 Jakub Jelinek <jakub@redhat.com> * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns. * doc/rtl.texi (CONST_VECTOR): Likewise.
2024-01-24Add -fmin-function-alignmnetJan Hubicka1-1/+17
-falign-functions is ignored in cold code, since it is an optimization intended to improve instruction prefetch. In some case it is necessary to force alignment for all functions, so this patch adds -fmin-function-alignment for this purpose. gcc/ChangeLog: PR middle-end/88345 * common.opt: (flimit-function-alignment): Reorder alphabeticaly (fmin-function-alignment): New parameter. * doc/invoke.texi: (-fmin-function-alignment): Document. (-falign-functions,-falign-loops,-falign-labels): Mention that aglinments are ignored in cold code. * varasm.cc (assemble_start_function): Handle min-function-alignment.
2024-01-24MIPS: Accept arguments for -mexplicit-relocsYunQiang Su1-0/+16
GAS introduced explicit relocs since 2001, and %pcrel_hi/low were introduced in 2014. In future, we may introduce more. Let's convert -mexplicit-relocs option, and accpet options: none, base, pcrel. We also update gcc/configure.ac to set the value to option the gas support when GCC itself is built. gcc * configure.ac: Detect the explicit relocs support for mips, and define C macro MIPS_EXPLICIT_RELOCS. * config.in: Regenerated. * configure: Regenerated. * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs. * config/mips/mips-opts.h: Define enum mips_explicit_relocs. * config/mips/mips.cc(mips_set_compression_mode): Sorry if !TARGET_EXPLICIT_RELOCS instead of just set it. * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs. * config/mips/mips.opt: Introduce -mexplicit-relocs= option and define -m(no-)explicit-relocs as aliases.
2024-01-23LoongArch: doc: Add attribute descriptions defined in the target-supports.exp.chenxiaolong1-0/+20
gcc/ChangeLog: * doc/sourcebuild.texi: Add attributes for keywords.
2024-01-23Correct lists of options enabled by -Wall and -Wextra [PR90463]Sandra Loosemore1-29/+50
gcc/ChangeLog PR c++/90463 * doc/invoke.texi (Warning Options): Correct lists of options enabled by -Wall and -Wextra by checking against common.opt and c-family/c.opt.
2024-01-21Make the manual clearer about what options -Wunused enables [PR90464]Sandra Loosemore1-10/+18
gcc/ChangeLog PR c++/90464 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter isn't enabled by -Wunused unless -Wextra is provided, and that -Wunused does enable -Wunused-const-variable=1 for C. Clarify that -Wunused doesn't enable -Wunused-* options documented as behaving otherwise, and list them explicitly.
2024-01-21Clean up examples for -Wdangling-pointer [PR109708]Sandra Loosemore1-22/+34
gcc/ChangeLog PR c/109708 * doc/invoke.texi (Warning Options): Fix broken example and clean up/reorganize the others. Also describe what the short-form options mean.
2024-01-20Correct documentation for -Warray-parameter [PR102998]Sandra Loosemore1-8/+16
gcc/ChangeLog PR c/102998 * doc/invoke.texi (Option Summary): Add -Warray-parameter. (Warning Options): Correct/edit discussion of -Warray-parameter to make the first example less confusing, and fill in missing info.
2024-01-19RISC-V: Documnet the list of supported extensionsKito Cheng1-0/+461
Try to list all supported extensions: name, version and few description for each extension. v2 changes: - Fix several typo. - Add expantion info for vector crypto extensions. - Drop zvl8192b, zvl16384b, zvl32768b and zvl65536b. - Aadd zicntr and zihpm gcc/ChangeLog: * doc/invoke.texi (RISC-V Options): Add list of supported extensions.
2024-01-19RISC-V: Document the syntax of -marchKito Cheng1-0/+16
gcc/ChangeLog * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
2024-01-19More precise documentation for cleanup attribute [PR110029]Sandra Loosemore1-0/+5
gcc/ChangeLog PR c/110029 * doc/extend.texi (Common Variable Attributes): Explain what happens when multiple variables with cleanups are in the same scope.
2024-01-18Improve documentation of noinline and noipa attributes [PR108470]Sandra Loosemore1-7/+10
gcc/ChangeLog PR ipa/108470 * doc/extend.texi (Common Function Attributes): Document that noinline also disables some interprocedural optimizations and improve flow to the part about using inline asm instead to disable calls from being optimized away completely. Remove the sentence that says noipa is mainly for internal compiler testing.
2024-01-18Remove remnant of removed Cygwin options from invoke.texi [PR108521]Brian Inglis1-1/+1
The -mcygwin option for x86 Windows was removed in 2010 by commit 3edeb30d044a4852881c34229e618b34f95b0d9e, but this reference was overlooked. gcc/ChangeLog PR target/108521 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin from x86 Windows Options.
2024-01-18Restore documentation for const/volatile functions [PR107942]Sandra Loosemore1-2/+35
In r5-7698-g8648c55f3b703a I accidentally removed the documentation of GCC's special interpretation of const/volatile qualifiers on functions from the function attributes section, thinking this was just a bit-rotten leftover from old versions of GCC. PR107942 points out that this functionality is still present even though the docs are now gone. I decided this material didn't really belong in the function attributes discussion, but a new subsection in the general list of GCC extensions to the C language. And I agree with the comment in the issue that we shouldn't really recommend this usage any more. gcc/ChangeLog PR c/107942 * doc/extend.texi (C Extensions): Add new section to menu. (Function Attributes): Move dangling index entries to.... (Const and Volatile Functions): New section.
2024-01-18Document negative forms of -Wtsan and -Wxor-used-as-pow [PR110847]Sandra Loosemore1-11/+11
These warnings are enabled by default, thus the manual should document the -no form instead of the positive form. gcc/ChangeLog PR middle-end/110847 * doc/invoke.texi (Option Summary): Document negative forms of -Wtsan and -Wxor-used-as-pow. (Warning Options): Likewise.
2024-01-18Re-alphabetize attribute tables in extend.texi.Sandra Loosemore1-393/+396
These sections used to be alphabetized, but when I was working on the fix for PR111659 I noticed documentation for some newer attributes had been inserted at random places in the tables instead of maintaining alphabetical order. There's no change to content here, just moving blocks of text around. gcc/ChangeLog * doc/extend.texi (Common Function Attributes): Re-alphabetize the table. (Common Variable Attributes): Likewise. (Common Type Attributes): Likewise.
2024-01-17Clean up documentation for -Wstrict-flex-arrays [PR111659]Sandra Loosemore2-34/+47
gcc/ChangeLog PR middle-end/111659 * doc/extend.texi (Common Variable Attributes): Fix long lines in documentation of strict_flex_array + other minor copy-editing. Add a cross-reference to -Wstrict-flex-arrays. * doc/invoke.texi (Option Summary): Fix whitespace in tables before -fstrict-flex-arrays and -Wstrict-flex-arrays. (C Dialect Options): Combine the docs for the two -fstrict-flex-arrays forms into a single entry. Note this option is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays. (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only. Minor copy-editing. Add cross references to the strict_flex_array attribute and -fstrict-flex-arrays option. Add note that this option depends on -ftree-vrp.
2024-01-17Move docs for -Wuse-after-free and -Wuseless-cast [PR111693]Sandra Loosemore1-79/+79
These options were categorized as C++ options, but they apply to all C-family languages. gcc/ChangeLog PR c/111693 * doc/invoke.texi (Option Summary): Move -Wuseless-cast from C++ Language Options to Warning Options. Add entry for -Wuse-after-free. (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast from here.... (Warning Options): ...to here. Minor copy-editing to fix typo and grammar.
2024-01-17Tidy documentation for BPF builtins [PR112973]Sandra Loosemore1-14/+24
gcc/Changelog PR target/112973 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and give the section a light copy-editing pass.
2024-01-16AArch64: Add -mcpu=cobalt-100Wilco Dijkstra1-1/+1
Add support for -mcpu=cobalt-100 (Neoverse N2 with a different implementer ID). gcc/ChangeLog: * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU. * config/aarch64/aarch64-tune.md: Regenerated. * doc/invoke.texi (-mcpu): Add cobalt-100 core.
2024-01-16AVR: Add AVR16EB, AVR16EA and AVR32EA devices.Georg-Johann Lay1-1/+1
gcc/ * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32) (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add. * doc/avr-mmcu.texi: Regenerate.
2024-01-15AVR: Document option -mskip-bug.Georg-Johann Lay1-4/+10
gcc/ * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
2024-01-14AVR: Support .rodata in Flash for AVR64* and AVR128* Devices.Georg-Johann Lay1-2/+38
These devices see a 32 KiB block of their program memory (flash) in the RAM address space. This can be used to support .rodata in flash provided Binutils support PR31124 (Add new emulations which locate .rodata in flash). This patch does the following: * configure checks availability of Binutils PR31124. * Add new command line options -mrodata-in-ram and -mflmap. While -flmap is for internal usage (communicate hardware properties from device-specs to the compiler proper), -mrodata-in-ram is a user space option that allows to return to the current rodata-in-ram layout. * Adjust gen-avr-mmcu-specs.cc so that device-specs are generated that sanity check options, and that translate -m[no-]rodata-in-ram to its emulation. * Objects in .rodata don't drag __do_copy_data. * Document new options and built-in macros. PR target/112944 gcc/ * configure.ac [target=avr]: Check availability of emulations avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP. * configure: Regenerate. * config.in: Regenerate. * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram, __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__. * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options. * config/avr/avr-arch.h (enum avr_device_specific_features): Add AVR_ISA_FLMAP. * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag AVR_ISA_FLMAP. * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars. (avr_set_core_architecture): Set avr_arch_index. (have_avrxmega2_flmap, have_avrxmega4_flmap) (have_avrxmega3_rodata_in_flash): Set new static const bool according to configure results. (avr_rodata_in_flash_p): New function using them. (avr_asm_init_sections): Let readonly_data_section->unnamed.callback track avr_need_copy_data_p only if not avr_rodata_in_flash_p(). (avr_asm_named_section): Track avr_has_rodata_p. (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p and not avr_rodata_in_flash_p (). * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram). (LINK_SPEC): Add %(link_rodata_in_ram). (LINK_ARCH_SPEC): Remove. * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash) (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static const bool according to configure results. (diagnose_mrodata_in_ram): New function. (print_mcu): Generate specs with the following changes: <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't need to extend avr/specs.h each time we add a new bell or whistle. <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose -m[no-]rodata-in-ram. <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1. <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies. <*cpp>: Add %(cpp_rodata_in_ram). <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as requested. <*self_spec>: Add -mflmap or %<mflmap as needed. gcc/testsuite/ * gcc.target/avr/torture/pr112944-flmap-0.c: New test. * gcc.target/avr/torture/pr112944-flmap-1.c: New test.
2024-01-12AVR: Documentation: Web-Link an example ld-Script for Address-Space __flashN.Georg-Johann Lay1-1/+3
gcc/ * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats): Add web-link to the avr-gcc wiki.
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