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2025-03-07x86: Improve documentation for -msse4 [PR116708]Sandra Loosemore1-0/+5
gcc/ChangeLog PR target/116708 * doc/invoke.texi (x86 Options): Clarify how -msse4 and -mno-sse4 interact with other SSE options.
2025-03-07docs: Attempt to clarify complex literal suffixes [PR112960]Jakub Jelinek1-11/+16
This attempts to clarify Complex literal suffixes in the documentation. 2025-03-07 Jakub Jelinek <jakub@redhat.com> PR c/112960 PR c/117029 * doc/extend.texi (Complex): Add I and J suffixes to the list of complex suffixes, adjust for all of those being part of ISO C2Y, clarify that for -fno-ext-numeric-literals none of those are recognized as GNU extensions and for C++14 i is considered UDL even for -fext-numeric-literals when <complex> is included.
2025-03-07middle-end: delay checking for alignment to load [PR118464]Tamar Christina1-1/+1
This fixes two PRs on Early break vectorization by delaying the safety checks to vectorizable_load when the VF, VMAT and vectype are all known. This patch does add two new restrictions: 1. On LOAD_LANES targets, where the buffer size is known, we reject non-power of two group sizes, as they are unaligned every other iteration and so may cross a page unwittingly. For those cases require partial masking support. 2. On LOAD_LANES targets when the buffer is unknown, we reject vectorization if we cannot peel for alignment, as the alignment requirement is quite large at GROUP_SIZE * vectype_size. This is unlikely to ever be beneficial so we don't support it for now. There are other steps documented inside the code itself so that the reasoning is next to the code. As a fall-back, when the alignment fails we require partial vector support. For VLA targets like SVE return element alignment as the desired vector alignment. This means that the loads are never misaligned and so annoying it won't ever need to peel. So what I think needs to happen in GCC 16 is that. 1. during vect_compute_data_ref_alignment we need to take the max of POLY_VALUE_MIN and vector_alignment. 2. vect_do_peeling define skip_vector when PFA for VLA, and in the guard add a check that ncopies * vectype does not exceed POLY_VALUE_MAX which we use as a proxy for pagesize. 3. Force LOOP_VINFO_USING_PARTIAL_VECTORS_P to be true in vect_determine_partial_vectors_and_peeling since the first iteration has to be partial. Require LOOP_VINFO_MUST_USE_PARTIAL_VECTORS_P otherwise we have to fail to vectorize. 4. Create a default mask to be used, so that vect_use_loop_mask_for_alignment_p becomes true and we generate the peeled check through loop control for partial loops. From what I can tell this won't work for LOOP_VINFO_FULLY_WITH_LENGTH_P since they don't have any peeling support at all in the compiler. That would need to be done independently from the above. In any case, not GCC 15 material so I've kept the WIP patches I have downstream. Bootstrapped Regtested on aarch64-none-linux-gnu, arm-none-linux-gnueabihf, x86_64-pc-linux-gnu -m32, -m64 and no issues. gcc/ChangeLog: PR tree-optimization/118464 PR tree-optimization/116855 * doc/invoke.texi (min-pagesize): Update docs with vectorizer use. * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Delay checks. (vect_compute_data_ref_alignment): Remove alignment checks and move to get_load_store_type, increase group access alignment. (vect_enhance_data_refs_alignment): Add note to comment needing investigating. (vect_analyze_data_refs_alignment): Likewise. (vect_supportable_dr_alignment): For group loads look at first DR. * tree-vect-stmts.cc (get_load_store_type): Perform safety checks for early break pfa. * tree-vectorizer.h (dr_set_safe_speculative_read_required, dr_safe_speculative_read_required, DR_SCALAR_KNOWN_BOUNDS): New. (need_peeling_for_alignment): Renamed to... (safe_speculative_read_required): .. This (class dr_vec_info): Add scalar_access_known_in_bounds. gcc/testsuite/ChangeLog: PR tree-optimization/118464 PR tree-optimization/116855 * gcc.dg/vect/bb-slp-pr65935.c: Update, it now vectorizes because the load type is relaxed later. * gcc.dg/vect/vect-early-break_121-pr114081.c: Update. * gcc.dg/vect/vect-early-break_22.c: Require partial vectors. * gcc.dg/vect/vect-early-break_128.c: Likewise. * gcc.dg/vect/vect-early-break_26.c: Likewise. * gcc.dg/vect/vect-early-break_43.c: Likewise. * gcc.dg/vect/vect-early-break_44.c: Likewise. * gcc.dg/vect/vect-early-break_2.c: Require load_lanes. * gcc.dg/vect/vect-early-break_7.c: Likewise. * gcc.dg/vect/vect-early-break_132-pr118464.c: New test. * gcc.dg/vect/vect-early-break_133_pfa1.c: New test. * gcc.dg/vect/vect-early-break_133_pfa11.c: New test. * gcc.dg/vect/vect-early-break_133_pfa10.c: New test. * gcc.dg/vect/vect-early-break_133_pfa2.c: New test. * gcc.dg/vect/vect-early-break_133_pfa3.c: New test. * gcc.dg/vect/vect-early-break_133_pfa4.c: New test. * gcc.dg/vect/vect-early-break_133_pfa5.c: New test. * gcc.dg/vect/vect-early-break_133_pfa6.c: New test. * gcc.dg/vect/vect-early-break_133_pfa7.c: New test. * gcc.dg/vect/vect-early-break_133_pfa8.c: New test. * gcc.dg/vect/vect-early-break_133_pfa9.c: New test. * gcc.dg/vect/vect-early-break_39.c: Update testcase for misalignment. * gcc.dg/vect/vect-early-break_18.c: Likewise. * gcc.dg/vect/vect-early-break_20.c: Likewise. * gcc.dg/vect/vect-early-break_21.c: Likewise. * gcc.dg/vect/vect-early-break_38.c: Likewise. * gcc.dg/vect/vect-early-break_6.c: Likewise. * gcc.dg/vect/vect-early-break_53.c: Likewise. * gcc.dg/vect/vect-early-break_56.c: Likewise. * gcc.dg/vect/vect-early-break_57.c: Likewise. * gcc.dg/vect/vect-early-break_81.c: Likewise.
2025-03-07Documentation: Improve -Wstringop-overflow documentation [PR 113515]Sandra Loosemore1-6/+29
This option can warn about things other than string and memory functions. Say so explicitly, and give an example. I also did some copy-editing of the text and added some paragraph breaks. gcc/ChangeLog PR c/113515 * doc/invoke.texi (Warning Options): Improve -Wstringop-overflow documentation.
2025-03-06AArch64: Enable early scheduling for -O3 and higher (PR118351)Wilco Dijkstra1-1/+3
Enable the early scheduler on AArch64 for O3/Ofast. This means GCC15 benefits from much faster build times with -O2, but avoids the regressions in lbm which is very sensitive to minor scheduling changes due to long FMA chains. gcc: PR target/118351 PR other/38768 * common/config/aarch64/aarch64-common.cc: Enable early scheduling with -O3 and higher. * doc/invoke.texi (-fschedule-insns): Update comment.
2025-03-06Revert "ira: Add new hooks for callee-save vs spills [PR117477]"Richard Sandiford2-73/+10
This reverts commit e836d80374aa03a5ea5bd6cca00d826020c461da.
2025-03-06ira: Add new hooks for callee-save vs spills [PR117477]Richard Sandiford2-10/+73
Following on from the discussion in: https://gcc.gnu.org/pipermail/gcc-patches/2025-February/675256.html this patch removes TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE and replaces it with two hooks: one that controls the cost of using an extra callee-saved register and one that controls the cost of allocating a frame for the first spill. (The patch does not attempt to address the shrink-wrapping part of the thread above.) On AArch64, this is enough to fix PR117477, as verified by the new tests. The patch does not change the SPEC2017 scores significantly. (I saw a slight improvement in fotonik3d and roms, but I'm not convinced that the improvements are real.) The patch makes IRA use caller saves for gcc.target/aarch64/pr103350-1.c, which is a scan-dump correctness test that relies on not using caller saves. The decision to use caller saves looks appropriate, and saves an instruction, so I've just added -fno-caller-saves to the test options. The x86 parts were written by Honza. gcc/ PR rtl-optimization/117477 * config/aarch64/aarch64.cc (aarch64_count_saves): New function. (aarch64_count_above_hard_fp_saves, aarch64_callee_save_cost) (aarch64_frame_allocation_cost): Likewise. (TARGET_CALLEE_SAVE_COST): Define. (TARGET_FRAME_ALLOCATION_COST): Likewise. * config/i386/i386.cc (ix86_ira_callee_saved_register_cost_scale): Replace with... (ix86_callee_save_cost): ...this new hook. (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete. (TARGET_CALLEE_SAVE_COST): Define. * target.h (spill_cost_type, frame_cost_type): New enums. * target.def (callee_save_cost, frame_allocation_cost): New hooks. (ira_callee_saved_register_cost_scale): Delete. * doc/tm.texi.in (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete. (TARGET_CALLEE_SAVE_COST, TARGET_FRAME_ALLOCATION_COST): New hooks. * doc/tm.texi: Regenerate. * hard-reg-set.h (hard_reg_set_popcount): New function. * ira-color.cc (allocated_memory_p): New variable. (allocated_callee_save_regs): Likewise. (record_allocation): New function. (assign_hard_reg): Use targetm.frame_allocation_cost to model the cost of the first spill or first caller save. Use targetm.callee_save_cost to model the cost of using new callee-saved registers. Apply the exit rather than entry frequency to the cost of restoring a register or deallocating the frame. Update the new variables above. (improve_allocation): Use record_allocation. (color): Initialize allocated_callee_save_regs. (ira_color): Initialize allocated_memory_p. * targhooks.h (default_callee_save_cost): Declare. (default_frame_allocation_cost): Likewise. * targhooks.cc (default_callee_save_cost): New function. (default_frame_allocation_cost): Likewise. gcc/testsuite/ PR rtl-optimization/117477 * gcc.target/aarch64/callee_save_1.c: New test. * gcc.target/aarch64/callee_save_2.c: Likewise. * gcc.target/aarch64/callee_save_3.c: Likewise. * gcc.target/aarch64/pr103350-1.c: Add -fno-caller-saves. Co-authored-by: Jan Hubicka <hubicka@ucw.cz>
2025-03-04AVR: Add texi @subsubsection "AVR Optimization Options".Georg-Johann Lay1-82/+93
gcc/ * doc/invoke.texi (AVR Optimization Options): New @subsubsection for pure optimization options.
2025-03-04__builtin_bswapXX: improve docsOscar Gustafsson1-1/+1
gcc/ChangeLog: * doc/extend.texi: Improve example for __builtin_bswap16.
2025-03-01doc: Simplify description of *-*-freebsd*Gerald Pfeifer1-2/+1
gcc: PR target/69374 * doc/install.texi (Specific, *-*-freebsd*): Simplify description.
2025-02-27GCC: Documentation of -x optionJerry DeLisle1-1/+5
This change updates information about the -x option to clarify that it does not ensure standards compliance. Sparked by discussions in the following PR. PR fortran/108369 gcc/ChangeLog: * doc/invoke.texi: Add a note to clarify. Adjust some wording.
2025-02-26[testsuite] add x86 effective targetAlexandre Oliva1-0/+3
I got tired of repeating the conditional that recognizes ia32 or x86_64, and introduced 'x86' as a shorthand for that, adjusting all occurrences in target-supports.exp, to set an example. I found some patterns that recognized i?86* and x86_64*, but I took those as likely cut&pastos instead of trying to preserve those weirdnesses. for gcc/ChangeLog * doc/sourcebuild.texi: Add x86 effective target. for gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_x86): New. Replace all uses of i?86-*-* and x86_64-*-* in this file.
2025-02-26[testsuite] adjust expectations of x86 vect-simd-clone testsAlexandre Oliva1-0/+5
Some vect-simd-clone tests fail when targeting ancient x86 variants, because the expected transformations only take place with -msse4 or higher. So arrange for these tests to take an -msse4 option on x86, so that the expected vectorization takes place, but decay to a compile test if vect.exp would enable execution but the target doesn't have an sse4 runtime. This requires the new dg-do-if to override the action on a target while retaining the default action on others, instead of disabling the test. We can count on avx512f compile-time support for these tests, because vect_simd_clones requires that on x86, and that implies sse4 support, so we need not complicate the scan conditionals with tests for sse4, except on the last test. for gcc/ChangeLog * doc/sourcebuild.texi (dg-do-if): Document. for gcc/testsuite/ChangeLog * lib/target-supports-dg.exp (dg-do-if): New. * gcc.dg/vect/vect-simd-clone-16f.c: Use -msse4 on x86, and skip in case execution is enabled but the runtime isn't. * gcc.dg/vect/vect-simd-clone-17f.c: Likewise. * gcc.dg/vect/vect-simd-clone-18f.c: Likewise. * gcc.dg/vect/vect-simd-clone-20.c: Likewise, but only skip the scan test.
2025-02-25doc: update C++98 bootstrap noteJason Merrill1-1/+1
r10-11132 uses C++11 default member initializers, which breaks bootstrapping with a C++98 compiler. gcc/ChangeLog: * doc/install.texi: 10.5 won't bootstrap with C++98.
2025-02-20doc: Drop note for Binutils pre 2.24Gerald Pfeifer1-4/+0
Binutils 2.24 was released in 2013, so this is more than 11 years old. gcc: PR target/69374 * doc/install.texi (Specific, aarch64*-*-*): Drop note for Binutils pre 2.24.
2025-02-20invoke.texi: Fix typo in the file-cache-lines paramFilip Kastl1-1/+1
file-cache-lines param was documented as file-cache-files. This fixes the typo. gcc/ChangeLog: * doc/invoke.texi: Fix typo file-cache-files -> file-cache-lines. Signed-off-by: Filip Kastl <fkastl@suse.cz>
2025-02-18[PR middle-end/113525] Drop obsolete options from documentationJeff Law1-8/+0
The sibling and unshare passes were dropped as distinct passes 10+ years ago. Docs weren't ever updated. This just removes them; given their age I don't think we need to keep them around any longer. PR middle-end/113525 gcc/ * doc/invoke.texi (dump-rtl-sibling): Drop documentation for pass removed long ago. (dump-rtl-unshare): Likewise.
2025-02-18Fix description of file-cache-lines/file-cache-files paramsAndi Kleen1-10/+10
The file-cache-lines / file-cache-files tunables were documented in the wrong section. Fix that. Reported-by: Filip Kastl Comitted as obvious. gcc/ChangeLog: * doc/invoke.texi:
2025-02-17i386: Re-alias avx10.2 to 512 bit and deprecate -mno-avx10.2-[256,512]Haochen Jiang2-7/+6
As mentioned in avx10.1 option deprecate patch, based on the feedback we got, we would like to re-alias avx10.x to 512 bit. For -mno- options, also mentioned in the previous patch, it is confusing what it is disabling when it comes to avx10. So we will only provide -mno-avx10.x options from AVX10.2, disabling the whole AVX10.x. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_UNSET): Adjust macro. (OPTION_MASK_ISA2_AVX10_2_256_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_2_UNSET): New. (ix86_handle_option): Remove disable part for avx10.2-256. Rename avx10.2-512 switch case to avx10.2 and adjust disable part macro. * common/config/i386/i386-isas.h: Adjust avx10.2 and avx10.2-512. * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10.x-256 for -march=native. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Adjust avx10.2 and avx10.2-512. * config/i386/i386.opt: Reject Negative for mavx10.2-256. Alias mavx10.2-512 to mavx10.2. Reject Negative for mavx10.2-512. * doc/extend.texi: Adjust documentation. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-512-vminmaxbf16-2.c: Add missing avx10_2_512 check. * gcc.target/i386/avx10_2-512-vminmaxpd-2.c: Ditto. * gcc.target/i386/avx10_2-512-vminmaxph-2.c: Ditto. * gcc.target/i386/avx10_2-512-vminmaxps-2.c: Ditto. * gcc.target/i386/avx10-check.h: Change avx10.2 to avx10.2-256. * gcc.target/i386/avx10_2-bf16-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-cmp-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-fma-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-operations-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c: Ditto. * gcc.target/i386/avx10_2-builtin-1.c: Ditto. * gcc.target/i386/avx10_2-builtin-2.c: Ditto. * gcc.target/i386/avx10_2-comibf-1.c: Ditto. * gcc.target/i386/avx10_2-comibf-2.c: Ditto. * gcc.target/i386/avx10_2-comibf-3.c: Ditto. * gcc.target/i386/avx10_2-comibf-4.c: Ditto. * gcc.target/i386/avx10_2-compare-1.c: Ditto. * gcc.target/i386/avx10_2-compare-1b.c: Ditto. * gcc.target/i386/avx10_2-convert-1.c: Ditto. * gcc.target/i386/avx10_2-media-1.c: Ditto. * gcc.target/i386/avx10_2-minmax-1.c: Ditto. * gcc.target/i386/avx10_2-movrs-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-fast-math-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-fma-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-operations-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-smaxmin-1.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Ditto. * gcc.target/i386/avx10_2-rounding-2.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: Ditto. * gcc.target/i386/avx10_2-satcvt-1.c: Ditto. * gcc.target/i386/avx10_2-vaddbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcmpbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcomisbf16-1.c: Ditto. * gcc.target/i386/avx10_2-vcomisbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ps2phx-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbf162ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbf162iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvthf82ph-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtps2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttbf162ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttbf162iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2dqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2qqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2udqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttph2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttph2iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2dqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2qqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2udqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2uqqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttsd2sis-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttsd2usis-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttss2sis-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttss2usis-2.c: Ditto. * gcc.target/i386/avx10_2-vdivbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vdpphps-2.c: Ditto. * gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfpclassbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vgetexpbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vgetmantbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vmaxbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vminbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxpd-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxph-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxps-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxsd-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxsh-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxss-2.c: Ditto. * gcc.target/i386/avx10_2-vmovd-1.c: Ditto. * gcc.target/i386/avx10_2-vmovd-2.c: Ditto. * gcc.target/i386/avx10_2-vmovw-1.c: Ditto. * gcc.target/i386/avx10_2-vmovw-2.c: Ditto. * gcc.target/i386/avx10_2-vmpsadbw-2.c: Ditto. * gcc.target/i386/avx10_2-vmulbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbssd-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbssds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbsud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbsuds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbuud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbuuds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwsud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwsuds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwusd-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwusds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwuud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwuuds-2.c: Ditto. * gcc.target/i386/avx10_2-vrcpbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vreducebf16-2.c: Ditto. * gcc.target/i386/avx10_2-vrndscalebf16-2.c: Ditto. * gcc.target/i386/avx10_2-vrsqrtbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vscalefbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vsqrtbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vsubbf16-2.c: Ditto. * gcc.target/i386/funcspec-56.inc: Ditto. * gcc.target/i386/part-vect-vec_cmpbf.c: Ditto. * gcc.target/i386/pr117495.c: Ditto. * gcc.target/i386/sm4-avx10_2-1.c: Ditto. * gcc.target/i386/sm4-check.h: Ditto. * gcc.target/i386/vnniint16-auto-vectorize-3.c: Ditto. * gcc.target/i386/vnniint8-auto-vectorize-3.c: Ditto. * lib/target-supports.exp: Ditto.
2025-02-17i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the ↵Haochen Jiang2-11/+5
whole AVX10.1 Based on the feedback we got, we would like to re-alias avx10.x to 512 bit in the future. This leaves the current avx10.1 alias to 256 bit inconsistent. Since it has been there for GCC 14.1 and GCC 14.2, we decide to deprecate avx10.1 alias. The current proposal is not adding it back in the future, but it might change if necessary. For -mno- options, it is confusing what it is disabling when it comes to avx10. Since there is barely usage enabling AVX10 with 512 bit then disabling it, we will only provide -mno-avx10.x options in the future, disabling the whole AVX10.x. If someone really wants to disable 512 bit after enabling it, -mavx10.x-512 -mno-avx10.x -mavx10.x-256 is the only way to do that since we also do not want to break the usual expression on -m- options enabling everything mentioned. However, for avx10.1, since we deprecated avx10.1, there is no reason we should have -mno-avx10.1. Thus, we need to keep -mno-avx10.1-[256,512]. To avoid confusion, we will make -mno-avx10.1-512 to disable the whole AVX10.1 set to match the future -mno-avx10.x. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro. (OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_UNSET): New. (ix86_handle_option): Adjust AVX10.1 unset macro. * common/config/i386/i386-isas.h: Remove avx10.1. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Ditto. (ix86_option_override_internal): Adjust warning message. * config/i386/i386.opt: Remove mavx10.1. * doc/extend.texi: Remove avx10.1 and adjust doc. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10-check.h: Change to avx10.1-256. * gcc.target/i386/avx10_1-1.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-24.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/pr117946.c: Ditto. * gcc.target/i386/avx10_1-12.c: Adjust warning message. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-17.c: Adjust to no-avx10.1-512.
2025-02-16AVR: ad target/118764 - Let -mcvt set built-in macro __AVR_CVT__Georg-Johann Lay1-1/+5
gcc/ PR target/118764 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [TARGET_CVT]: Define __AVR_CVT__. * doc/invoke.texi (AVR Built-in Macros): Document __AVR_CVT__.
2025-02-15sarif-replay: display annotations as labelled ranges (§3.28.6) [PR118881]David Malcolm1-0/+5
In our .sarif output from e.g.: bad-binary-op.c: In function ‘test_4’: bad-binary-op.c:19:23: error: invalid operands to binary + (have ‘S’ {aka ‘struct s’} and ‘T’ {aka ‘struct t’}) 19 | return callee_4a () + callee_4b (); | ~~~~~~~~~~~~ ^ ~~~~~~~~~~~~ | | | | | T {aka struct t} | S {aka struct s} the labelled ranges are captured in the 'annotations' property of the 'location' object (§3.28.6). However sarif-replay emits just: In function 'test_4': bad-binary-op.c:19:23: error: invalid operands to binary + (have ‘S’ {aka ‘struct s’} and ‘T’ {aka ‘struct t’}) [error] 19 | return callee_4a () + callee_4b (); | ^ missing the labelled ranges. This patch adds support to sarif-replay for the 'annotations' property; with this patch we emit: In function 'test_4': bad-binary-op.c:19:23: error: invalid operands to binary + (have ‘S’ {aka ‘struct s’} and ‘T’ {aka ‘struct t’}) [error] 19 | return callee_4a () + callee_4b (); | ~~~~~~~~~~~~ ^ ~~~~~~~~~~~~ | | | | | T {aka struct t} | S {aka struct s} thus showing the labelled ranges. Doing so requires adding a new entrypoint to libgdiagnostics: diagnostic_physical_location_get_file Given that we haven't yet released a stable version and that sarif-replay is built together with libgdiagnostics I didn't bother updating the ABI version. gcc/ChangeLog: PR sarif-replay/118881 * doc/libgdiagnostics/topics/physical-locations.rst: Add diagnostic_physical_location_get_file. * libgdiagnostics++.h (physical_location::get_file): New wrapper. (diagnostic::add_location): Likewise. * libgdiagnostics.cc (diagnostic_manager::get_file_by_name): New. (diagnostic_physical_location::get_file): New. (diagnostic_physical_location_get_file): New. * libgdiagnostics.h (diagnostic_physical_location_get_file): New. * libgdiagnostics.map (diagnostic_physical_location_get_file): New. * libsarifreplay.cc (class annotation): New. (add_any_annotations): New. (sarif_replayer::handle_result_obj): Collect vectors of annotations in the calls to handle_location_object and apply them to "err" and to "note" as appropriate. (sarif_replayer::handle_thread_flow_location_object): Pass nullptr for annotations. (sarif_replayer::handle_location_object): Handle §3.28.6 "annotations" property, using it to populate a new "out_annotations" param. gcc/testsuite/ChangeLog: PR sarif-replay/118881 * sarif-replay.dg/2.1.0-valid/3.28.6-annotations-1.sarif: New test. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2025-02-14LoongArch: Adjust the cost of ADDRESS_REG_REG.Lulu Cheng1-1/+6
After changing this cost from 1 to 3, the performance of spec2006 401 473 416 465 482 can be improved by about 2% on LA664. Add option '-maddr-reg-reg-cost='. gcc/ChangeLog: * config/loongarch/genopts/loongarch.opt.in: Add option '-maddr-reg-reg-cost='. * config/loongarch/loongarch-def.cc (loongarch_rtx_cost_data::loongarch_rtx_cost_data): Initialize addr_reg_reg_cost to 3. * config/loongarch/loongarch-opts.cc (loongarch_target_option_override): If '-maddr-reg-reg-cost=' is not used, set it to the initial value. * config/loongarch/loongarch-tune.h (struct loongarch_rtx_cost_data): Add the member addr_reg_reg_cost and its assignment function to the structure loongarch_rtx_cost_data. * config/loongarch/loongarch.cc (loongarch_address_insns): Use la_addr_reg_reg_cost to set the cost of ADDRESS_REG_REG. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch.opt.urls: Regenerate. * doc/invoke.texi: Add description of '-maddr-reg-reg-cost='. gcc/testsuite/ChangeLog: * gcc.target/loongarch/const-double-zero-stx.c: Add '-maddr-reg-reg-cost=1'. * gcc.target/loongarch/stack-check-alloca-1.c: Likewise.
2025-02-13driver: -fhardened and -z lazy/-z norelro [PR117739]Marek Polacek1-2/+2
As the manual states, using "-fhardened -fstack-protector" will produce a warning because -fhardened wants to enable -fstack-protector-strong, but it can't since it's been overriden by the weaker -fstack-protector. -fhardened also attempts to enable -Wl,-z,relro,-z,now. By the same logic as above, "-fhardened -z norelro" or "-fhardened -z lazy" should produce the same warning. But we don't detect this combination, so this patch fixes it. I also renamed a variable to better reflect its purpose. Also don't check warn_hardened in process_command, since it's always true there. Also tweak wording in the manual as Jon Wakely suggested on IRC. PR driver/117739 gcc/ChangeLog: * doc/invoke.texi: Tweak wording for -Whardened. * gcc.cc (driver_handle_option): If -z lazy or -z norelro was specified, don't enable linker hardening. (process_command): Don't check warn_hardened. gcc/testsuite/ChangeLog: * c-c++-common/fhardened-16.c: New test. * c-c++-common/fhardened-17.c: New test. * c-c++-common/fhardened-18.c: New test. * c-c++-common/fhardened-19.c: New test. * c-c++-common/fhardened-20.c: New test. * c-c++-common/fhardened-21.c: New test. Reviewed-by: Jakub Jelinek <jakub@redhat.com>
2025-02-13tree, gengtype: Fix up GC issue with DECL_VALUE_EXPR [PR118790]Jakub Jelinek1-0/+5
The following testcase ICEs, because we have multiple levels of DECL_VALUE_EXPR VAR_DECLs: character(kind=1) id_string[1:.id_string] [value-expr: *id_string.55]; character(kind=1)[1:.id_string] * id_string.55 [value-expr: FRAME.107.id_string.55]; integer(kind=8) .id_string [value-expr: FRAME.107..id_string]; id_string is the user variable mentioned in BLOCK_VARS, it has DECL_VALUE_EXPR because it is a VLA, id_string.55 is a temporary created by gimplify_vla_decl as the address that points to the start of the VLA, what is normally used in the IL to access it. But as this artificial var is then used inside of a nested function, tree-nested.cc adds DECL_VALUE_EXPR to it too and moves the actual value into the FRAME.107 object's member. Now, remove_unused_locals removes id_string.55 (and various other VAR_DECLs) from cfun->local_decls, simply because it is not mentioned in the IL at all (neither is id_string itself, but that is kept in BLOCK_VARS as it has DECL_VALUE_EXPR). So, after this point, id_string.55 tree isn't referenced from anywhere but id_string's DECL_VALUE_EXPR. Next GC collection is triggered, and we are unlucky enough that in the value_expr_for_decl hash table (underlying hash map for DECL_VALUE_EXPR) the id_string.55 entry comes before the id_string entry. id_string is ggc_marked_p because it is referenced from BLOCK_VARS, but id_string.55 is not, as we don't mark DECL_VALUE_EXPR anywhere but by gt_cleare_cache on value_expr_for_decl. But gt_cleare_cache does two things, it calls clear_slots on entries where the key is not ggc_marked_p (so the id_string.55 mapping to FRAME.107.id_string.55 is lost and DECL_VALUE_EXPR (id_string.55) becomes NULL) but then later we see id_string entry, which is ggc_marked_p, so mark the whole hash table entry, which sets ggc_set_mark on id_string.55. But at this point its DECL_VALUE_EXPR is lost. Later during dwarf2out.cc we want to emit DW_AT_location for id_string, see it has DECL_VALUE_EXPR, so emit it as indirection of id_string.55 for which we again lookup DECL_VALUE_EXPR as it has DECL_HAS_VALUE_EXPR_P, but as it is NULL, we ICE, instead of finding it is a subobject of FRAME.107 for which we can find its stack location. Now, as can be seen in the PR, I've tried to tweak tree-ssa-live.cc so that it would keep id_string.55 in cfun->local_decls; that prohibits it from the DECL_VALUE_EXPR of it being GC until expansion, but then we shrink and free cfun->local_decls completely and so GC at that point still can throw it away. The following patch adds an extension to the GTY ((cache)) option, before calling the gt_cleare_cache on some hash table by specifying GTY ((cache ("somefn"))) it calls somefn on that hash table as well. And this extra hook can do any additional ggc_set_mark needed so that gt_cleare_cache preserves everything that is actually needed and throws away the rest. In order to make it just 2 pass rather than up to n passes - (if we had say id1 -> something, id2 -> x(id1), id3 -> x(id2), id4 -> x(id3), id5 -> x(id4) in the value_expr_for_decl hash table in that order (where idN are VAR_DECLs with DECL_HAS_VALUE_EXPR_P, id5 is the only one mentioned from outside and idN -> X stands for idN having DECL_VALUE_EXPR X, something for some arbitrary tree and x(idN) for some arbitrary tree which mentions idN variable) and in each pass just marked the to part of entries with ggc_marked_p base.from we'd need to repeat until we don't mark anything) the patch calls walk_tree on DECL_VALUE_EXPR of the marked trees and if it finds yet unmarked tree, it marks it and walks its DECL_VALUE_EXPR as well the same way. 2025-02-13 Jakub Jelinek <jakub@redhat.com> PR debug/118790 * gengtype.cc (write_roots): Remove cache variable, instead break from the loop on match and test o for NULL. If the cache option has non-empty string argument, call the specified function with v->name as argument before calling gt_cleare_cache on it. * tree.cc (gt_value_expr_mark_2, gt_value_expr_mark_1, gt_value_expr_mark): New functions. (value_expr_for_decl): Use GTY ((cache ("gt_value_expr_mark"))) rather than just GTY ((cache)). * doc/gty.texi (cache): Document optional argument of cache option. * gfortran.dg/gomp/pr118790.f90: New test.
2025-02-13doc: Update install.texi for GCC 15 on SolarisRainer Orth1-5/+8
Apart from minor updates, this patch is primarily an important caveat about binutils PR ld/32580, which has broken the binutils 2.44 ld on Solaris/x86. Tested on i386-pc-solaris2.11. 2025-02-11 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> gcc: * doc/install.texi (Specific, *-*-solaris2*): Updates for newer Solaris 11.4 SRUs and binutils 2.44.
2025-02-12AVR: target/118806 - Add -mno-call-main to tweak running main().Georg-Johann Lay1-2/+32
On devices with very limited resources, it may be desirable to run main in a more efficient way than provided by the startup code XCALL main XJMP exit from section .init9. In AVR-LibC v2.3, that code has been moved to libmcu.a, hence symbol __call_main can be satisfied so that the respective code is no more pulled in from that library. Instead, main can be run by putting it in section .init9. The patch adds attributes noreturn and section(".init9"), and sets __call_main=0 when it encounters main(). gcc/ PR target/118806 * config/avr/avr.opt (-mcall-main): New option and... (avropt_call_main): ...variable. * config/avr/avr.cc (avr_no_call_main_p): New variable. (avr_insert_attributes) [-mno-call-main, main]: Add attributes noreturn and section(".init9") to main. Set avr_no_call_main_p. (avr_file_end) [avr_no_call_main_p]: Define symbol __call_main. * doc/invoke.texi (AVR Options) <-mno-call-main>: Document. <-mnodevicelib>: Extend explanation.
2025-02-12Doc: Fix Texinfo warning in install.texiSandra Loosemore1-1/+1
For some time I've been seeing this Texinfo warning in my builds: .../gcc/doc/install.texi:2295: warning: `.' or `,' must follow @xref, not f Fixed thusly. gcc/ChangeLog * doc/install.texi: Add missing comma after @xref to fix warning.
2025-02-12Doc: Fix some typos and other nearby sloppy-writing issuesSandra Loosemore2-75/+74
I spotted some typos in the GCC manual. Since often these are a sign that the text was inserted without being proofread, I looked at the context and fixed some grammar/punctuation/wording issues as well. gcc/ChangeLog * doc/extend.texi: Fix a bunch of typos and other writing bugs. * doc/invoke.texi: Likewise.
2025-02-12Doc: Delete obsolete interface.texi chapter from GCC internals manualSandra Loosemore2-74/+1
The "Interfacing to GCC Output" chapter used to be part of the user-facing GCC documentation but ended up in the GCC internals manual when the two documents were separated in 2001. It hasn't been updated in any substantive way since then, and is now very bit-rotten. (PCC is no longer the "standard compiler" on any target, and the target-specific issues mentioned are for very old architectures.) Meanwhile, the GCC user documentation now has a chapter called "Binary Compatibility" that covers ABI issues in a generic way and also covers C++ compatibility. Let's keep that one and throw out the obsolete text that seems to predate the whole notion of an ABI. gcc/ChangeLog * Makefile.in (TEXI_GCCINT_FILES): Remove interface.texi. * doc/gccint.texi (Top): Remove menu entry for the "interface" node, and include of interface.texi. * doc/interface.texi: Delete.
2025-02-12c++: don't default -frange-for-ext-temps in -std=gnu++20 [PR188574]Jason Merrill1-3/+2
Since -frange-for-ext-temps has been causing trouble, let's not enable it by default in pre-C++23 GNU modes for GCC 15, and also allow disabling it in C++23 and up. PR c++/188574 gcc/c-family/ChangeLog: * c-opts.cc (c_common_post_options): Only enable -frange-for-ext-temps by default in C++23. gcc/ChangeLog: * doc/invoke.texi: Adjust -frange-for-ext-temps documentation. gcc/testsuite/ChangeLog: * g++.dg/cpp23/range-for3.C: Use -frange-for-ext-temps. * g++.dg/cpp23/range-for4.C: Adjust expected result. libgomp/ChangeLog: * testsuite/libgomp.c++/range-for-4.C: Adjust expected result.
2025-02-10[gcn] install.texi: Update for new ISA targets and their requirementsTobias Burnus1-4/+26
GCN now supports several additional ISA targets such that no longer all targets have a multilib by default; add a note about this, the generic targets and the required LLVM (and ROCm) versions. gcc/ChangeLog: * doc/install.texi (GCN): Update section about multilibs and required LLVM version.
2025-02-08ad target/118764: Fix a typo in doc/extend.texi.Georg-Johann Lay1-3/+3
gcc/ PR target/118764 * doc/invoke.texi (AVR Options): Fix typos.
2025-02-08Clarify that effective-targets 'exceptions' and 'exceptions_enabled' are ↵Thomas Schwinge1-3/+4
orthogonal In Subversion r268025 (Git commit 3f21b8e3f7be32dd2b3624a2ece12f84bed545bb) "Add dg-require-effective-target exceptions", effective-target 'exceptions' was added, which "says that AMD GCN does not support [exception handling]". In Subversion r279246 (Git commit a9046e9853024206bec092dd63e21e152cb5cbca) "MSP430: Add -fno-exceptions multilib", effective-target 'exceptions_enabled' was added "to check if the testing configuration supports exceptions". Testing "if exceptions are unsupported or disabled (e.g. by passing -fno-exceptions)" works as expected if exception handling is disabled at the front-end level ('-fno-exceptions'; the "exceptions are [...] disabled" case): exceptions_enabled2066068.cc: In function ‘void foo()’: exceptions_enabled2066068.cc:3:27: error: exception handling disabled, use ‘-fexceptions’ to enable However, effective-target 'exceptions_enabled' additionally assumes that "If exceptions aren't supported [by the target], then they're not enabled". This is not correct: it's not unlikely that, in presence of explicit/implicit '-fexceptions', exception handling code gets fully optimized away by the compiler, and therefore effective-target 'exceptions_enabled' test cases may PASS even for targets that don't support effective-target 'exceptions'; these two effective-targets are orthogonal concepts. (For completeness: code with trivial instances of C++ exception handling may translate into simple '__cxa_allocate_exception', '__cxa_throw' function calls without requiring any back end-level "exceptions magic", and then trigger unresolved symbols at link time, if these functions are not available.) This change only affects GCN, as that one currently is the only target declared as not supporting effective-target 'exceptions'. gcc/ * doc/sourcebuild.texi (Effective-Target Keywords): Clarify that effective-target 'exceptions' and 'exceptions_enabled' are orthogonal. gcc/testsuite/ * lib/gcc-dg.exp (gcc-dg-prune): Clarify effective-target 'exceptions_enabled'. * lib/target-supports.exp (check_effective_target_exceptions_enabled): Don't consider effective-target 'exceptions'. libstdc++-v3/ * testsuite/lib/prune.exp (libstdc++-dg-prune): Clarify effective-target 'exceptions_enabled'.
2025-02-07[gcn] Add gfx9-generic and generic-associated gfx*Tobias Burnus1-0/+53
This patch adds gfx9-generic, completing the gfx*-generic support. It also adds all gfx* devices that are part of any of the gfx*-generic, i.e. gfx902, gfx904, gfx909, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1101, gfx1102, gfx1150, gfx1151, gfx1152, and gfx1153. gcc/ChangeLog: * config/gcn/gcn-devices.def (GCN_DEVICE): Add gfx9-generic, gfx902, gfx904, gfx909, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1101, gfx1102, gfx1150, gfx1151, gfx1152, and gfx1153. Add a currently unused column linking, a specific ISA to a generic one (if it exists). * config/gcn/gcn-tables.opt: Regenerate * doc/invoke.texi (AMD GCN): Add the the new gfc... and the older gfx{10-3,11}-generic to -march= as 'experimental'.
2025-02-07ira: Add a target hook for callee-saved register cost scaleH.J. Lu2-0/+10
commit 3b9b8d6cfdf59337f4b7ce10ce92a98044b2657b Author: Surya Kumari Jangala <jskumari@linux.ibm.com> Date: Tue Jun 25 08:37:49 2024 -0500 ira: Scale save/restore costs of callee save registers with block frequency scales the cost of saving/restoring a callee-save hard register in epilogue and prologue with the entry block frequency, which, if not optimizing for size, is 10000, for all targets. As the result, callee-saved registers may not be used to preserve local variable values across calls on some targets, like x86. Add a target hook for the callee-saved register cost scale in epilogue and prologue used by IRA. The default version of this target hook returns 1 if optimizing for size, otherwise returns the entry block frequency. Add an x86 version of this target hook to restore the old behavior prior to the above commit. PR rtl-optimization/111673 PR rtl-optimization/115932 PR rtl-optimization/116028 PR rtl-optimization/117081 PR rtl-optimization/117082 PR rtl-optimization/118497 * ira-color.cc (assign_hard_reg): Call the target hook for the callee-saved register cost scale in epilogue and prologue. * target.def (ira_callee_saved_register_cost_scale): New target hook. * targhooks.cc (default_ira_callee_saved_register_cost_scale): New. * targhooks.h (default_ira_callee_saved_register_cost_scale): Likewise. * config/i386/i386.cc (ix86_ira_callee_saved_register_cost_scale): New. (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Likewise. * doc/tm.texi: Regenerated. * doc/tm.texi.in (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): New. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-02-06AVR: Add support for a Compact Vector Table (-mcvt).Georg-Johann Lay1-1/+18
Some AVR devices support a CVT: - Devices from the 0-series, 1-series, 2-series. - AVR16, AVR32, AVR64, AVR128 devices. The support is provided by means of a startup code file crt<mcu>-cvt.o from AVR-LibC v2.3 that can be linked instead of the traditional crt<mcu>.o. This patch adds a new command line option -mcvt that links that CVT startup code (or issues an error when the device doesn't support a CVT). PR target/118764 gcc/ * config/avr/avr.opt (-mcvt): New target option. * config/avr/avr-arch.h (AVR_CVT): New enum value. * config/avr/avr-mcus.def: Add AVR_CVT flag for devices that support it. * config/avr/avr.cc (avr_handle_isr_attribute) [TARGET_CVT]: Issue an error when a vector number larger that 3 is used. * config/avr/gen-avr-mmcu-specs.cc (McuInfo.have_cvt): New property. (print_mcu) <*avrlibc_startfile>: Use crt<mcu>-cvt.o depending on -mcvt (or issue an error when the device doesn't support a CVT). * doc/invoke.texi (AVR Options): Document -mcvt.
2025-02-04Fix file cache tunables documentationAndi Kleen1-0/+10
Document new params in invoke.texi. The auto tuning description was on the wrong tunable, move to lines. Comitted as obvious. gcc/ChangeLog: * doc/invoke.texi: Document file cache tunables. * params.opt: Move auto tuning description to lines.
2025-02-02PR modula2/117411 Request for documentation to include exception exampleGaius Mulley1-9/+153
This patch adds a new section to the gm2 documentation and new corresponding testcode to the regression testsuite. gcc/ChangeLog: PR modula2/117411 * doc/gm2.texi (Exception handling): New section. (The ISO system module): Add description of COFF_T. (Assembler language): Tidy up last sentance. gcc/testsuite/ChangeLog: PR modula2/117411 * gm2/iso/run/pass/except9.mod: New test. * gm2/iso/run/pass/lazyunique.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2025-01-30AVR: Provide built-ins for strlen where the string lives in some AS.Georg-Johann Lay1-0/+10
This patch adds built-in functions __builtin_avr_strlen_flash, __builtin_avr_strlen_flashx and __builtin_avr_strlen_memx. Purpose is that higher-level functions can use __builtin_constant_p on strlen without raising a diagnostic due to -Waddr-space-convert. gcc/ * config/avr/builtins.def (STRLEN_FLASH, STRLEN_FLASHX) (STRLEN_MEMX): New DEF_BUILTIN's. * config/avr/avr.cc (avr_ftype_strlen): New static function. (avr_builtin_supported_p): New built-ins are not for AVR_TINY. (avr_init_builtins) <strlen_flash_node, strlen_flashx_node, strlen_memx_node>: Provide new fntypes. (avr_fold_builtin) [AVR_BUILTIN_STRLEN_FLASH] [AVR_BUILTIN_STRLEN_FLASHX, AVR_BUILTIN_STRLEN_MEMX]: Fold if possible. * doc/extend.texi (AVR Built-in Functions): Document __builtin_avr_strlen_flash, __builtin_avr_strlen_flashx, __builtin_avr_strlen_memx. libgcc/ * config/avr/t-avr (LIB1ASMFUNCS): Add _strlen_memx. * config/avr/lib1funcs.S <L_strlen_memx, __strlen_memx>: Implement.
2025-01-30AVR: Only provide a built-in when it is available.Georg-Johann Lay1-8/+10
Some built-ins are not available for C++ since they are using named address-spaces or fixed-point types. gcc/ * config/avr/builtins.def (AVR_FIRST_C_ONLY_BUILTIN_ID): New macro. * config/avr/avr-protos.h (avr_builtin_supported_p): New. * config/avr/avr.cc (avr_builtin_supported_p): New function. (avr_init_builtins): Only provide a built-in when it is supported. * config/avr/avr-c.cc (avr_cpu_cpp_builtins): Only define the __BUILTIN_AVR_<NAME> build-in defines when the associated built-in function is supported. * doc/extend.texi (AVR Built-in Functions): Add a note that following built-ins are supported for only for GNU-C.
2025-01-29PR modula2/116073 invalid rtl sharing compiling FileSystem.mod caused by ext-dceGaius Mulley1-5/+9
The bug fixes to PR modula2/118010 and PR modula2/118183 uncovered a bug in the procedure interface to lseek which uses SYSTEM.COFF_T rather than SYSTEM.CSSIZE_T. This patch sets the default size for COFF_T to the same as CSSIZE_T. gcc/ChangeLog: PR modula2/118010 PR modula2/118183 PR modula2/116073 * doc/gm2.texi (-fm2-file-offset-bits=): Change the default size description to CSSIZE_T. Add COFF_T to the list of data types exported by SYSTEM.def. gcc/m2/ChangeLog: PR modula2/118010 PR modula2/118183 PR modula2/116073 * gm2-compiler/M2Options.mod (OffTBits): Assign to 0. * gm2-gcc/m2type.cc (build_m2_specific_size_type): Ensure that layout_type is called before returning c. (build_m2_offt_type_node): If GetFileOffsetBits returns 0 then use the type size of ssize_t. gcc/testsuite/ChangeLog: PR modula2/118010 PR modula2/118183 PR modula2/116073 * gm2/pim/run/pass/printtypesize.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2025-01-24aarch64: Add +cpa feature flagAndrew Carlotti1-1/+3
This doesn't enable anything within the compiler, but this allows the flag to be passed the assembler. There also doesn't appear to be a kernel cpuinfo name yet. gcc/ChangeLog: * config/aarch64/aarch64-arches.def (V9_5A): Add CPA. * config/aarch64/aarch64-option-extensions.def (CPA): New. * doc/invoke.texi: Document +cpa.
2025-01-24docs: Add +wfxt and +xs to armv9.2-aAndrew Carlotti1-1/+1
I missed that the documentation doesn't include armv8.7-a within armv9.2-a. gcc/ChangeLog: * doc/invoke.texi: Add +wfxt and +xs to armv9.2-a
2025-01-24aarch64: Add command line support for armv9.5-aAndrew Carlotti1-0/+1
gcc/ChangeLog: * config/aarch64/aarch64-arches.def (V9_5A): New. * doc/invoke.texi: Document armv9.5-a option. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/armv9p5.c: New test.
2025-01-23testsuite: Only run test if alarm is availableTorbjörn SVENSSON1-0/+3
Most baremetal toolchains will not have an implementation for alarm and sigaction as they are target specific. For arm-none-eabi with newlib, function signatures are exposed, but there is no implmentation and thus the test cases causes a undefined symbol link error. gcc/testsuite/ChangeLog: * gcc.dg/pr78185.c: Remove dg-do and replace with with dg-require-effective-target of signal and alarm. * gcc.dg/pr116906-1.c: Likewise. * gcc.dg/pr116906-2.c: Likewise. * gcc.dg/vect/pr101145inf.c: Use effective-target alarm. * gcc.dg/vect/pr101145inf_1.c: Likewise. * lib/target-supports.exp(check_effective_target_alarm): New. gcc/ChangeLog: * doc/sourcebuild.texi (Effective-Target Keywords): Document 'alarm'. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
2025-01-23c++: Fix mangling of lambdas in static data member initializers [PR107741]Nathaniel Shead1-0/+3
This fixes an issue where lambdas declared in the initializer of a static data member within the class body do not get a mangling scope of that variable; this results in mangled names that do not conform to the ABI spec. To do this, the patch splits up grokfield for this case specifically, allowing a declaration to be build and used in start_lambda_scope before parsing the initializer, so that record_lambda_scope works correctly. As a drive-by, this also fixes the issue of a static member not being visible within its own initializer. PR c++/107741 gcc/c-family/ChangeLog: * c-opts.cc (c_common_post_options): Bump ABI version. gcc/ChangeLog: * common.opt: Add -fabi-version=20. * doc/invoke.texi: Likewise. gcc/cp/ChangeLog: * cp-tree.h (start_initialized_static_member): Declare. (finish_initialized_static_member): Declare. * decl2.cc (start_initialized_static_member): New function. (finish_initialized_static_member): New function. * lambda.cc (record_lambda_scope): Support falling back to old ABI (maybe with warning). * parser.cc (cp_parser_member_declaration): Build decl early when parsing an initialized static data member. gcc/testsuite/ChangeLog: * g++.dg/abi/macro0.C: Bump ABI version. * g++.dg/abi/mangle74.C: Remove XFAILs. * g++.dg/other/fold1.C: Restore originally raised error. * g++.dg/abi/lambda-ctx2-19.C: New test. * g++.dg/abi/lambda-ctx2-19vs20.C: New test. * g++.dg/abi/lambda-ctx2-20.C: New test. * g++.dg/abi/lambda-ctx2.h: New test. * g++.dg/cpp0x/static-member-init-1.C: New test. Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com>
2025-01-21LoongArch: Implement target pragma.Lulu Cheng1-0/+13
The target pragmas defined correspond to the target function attributes. This implementation is derived from AArch64. gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_reset_previous_fndecl): Add function declaration. (loongarch_save_restore_target_globals): Likewise. (loongarch_register_pragmas): Likewise. * config/loongarch/loongarch-target-attr.cc (loongarch_option_valid_attribute_p): Optimize the processing of attributes. (loongarch_pragma_target_parse): New functions. (loongarch_register_pragmas): Likewise. * config/loongarch/loongarch.cc (loongarch_reset_previous_fndecl): New functions. (loongarch_set_current_function): When the old_tree is the same as the new_tree, the rules for using registers, etc., are set according to the option values to ensure that the pragma can be processed correctly. * config/loongarch/loongarch.h (REGISTER_TARGET_PRAGMAS): Define macro. * doc/extend.texi: Supplemental Documentation. gcc/testsuite/ChangeLog: * gcc.target/loongarch/arch-func-attr-1.c: Add '#pragma'. * gcc.target/loongarch/cmodel-func-attr-1.c: Likewise. * gcc.target/loongarch/lasx-func-attr-1.c: Likewise. * gcc.target/loongarch/lsx-func-attr-1.c: Likewise. * gcc.target/loongarch/strict_align-func-attr-1.c: Likewise. * gcc.target/loongarch/strict_align-func-attr-2.c: Likewise. * gcc.target/loongarch/vector-func-attr-1.c: Likewise. * gcc.target/loongarch/arch-pragma-attr-1.c: Likewise. * gcc.target/loongarch/cmodel-pragma-attr-1.c: New test. * gcc.target/loongarch/lasx-pragma-attr-1.c: New test. * gcc.target/loongarch/lasx-pragma-attr-2.c: New test. * gcc.target/loongarch/lsx-pragma-attr-1.c: New test. * gcc.target/loongarch/lsx-pragma-attr-2.c: New test. * gcc.target/loongarch/strict_align-pragma-attr-1.c: New test. * gcc.target/loongarch/strict_align-pragma-attr-2.c: New test. * gcc.target/loongarch/vector-pragma-attr-1.c: New test. * gcc.target/loongarch/pragma-push-pop.c: New test.
2025-01-21LoongArch: Implement target attribute.Lulu Cheng1-0/+75
Add function attributes support for LoongArch. Currently, the following items are supported: __attribute__ ((target ("{no-}strict-align"))) __attribute__ ((target ("cmodel="))) __attribute__ ((target ("arch="))) __attribute__ ((target ("tune="))) __attribute__ ((target ("{no-}lsx"))) __attribute__ ((target ("{no-}lasx"))) This implementation is derived from AArch64. gcc/ChangeLog: * attr-urls.def: Regenerate. * config.gcc: Add loongarch-target-attr.o to extra_objs. * config/loongarch/loongarch-protos.h (loongarch_option_valid_attribute_p): Function declaration. (loongarch_option_override_internal): Likewise. * config/loongarch/loongarch.cc (loongarch_option_override_internal): Delete the modifications to target_option_default_node and target_option_current_node. (loongarch_set_current_function): Add annotation information. (loongarch_option_override): add assignment operations to target_option_default_node and target_option_current_node. (TARGET_OPTION_VALID_ATTRIBUTE_P): Define. * config/loongarch/t-loongarch: Add compilation of target file loongarch-target-attr.o. * doc/extend.texi: Add description information of LoongArch Function Attributes. * config/loongarch/loongarch-target-attr.cc: New file. gcc/testsuite/ChangeLog: * gcc.target/loongarch/arch-func-attr-1.c: New test. * gcc.target/loongarch/cmodel-func-attr-1.c: New test. * gcc.target/loongarch/lasx-func-attr-1.c: New test. * gcc.target/loongarch/lasx-func-attr-2.c: New test. * gcc.target/loongarch/lsx-func-attr-1.c: New test. * gcc.target/loongarch/lsx-func-attr-2.c: New test. * gcc.target/loongarch/strict_align-func-attr-1.c: New test. * gcc.target/loongarch/strict_align-func-attr-2.c: New test. * gcc.target/loongarch/vector-func-attr-1.c: New test. * gcc.target/loongarch/attr-check-error-message.c: New test.
2025-01-21Add warning for non-spec compliant FMV in Aarch64Alfie Richards1-1/+10
This patch adds a warning when FMV is used for Aarch64. The reasoning for this is the ACLE [1] spec for FMV has diverged significantly from the current implementation and we want to prevent potential future compatability issues. There is a patch for an ACLE compliant version of target_version and target_clone in progress but it won't make gcc-15. This has been bootstrap and regression tested for Aarch64. Is this okay for master and packport to gcc-14? [1] https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_process_target_version_attr): Add experimental warning. * config/aarch64/aarch64.opt: Add command line option to disable warning. * doc/invoke.texi: Add documentation for -W[no-]experimental-fmv-target. gcc/testsuite/ChangeLog: * g++.target/aarch64/mv-1.C: Add CLI flag. * g++.target/aarch64/mv-symbols1.C: Add CLI flag. * g++.target/aarch64/mv-symbols2.C: Add CLI flag. * g++.target/aarch64/mv-symbols3.C: Add CLI flag. * g++.target/aarch64/mv-symbols4.C: Add CLI flag. * g++.target/aarch64/mv-symbols5.C: Add CLI flag. * g++.target/aarch64/mv-warning1.C: New test. * g++.target/aarch64/mvc-symbols1.C: Add CLI flag. * g++.target/aarch64/mvc-symbols2.C: Add CLI flag. * g++.target/aarch64/mvc-symbols3.C: Add CLI flag. * g++.target/aarch64/mvc-symbols4.C: Add CLI flag. * g++.target/aarch64/mv-pragma.C: Add CLI flag. * g++.target/aarch64/mvc-warning1.C: New test.
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