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2024-01-310From: Alexandre Oliva <oliva@adacore.com>Alexandre Oliva1-0/+29
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-16Add support for target_version attributeAndrew Carlotti1-0/+12
2023-12-15bitint: Introduce abi_limb_modeJakub Jelinek1-2/+2
2023-12-07strub: enable conditional supportAlexandre Oliva1-0/+6
2023-12-05Introduce strub: machine-independent stack scrubbingAlexandre Oliva1-0/+19
2023-12-05Allow targets to add USEs to asmsRichard Sandiford1-2/+3
2023-12-05Add a new target hook: TARGET_START_CALL_ARGSRichard Sandiford1-10/+43
2023-12-05Add a target hook for sibcall epiloguesRichard Sandiford1-0/+8
2023-12-05Allow prologues and epilogues to be inserted laterRichard Sandiford1-0/+19
2023-12-02Allow target attributes in non-gnu namespacesRichard Sandiford1-6/+27
2023-11-27aarch64: Use br instead of ret for eh_returnSzabolcs Nagy1-0/+12
2023-11-23gcc: Introduce -fhardenedMarek Polacek1-0/+5
2023-11-21Add register filter operand to define_register_constraintRichard Sandiford1-1/+2
2023-11-18Add TARGET_HAVE_LIBATOMICSebastian Huber1-0/+5
2023-11-18gcov: Remove TARGET_GCOV_TYPE_SIZE target hookSebastian Huber1-11/+0
2023-11-11mode-switching: Add a backprop hookRichard Sandiford1-0/+28
2023-11-11mode-switching: Add a target-configurable confluence operatorRichard Sandiford1-0/+16
2023-11-11mode-switching: Pass the set of live registers to the after hookRichard Sandiford1-1/+3
2023-11-11mode-switching: Pass set of live registers to the needed hookRichard Sandiford1-2/+3
2023-11-11mode-switching: Allow targets to set the mode for EH handlersRichard Sandiford1-0/+6
2023-11-11mode-switching: Tweak the macro/hook documentationRichard Sandiford1-27/+42
2023-10-07[APX EGPR] middle-end: Add index_reg_class with insn argument.Hongyu Wang1-0/+8
2023-10-07[APX EGPR] middle-end: Add insn argument to base_reg_classKong Lingling1-0/+18
2023-09-21rust: Reintroduce TARGET_RUST_OS_INFO hookIain Buclaw1-0/+5
2023-09-21rust: Reintroduce TARGET_RUST_CPU_INFO hookIain Buclaw1-0/+13
2023-09-21rust: Add skeleton support and documentation for targetrustm hooks.Iain Buclaw1-0/+8
2023-09-06Middle-end _BitInt support [PR102989]Jakub Jelinek1-0/+15
2023-08-31Darwin: homogenize spelling of macOSFrancois-Xavier Coudert1-1/+1
2023-08-23rtl: use rtx_code for gen_ccmp_first and gen_ccmp_nextRichard Earnshaw1-2/+2
2023-08-09targhooks: Extend legitimate_address_p with code_helper [PR110248]Kewen Lin1-5/+13
2023-05-30stor-layout, aarch64: Express SRA intrinsics with RTL codesKyrylo Tkachov1-1/+13
2023-04-28Add targetm.libm_function_max_errorJakub Jelinek1-0/+15
2023-04-01aarch64, builtins: Include PR registers in FUNCTION_ARG_REGNO_P etc. [PR109254]Jakub Jelinek1-2/+4
2023-03-23Remove TARGET_GEN_MEMSET_SCRATCH_RTX since it's not used anymore.liuhongt1-7/+0
2023-03-12middle-end: Implement preferred_div_as_shifts_over_mult [PR108583]Tamar Christina1-0/+6
2023-03-12middle-end: Revert can_special_div_by_const changes [PR108583]Tamar Christina1-14/+0
2023-03-03c++, v3: Emit fundamental tinfos for _Float16/decltype(0.0bf16) types on ia32...Jakub Jelinek1-0/+9
2023-02-23**/*.texi: Reorder index entriesArsen Arsenović1-2/+2
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2023-01-03Revert "Compute a table of DWARF register sizes at compile"Florian Weimer1-4/+3
2023-01-02Compute a table of DWARF register sizes at compileFlorian Weimer1-3/+4
2022-11-25OpenMP: Generate SIMD clones for functions with "declare target"Sandra Loosemore1-1/+1
2022-11-14middle-end: Support not decomposing specific divisions during vectorization.Tamar Christina1-0/+16
2022-11-14Revert "sphinx: remove texinfo files"Martin Liska1-0/+12436
2022-11-09sphinx: remove texinfo filesMartin Liska1-12436/+0
2022-10-29d: Make TARGET_D_MINFO_SECTION hooks in elfos.h the language default.Iain Buclaw1-6/+10
2022-10-28c: tree: target: C2x (...) function prototypes and va_start relaxationJoseph Myers1-1/+3
2022-10-07Introduce DWARF_VERSION_DEFAULT and redefine for VxWorksOlivier Hainque1-0/+6
2022-09-30Document -fexcess-precision=16 in tm.texiPalmer Dabbelt1-1/+1
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