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2018-08-17doc: Use @ref, not @xref, in the middle of a sentenceSegher Boessenkool1-1/+1
2018-08-17C-SKY port: DocumentationSandra Loosemore1-0/+36
2018-08-02Revert "[ARM] Fix PR85434: spilling of stack protector guard's address on ARM"Thomas Preud'homme1-47/+8
2018-08-02[gen/AArch64] Generate helpers for substituting iterator values into pattern ...Richard Sandiford1-8/+117
2018-08-02[ARM] Fix PR85434: spilling of stack protector guard's address on ARMThomas Preud'homme1-8/+47
2018-07-31Add __builtin_speculation_safe_valueRichard Earnshaw1-0/+15
2018-07-12rtl.texi (REG_NONNEG): Remove decrement and branch until zero reference, add ...Paul Koning1-78/+62
2018-07-12Add IFN_COND_FMA functionsRichard Sandiford1-0/+17
2018-07-11md.texi (define_subst): Document how multiple occurrences of the same argumen...Paul Koning1-1/+5
2018-07-06Update internal documentation to describe that DONE and FAILPaul Koning1-0/+51
2018-07-03[16/n] PR85694: Add detection of averaging operationsRichard Sandiford1-0/+28
2018-06-27Convert pdp11 back end to CCmode.Paul Koning1-1/+9
2018-06-08Remove MPXMartin Liska1-6/+0
2018-05-29re PR target/85918 (Conversions to/from [unsigned] long long are not vectoriz...Jakub Jelinek1-0/+22
2018-05-25Add IFN_COND_{MUL,DIV,MOD,RDIV}Richard Sandiford1-0/+10
2018-05-25Add an "else" argument to IFN_COND_* functionsRichard Sandiford1-7/+16
2018-04-10cppopts.texi: Use "side effect" instead of side-effect.Martin Sebor1-5/+5
2018-01-13Add support for SVE scatter storesRichard Sandiford1-0/+29
2018-01-13Add support for SVE gather loadsRichard Sandiford1-0/+29
2018-01-13Add support for in-order addition reduction using SVE FADDARichard Sandiford1-0/+8
2018-01-13Add support for conditional reductions using SVE CLASTBRichard Sandiford1-0/+9
2018-01-13Add support for vectorising live-out values using SVE LASTBRichard Sandiford1-0/+8
2018-01-13Add support for reductions in fully-masked loopsRichard Sandiford1-0/+36
2018-01-13Add support for fully-predicated loopsRichard Sandiford1-0/+13
2018-01-13Add support for bitwise reductionsRichard Sandiford1-0/+11
2018-01-13SLP reductions with variable-length vectorsRichard Sandiford1-0/+8
2018-01-13Add support for masked load/store_lanesRichard Sandiford1-0/+36
2018-01-13[AArch64] Add SVE supportRichard Sandiford1-1/+7
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
2018-01-02Remove vec_perm_const optabRichard Sandiford1-14/+2
2017-12-16Add VEC_SERIES_EXPR and associated optabRichard Sandiford1-0/+13
2017-12-16Add VEC_DUPLICATE_EXPR and associated optabRichard Sandiford1-0/+11
2017-12-01Fix "central flowgraph" typo in machine desc docsJonathan Wakely1-1/+1
2017-11-13[Documentation] Fix latency in pipeline description exampleLuis Machado1-2/+2
2017-10-14target-insns.def: Add memory_blockage.Uros Bizjak1-0/+9
2017-09-04Turn HARD_REGNO_MODE_OK into a target hookRichard Sandiford1-2/+2
2017-09-01retire mem_signal_fence patternAlexander Monakov1-13/+0
2017-08-28optabs: ensure mem_thread_fence is a compiler barrierAlexander Monakov1-5/+11
2017-08-01re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b...Jakub Jelinek1-7/+14
2017-06-07Clarify define_insn documentationRichard Sandiford1-4/+21
2017-05-25md.texi (Machine Constraints): Update x86 family machine constraints section ...Sebastian Peryt1-3/+102
2017-05-17md.texi (Canonicalization of Instructions): Describe the canonical form of in...Uros Bizjak1-0/+19
2017-03-22re PR target/80123 (libgomp tests pr66199-2.c and pr66199-5.c fail with -mcpu...Aaron Sawdey1-0/+3
2017-03-21Use the more formal "cannot" instead of the informal "can't."Martin Sebor1-1/+1
2017-02-06RISC-V Port: gccPalmer Dabbelt1-0/+20
2017-01-10extend.texi: Tweak formatting to fix overfull hbox warnings.Sandra Loosemore1-5/+17
2017-01-03* doc/md.texi (Standard Names): Remove reference to Java frontend.Gerald Pfeifer1-2/+1
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
2016-10-27constraints.md (wH constraint): Add new constraints for allowing 32-bit integ...Michael Meissner1-0/+12
2016-10-25re PR target/78102 (GCC refuses to generate PCMPEQQ instruction for SSE4.1)Jakub Jelinek1-0/+16
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