riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-09	[committed] Fix minor bug in epiphany port	Jeff Law	1	-3/+3
2024-01-09	[committed] Fix minor bug on mn103 port	Richard Sandiford	1	-1/+3
2024-01-09	aarch64: Fix up GC of aarch64_simd_types [PR113270]	Jakub Jelinek	1	-1/+3
2024-01-09	ARC: Table-driven ashlsi implementation for better code/rtx_costs.	Roger Sayle	1	-32/+318
2024-01-09	RISC-V: Fix loop invariant check	Juzhe-Zhong	1	-1/+1
2024-01-09	i386: PR target/112992: Optimize mode for broadcast of constants.	Roger Sayle	1	-37/+87
2024-01-09	arm: Add support for Arm Cortex-M52 CPU.	Chung-Ju Wu	3	-3/+27
2024-01-09	LoongArch: Implement vec_init<M><N> where N is a LSX vector mode	Jiahao Xu	2	-7/+63
2024-01-09	RISC-V: Fix comments of segment load/store intrinsic [NFC]	Juzhe-Zhong	1	-2/+2
2024-01-09	RISC-V: Add crypto vector builtin function.	Feng Wang	8	-3/+633
2024-01-08	amdgcn: Add gfx1100 to new XNACK defaults in mkoffload	Tobias Burnus	1	-0/+1
2024-01-08	GCN: Add pre-initial support for gfx1100	Tobias Burnus	9	-36/+65
2024-01-08	AVR: PR target/112952: Fix attribute "address", "io" and "io_low"	Georg-Johann Lay	1	-51/+121
2024-01-08	amdgcn: Match new XNACK defaults in mkoffload	Andrew Stubbs	1	-2/+21
2024-01-08	amdgcn: Don't double-count AVGPRs	Andrew Stubbs	1	-29/+0
2024-01-08	i386: [APX] Add missing document for APX	Hongyu Wang	1	-1/+2
2024-01-08	RISC-V: Fix avl-type operand index error for ZVBC	Feng Wang	1	-2/+2
2024-01-07	i386: PR target/113231: Improved costs in Scalar-To-Vector (STV) pass.	Roger Sayle	1	-176/+188
2024-01-07	arm: Add Advanced SIMD cbranch implementation	Tamar Christina	1	-0/+49
2024-01-07	RISC-V: Use MAX instead of std::max [VSETVL PASS]	Juzhe-Zhong	1	-2/+2
2024-01-06	LoongArch: Improve lasx_xvpermi_q_<LASX:mode> insn pattern	Jiahao Xu	1	-1/+8
2024-01-06	RISC-V: Update MAX_SEW for available vsevl info[VSETVL PASS]	Juzhe-Zhong	1	-0/+17
2024-01-06	RISC-V: Teach liveness computation loop invariant shift amount	Juzhe-Zhong	1	-4/+27
2024-01-06	RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move	Juzhe-Zhong	3	-7/+26
2024-01-05	aarch64: Extend VECT_COMPARE_COSTS to !SVE [PR113104]	Richard Sandiford	2	-15/+5
2024-01-05	LoongArch: Fixed the problem of incorrect judgment of the immediate field of ...	Lulu Cheng	4	-83/+4
2024-01-05	aarch64: Further fix for throwing insns in ldp/stp pass [PR113217]	Alex Coplan	1	-0/+9
2024-01-05	asan: Align .LASANPC on function boundary	Ilya Leoshkevich	2	-2/+2
2024-01-05	Implement ASM_DECLARE_FUNCTION_NAME using ASM_OUTPUT_FUNCTION_LABEL	Ilya Leoshkevich	15	-38/+36
2024-01-05	RISC-V: Clean up unused variable [NFC]	Kito Cheng	1	-5/+0
2024-01-05	Revert "RISC-V: Add crypto vector builtin function."	Pan Li	8	-633/+3
2024-01-05	RISC-V: Add crypto vector builtin function.	Feng Wang	8	-3/+633
2024-01-05	RISC-V: Make liveness estimation be aware of .vi variant	Juzhe-Zhong	1	-7/+25
2024-01-04	Add generated .opt.urls files	David Malcolm	112	-0/+4578
2024-01-04	RISC-V: Nan-box the result of movhf on soft-fp16	Kuan-Lin Chen	2	-0/+42
2024-01-04	Revert "RISC-V: Make liveness estimation be aware of .vi variant"	Pan Li	1	-23/+7
2024-01-04	RISC-V: Make liveness estimation be aware of .vi variant	Juzhe-Zhong	1	-7/+23
2024-01-04	RISC-V: Fix misaligned stack offset for interrupt function	Kito Cheng	1	-1/+3
2024-01-04	RISC-V: Refine LMUL computation for MASK_LEN_LOAD/MASK_LEN_STORE IFN	Juzhe-Zhong	1	-14/+52
2024-01-04	LoongArch: Merge constant vector permuatation implementations.	Li Wei	1	-1092/+204
2024-01-04	MIPS: Add pattern insqisi_extended and inshisi_extended	YunQiang Su	1	-0/+24
2024-01-04	MIPS: Implement TARGET_INSN_COSTS	YunQiang Su	1	-0/+33
2024-01-04	MIPS: define_attr perf_ratio in mips.md	YunQiang Su	1	-0/+4
2024-01-04	RISC-V: Fix bug of earliest fusion for infinite loop[VSETVL PASS]	Juzhe-Zhong	2	-9/+36
2024-01-04	RISC-V: Fix indent	Juzhe-Zhong	1	-5/+5
2024-01-03	nvptx: Restructure code generating function map labels	Kwok Cheung Yeung	1	-2/+4
2024-01-03	Update copyright years.	Jakub Jelinek	1751	-1769/+1769
2024-01-03	LoongArch: Provide fmin/fmax RTL pattern for vectors	Xi Ruoyao	1	-0/+31
2024-01-03	RISC-V: Make liveness be aware of rgroup number of LENS[dynamic LMUL]	Juzhe-Zhong	1	-6/+28
2024-01-02	RISC-V: Use vector_length_operand instead of csr_operand in vsetvl patterns	Jun Sha (Joshua)	1	-4/+4