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AgeCommit message (Expand)AuthorFilesLines
2021-06-07Use moves to eliminate redundant test/compare instructionsJeff Law1-9/+44
2021-06-07Fix ICE of insn does not satisfy its constraints.liuhongt1-4/+4
2021-06-07Fix _mm256_zeroupper by representing the instructions as call_insns in which ...liuhongt8-143/+94
2021-06-06Reimplement LEAF_REG_REMAP macro for the SPARCEric Botcazou3-38/+37
2021-06-06aix: Use assemble_name to output BSS section name.David Edelsohn1-2/+8
2021-06-06i386: Clean up constraints.mdUros Bizjak1-6/+9
2021-06-05sh: Update unexpected empty split conditionKewen Lin1-1/+1
2021-06-05sparc: Update unexpected empty split conditionKewen Lin1-6/+6
2021-06-05or1k: Update unexpected empty split conditionKewen Lin1-1/+1
2021-06-05mips: Update unexpected empty split conditionKewen Lin1-3/+3
2021-06-05m68k: Update unexpected empty split conditionKewen Lin1-3/+3
2021-06-05Fix split conditions in H8/300 portJeff Law11-91/+91
2021-06-04i386: Convert a couple of predicates to use match_code RTXes.Uros Bizjak1-10/+7
2021-06-04i386: Add init pattern for V2HI vectors [PR100637]Uros Bizjak2-10/+117
2021-06-04arm: Update unexpected empty split conditionKewen Lin1-2/+2
2021-06-04i386: Update unexpected empty split conditionKewen Lin2-7/+7
2021-06-04x86: Fix ix86_expand_vector_init for V*TImode [PR100887]Jakub Jelinek1-3/+7
2021-06-04arc: Don't allow millicode thunks with reduced register set CPUs.Claudiu Zissulescu1-2/+4
2021-06-04rs6000: Disable mode promotion for pseudosHaochen Gui1-11/+0
2021-06-04rs6000: Expand PROMOTE_MODE marco in rs6000_promote_function_modeHaochen Gui1-1/+3
2021-06-04cris: Update unexpected empty split conditionKewen Lin1-1/+1
2021-06-03i386: Add insert and extract patterns for 4-byte vectors [PR100637]Uros Bizjak2-2/+180
2021-06-03Fix operand order to subf for p10 fusion.Aaron Sawdey2-41/+43
2021-06-03arm: Auto-vectorization for MVE: vabsChristophe Lyon4-9/+5
2021-06-03arc: Remove obsolete optionsClaudiu Zissulescu4-46/+7
2021-06-02arc: Remove define_insn_and_split *bbit_diKewen Lin1-28/+0
2021-06-02xtensa: Fix 2 warnings during xtensa build [PR100841]Jakub Jelinek1-3/+4
2021-06-02Make sure link reg save MEM has frame alias set.Pat Haugen1-8/+3
2021-06-02ARC: gcc driver default to hs38_linuxClaudiu Zissulescu1-1/+1
2021-06-02IBM Z: Remove match_scratch workaroundIlya Leoshkevich2-11/+5
2021-06-02Fix minor bugs in H8 port logical ops. Prepare for more compare/test removalJeff Law5-64/+55
2021-05-30rs6000: MMA test case ICEs using -O3 [PR99842]Peter Bergner1-1/+2
2021-05-29[committed][PR bootstrap/100730] Fix warnings in H8 target filesJeff Law1-7/+22
2021-05-28C-SKY: Define HAVE_sync_compare_and_swap*.Cooper Qu1-0/+10
2021-05-27i386: Remove unneeded binary operand fixup from expanders.Uros Bizjak2-160/+56
2021-05-27i386: Add XOP comparisons for 4- and 8-byte vectors [PR100637]Uros Bizjak2-2/+58
2021-05-27arm: Remove use of opts_set in arm_configure_build_target [PR100767]Richard Earnshaw3-17/+12
2021-05-27i386: Add uavg_ceil patterns for 4-byte vectors [PR100637]Uros Bizjak1-0/+41
2021-05-26i386: Autovectorize 4-byte vectorsUros Bizjak1-1/+4
2021-05-26arm: Auto-vectorization for MVE: vaddvChristophe Lyon3-14/+27
2021-05-26Remove useless register keywordsJakub Jelinek6-29/+31
2021-05-26arc: Remove useless register keywordJan-Benedict Glaw1-10/+10
2021-05-26C-SKY: Delete TARGET_CAN_CHANGE_MODE_CLASS, use defualt definition.Geng Qi1-16/+0
2021-05-26C-SKY: Support fldrd/fstrd for fpuv2 and fldr.64/fstr.64 for fpuv3.Geng Qi4-11/+16
2021-05-26C-SKY: Delete definition TARGET_PROMOTE_PROTOTYPES, just use the default defi...Geng Qi1-3/+0
2021-05-26C-SKY: Fix FAIL of gcc.dg/torture/stackalign/builtin-return-2.c.Geng Qi1-0/+4
2021-05-26C-SKY: Add instruction "ld.bs".Geng Qi1-0/+10
2021-05-25RISC-V: Pass -mno-relax to assemblerKito Cheng1-0/+1
2021-05-25C-SKY: Fix copyright of csky-modes.def.Cooper Qu1-19/+19
2021-05-25C-SKY: Amend copyrights of recently added files.Cooper Qu3-0/+58
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