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AgeCommit message (Expand)AuthorFilesLines
2023-10-20amdgcn: add -march=gfx1030 EXPERIMENTALAndrew Stubbs9-87/+183
2023-10-20SH: Fix PR 101177Oleg Endo1-1/+1
2023-10-20RISC-V: Rename some variables of vector_block_info[NFC]Juzhe-Zhong1-28/+29
2023-10-20RISC-V: Fix failed hoist in LICM of vmv.v.x instructionJuzhe-Zhong2-10/+31
2023-10-20RISC-V: Refactor and cleanup vsetvl passLehua Ding4-4636/+2953
2023-10-19aarch64: Generalise TFmode load/store pair patternsAlex Coplan2-11/+14
2023-10-19x86: Correct ISA enabled for clients since Arrow LakeHaochen Jiang2-8/+10
2023-10-19amdgcn: deprecate Fiji device and multilibAndrew Stubbs1-2/+6
2023-10-19LoongArch:Implement the new vector cost model framework.Jiahao Xu3-22/+181
2023-10-19LoongArch:Implement vec_widen standard names.Jiahao Xu4-17/+205
2023-10-19LoongArch:Implement avg and sad standard names.Jiahao Xu2-0/+156
2023-10-18pru: Implement TARGET_INSN_COSTDimitar Dimitrov1-0/+36
2023-10-18aarch64: Replace duplicated selftestsAndrew Carlotti1-12/+12
2023-10-18nvptx: Use fatal_error when -march= is missing not an assert [PR111093]Tobias Burnus1-2/+3
2023-10-18Darwin: Check as for .build_version support and use it if available.Iain Sandoe1-2/+32
2023-10-18AArch64: Rewrite simd move immediate patterns to new syntaxTamar Christina1-69/+47
2023-10-18LoongArch: Use fcmp.caf.s instead of movgr2cf for zeroing a fccXi Ruoyao1-1/+1
2023-10-18RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vxJuzhe-Zhong1-0/+85
2023-10-18Initial Panther Lake SupportHaochen Jiang4-44/+62
2023-10-18x86: Add m_CORE_HYBRID for hybrid clients tuningHaochen Jiang2-62/+52
2023-10-18Initial Clearwater Forest SupportHaochen Jiang4-2/+17
2023-10-18Support 32/64-bit vectorization for _Float16 fma related operations.liuhongt1-1/+151
2023-10-18RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832]Juzhe-Zhong1-6/+13
2023-10-17aarch64: Put LR save slot first in more casesRichard Sandiford1-1/+1
2023-10-17aarch64: Use vecs to store register save orderRichard Sandiford2-102/+110
2023-10-17LoongArch: Fix vec_initv32qiv16qi template to avoid ICE.Chenghui Pan1-1/+2
2023-10-17LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NOP.Lulu Cheng1-5/+0
2023-10-17RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjace...Juzhe-Zhong1-9/+84
2023-10-16i386: Allow -mlarge-data-threshold with -mcmodel=largeUros Bizjak2-4/+7
2023-10-16RISC-V: NFC: Move scalar block move expansion code into riscv-string.ccChristoph Müllner3-157/+158
2023-10-16ARC: Split asl dst,1,src into bset dst,0,src to implement 1<<x.Roger Sayle1-0/+16
2023-10-16s390: Fix expander popcountv8hi2_vxStefan Schulze Frielinghaus1-8/+8
2023-10-16RISC-V: Use VLS modes if the NITERS is known and smaller than VLS mode elements.Juzhe-Zhong1-4/+9
2023-10-16Support 32/64-bit vectorization for conversion between _Float16 and integer/f...liuhongt2-25/+151
2023-10-16Enable vectorization for V2HF/V4HF rounding operations and sqrt.liuhongt4-11/+284
2023-10-15RISC-V: Fix vsingle attributeJuzhe-Zhong1-1/+1
2023-10-14RISC-V: Remove redundant iterators.Juzhe-Zhong1-110/+0
2023-10-12RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal...Kito Cheng2-3/+7
2023-10-13RISC-V: Support FP lfloor/lfloorf auto vectorizationPan Li3-0/+23
2023-10-13RISC-V: Support FP lceil/lceilf auto vectorizationPan Li3-0/+23
2023-10-12PR111778, PowerPC: Do not depend on an undefined shiftMichael Meissner1-3/+26
2023-10-12AArch64: Fix Armv9-a warnings that get emitted whenever a ACLE header is used.Tamar Christina1-0/+1
2023-10-12RISC-V: Support FP lround/lroundf auto vectorizationPan Li3-0/+22
2023-10-12Support Intel USER_MSRHu, Lin112-1/+145
2023-10-12LoongArch: Adjust makefile dependency for loongarch headers.Yang Yujie2-4/+2
2023-10-12rs6000: Make 32 bit stack_protect support prefixed insn [PR111367]Kewen Lin1-46/+27
2023-10-12[APX] Support Intel APX PUSH2POP2Mo, Zewei2-15/+263
2023-10-12RISC-V: Support FP irintf auto vectorizationPan Li2-41/+42
2023-10-11RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the buildKito Cheng1-0/+6
2023-10-11RISC-V Adjust long unconditional branch sequenceJeff Law1-1/+1
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