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2018-11-13Do not allow -mabi=ms and -fsanitize={,kernel-}address (PR sanitizer/87930).Martin Liska1-0/+5
2018-11-13 Martin Liska <mliska@suse.cz> PR sanitizer/87930 * config/i386/i386.c (ix86_option_override_internal): Error about usage -mabi=ms and -fsanitize={,kernel-}address. 2018-11-13 Martin Liska <mliska@suse.cz> PR sanitizer/87930 * gcc.target/i386/pr87930.c: New test. From-SVN: r266073
2018-11-13[PATCH][GCC] Make DR_TARGET_ALIGNMENT compile time variableAndre Vieira1-3/+5
This patch enables targets to describe DR_TARGET_ALIGNMENT as a compile-time variable. It does so by turning the variable into a 'poly_uint64'. gcc/ChangeLog: 2018-11-13 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/aarch64/aarch64.c (aarch64_vectorize_preferred_vector_alignment): Change return type to poly_uint64. (aarch64_simd_vector_alignment_reachable): Adapt to preferred vector alignment being a poly int. * doc/tm.texi (TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): Change return type to poly_uint64. * target.def (default_preferred_vector_alignment): Likewise. * targhooks.c (default_preferred_vector_alignment): Likewise. * targhooks.h (default_preferred_vector_alignment): Likewise. * tree-vect-data-refs.c (vect_calculate_target_alignment): Likewise. (vect_compute_data_ref_alignment): Adapt to vector alignment being a poly int. (vect_update_misalignment_for_peel): Likewise. (vect_enhance_data_refs_alignment): Likewise. (vect_find_same_alignment_drs): Likewise. (vect_duplicate_ssa_name_ptr_info): Likewise. (vect_setup_realignment): Likewise. (vect_can_force_dr_alignment_p): Change alignment parameter type to poly_uint64. * tree-vect-loop-manip.c (get_misalign_in_elems): Learn to construct a mask with a compile time variable vector alignment. (vect_gen_prolog_loop_niters): Adapt to vector alignment being a poly int. (vect_do_peeling): Exit early if vector alignment is not constant. * tree-vect-stmts.c (ensure_base_align): Adapt to vector alignment being a poly int. (vectorizable_store): Likewise. (vectorizable_load): Likweise. * tree-vectorizer.h (struct dr_vec_info): Make target_alignment field a poly_uint64. (vect_known_alignment_in_bytes): Adapt to vector alignment being a poly int. (vect_can_force_dr_alignment_p): Change alignment parameter type to poly_uint64. From-SVN: r266072
2018-11-13[RS6000] Don't put large integer constants in TOC for -mcmodel=mediumAlan Modra1-2/+5
For -mcmodel=medium we can use toc-relative addressing to access constants placed in read-only data, which is better since they can be merged when in .rodata.cst8. * config/rs6000/linux64.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Exclude integer constants when -mcmodel=medium. From-SVN: r266069
2018-11-13[ARC] Add support for profiling in glibc.Claudiu Zissulescu3-9/+22
Use PROFILE_HOOK to add mcount library calls in each toolchain. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.h (FUNCTION_PROFILER): Redefine to empty. * config/arc/elf.h (PROFILE_HOOK): Define. * config/arc/linux.h (PROFILE_HOOK): Likewise. From-SVN: r266068
2018-11-13[ARC] Do not emit ZOL in the presence of text jump tables.Claudiu Zissulescu1-1/+11
Avoid emitting lp instruction when in its ZOL body we find a jump table data in text section. One of the reason is the jump tables size can be changed latter on, hence the total ZOL length may be wrongly computed. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (hwloop_optimize): Bailout when detecting a jump table data in the text section. From-SVN: r266067
2018-11-13[ARC] Update EH code.Claudiu Zissulescu4-8/+24
Our ABI says the blink is pushed first on stack followed by an unknown number of register saves, and finally by fp. Hence we cannot use the EH_RETURN_ADDRESS macro as the stack is not finalized at that moment. The alternative is to use the eh_return pattern and to initialize all the bits after register allocation when the stack layout is finalized. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_eh_return_address_location): Repurpose it to fit the eh_return pattern. * config/arc/arc.md (eh_return): Define. (VUNSPEC_ARC_EH_RETURN): Likewise. * config/arc/arc-protos.h (arc_eh_return_address_location): Match new implementation. * config/arc/arc.h (EH_RETURN_HANDLER_RTX): Remove it. testsuite/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/builtin_eh.c: New test. From-SVN: r266066
2018-11-13[ARC] Refurbish and improve prologue/epilogue functions.Claudiu Zissulescu5-441/+1054
Reimplement how prologue and epilogue is emitted to accomodate enter/leave instructions, as well as improving the size of the existing techinques. The following modifications are added: - millicode thunk calls can be now selected regardless of the optimization level. However they are enabled for size optimizations by default. Also, the millicode optimization is turned off when we compile for long jumps. - the compiler is able to use enter/leave instructions for prologue and epilogue. As these instructions are not ABI compatible we gurad them under a switch (i.e., -mcode-density-frame). When this option is on, the compiler will try emitting enter/leave instructions, if not, then millicode thunk calls (if enabled), and latter the regular push/pop instructions. - The prologue/epilogue is now optimized to use pointer walks, hence improving the chance to have push_s/pop_s instructions emitted. It also tries to combine the stack adjustments with load/store operations. gcc/ xxxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * common/config/arc/arc-common.c (arc_option_optimization_table): Millicode optimization is default on for size optimizations. * config/arc/arc-protos.h (arc_check_multi): New function. * config/arc/arc.c (RTX_OK_FOR_OFFSET_P): Rearange. (ENTER_LEAVE_START_REG): Define. (ENTER_LEAVE_END_REG): Likewise. (arc_override_options): Disable millicode when long calls option is on. (arc_frame_info): Change it from int to bool. (arc_compute_frame_size): Clean up. (arc_save_restore): Remove. (frame_save_reg): New function. (frame_restore_reg): Likewise. (arc_enter_leave_p): Likewise. (arc_save_callee_saves): Likewise. (arc_restore_callee_saves): Likewise. (arc_save_callee_enter): Likewise. (arc_restore_callee_leave): Likewise. (arc_save_callee_milli): Likewise. (arc_restore_callee_milli): Likewise. (arc_expand_prologue): Reimplement to emit enter/leave instructions. (arc_expand_epilogue): Likewise. (arc_check_multi): New function. * config/arc/arc.md (push_multi_fp): New pattern. (push_multi_fp_blink): Likewise. (pop_multi_fp): Likewise. (pop_multi_fp_blink): Likewise. (pop_multi_fp_ret): Likewise. (pop_multi_fp_blink_ret): Likewise. * config/arc/arc.opt (mmillicode): Update option. (mcode-density-frame): New option. * config/arc/predicates.md (push_multi_operand): New predicate. (pop_multi_operand): Likewise. * doc/invoke.texi (ARC): Update ARC options information. gcc/testsuite xxxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/firq-1.c: Update test. * gcc.target/arc/firq-3.c: Likewise. * gcc.target/arc/firq-4.c: Likewise. * gcc.target/arc/interrupt-6.c: Likewise. From-SVN: r266065
2018-11-13[ARC] Add peephole rules to combine store/loads into double store/loadsClaudiu Zissulescu3-0/+232
Simple peephole rules which combines multiple ld/st instructions into 64-bit load/store instructions. It only works for architectures which are having double load/store option on. gcc/ Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-protos.h (gen_operands_ldd_std): Add. * config/arc/arc.c (operands_ok_ldd_std): New function. (mem_ok_for_ldd_std): Likewise. (gen_operands_ldd_std): Likewise. * config/arc/arc.md: Add peephole2 rules for std/ldd. From-SVN: r266064
2018-11-13[RS6000] secondary_reload and find_replacementAlan Modra1-12/+4
This patch removes a call only necessary when using reload. It also corrects a PRE_DEC address offset. * config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Negate offset for PRE_DEC. (rs6000_secondary_reload_gpr): Don't call find_replacement. From-SVN: r266049
2018-11-13[RS6000] Comment fixesAlan Modra1-1/+1
* config/rs6000/rs6000.c (rs6000_emit_prologue): Comment fix. From-SVN: r266047
2018-11-13[RS6000] Rotate testcaseAlan Modra1-2/+2
The testcase exercises one of the rotate patterns. gcc/ * config/rs6000/predicates.md (logical_const_operand), (logical_operand): Correct comment. gcc/testsuite/ * gcc.target/powerpc/rotmask.c: New. From-SVN: r266046
2018-11-13[RS6000] Hide insn not needing to be publicAlan Modra1-1/+1
* config/rs6000/rs6000.md (addsi3_high): Prefix with '*'. From-SVN: r266045
2018-11-13[RS6000] Ignore "c", "l" and "h" for register preferenceAlan Modra1-13/+12
This catches a few places where move insn patterns don't slightly disparage CTR, LR and VRSAVE regs. Also fixes the doc for the rs6000 h constraint, and removes an r->cl alternative covered by r->h. * gcc/doc/md.texi (Machine Constraints): Correct rs6000 h constraint description. * config/rs6000/rs6000.md (movsi_internal1): Delete MT%0 case covered by alternative. (movcc_internal1): Ignore h for register preference. (mov<mode>_hardfloat64): Likewise. (mov<mode>_softfloat): Ignore c, l, h for register preference. From-SVN: r266044
2018-11-12[GCC, ARM] Enable armv8.5-a and add +sb and +predres for previous ARMv8-a in ARMSudakshina Das5-7/+61
This patch adds -march=armv8.5-a to the Arm backend. Armv8.5-A also adds two new security features: - Speculation Barrier instruction - Execution and Data Prediction Restriction Instructions These are made optional to all older Armv8-A versions. Thus we are adding two new options "+sb" and "+predres" to all older Armv8-A. These are passed on to the assembler and have no code generation effects and have already gone in the trunk of binutils. *** gcc/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/arm/arm-cpus.in (armv8_5, sb, predres): New features. (ARMv8_5a): New fgroup. (armv8.5-a): New arch. (armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a): New options sb and predres. * config/arm/arm-tables.opt: Regenerate. * config/arm/t-aprofile: Add matching rules for -march=armv8.5-a * config/arm/t-arm-elf (all_v8_archs): Add armv8.5-a. * config/arm/t-multilib (v8_5_a_simd_variants): New variable. Add matching rules for -march=armv8.5-a and extensions. * doc/invoke.texi (ARM options): Document -march=armv8.5-a. Add sb and predres to all armv8-a except armv8.5-a. *** gcc/testsuite/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * gcc.target/arm/multilib.exp: Add some -march=armv8.5-a combination tests. From-SVN: r266031
2018-11-12* config/mcore/mcore.h (WORD_REGISTER_OPERATIONS): Remove duplicate.Eric Botcazou1-2/+0
From-SVN: r266029
2018-11-12sse.md: Combine VFIXUPIMM* patternsWei Xiao1-36/+6
2018-11-12 Wei Xiao <wei3.xiao@intel.com> * config/i386/sse.md: Combine VFIXUPIMM* patterns (<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>): Update. (<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>): Update. (<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Remove. (avx512f_sfixupimm<mode>_maskz<round_saeonly_expand_name>): Update. (avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>): Update. (avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Remove. From-SVN: r266026
2018-11-12csky.md (*fpuv2_nmulsf3_1, [...]): Handle -frounding-math.Xianmiao Qu1-2/+2
2018-11-11 Xianmiao Qu <xianmiao_qu@c-sky.com> gcc/ * config/csky/csky.md (*fpuv2_nmulsf3_1, *fpuv2_nmuldf3_1): Handle -frounding-math. gcc/testsuite * gcc.target/csky/fnmul-1.c: New. * gcc.target/csky/fnmul-2.c: New. * gcc.target/csky/fnmul-3.c: New. * gcc.target/csky/fnmul-4.c: New. From-SVN: r266024
2018-11-11re PR target/87928 (ICE in ix86_compute_frame_layout, at ↵Uros Bizjak3-7/+2
config/i386/i386.c:11161 since r228607) PR target/87928 * config/i386/i386.h (STACK_BOUNDARY): Use TARGET_64BIT_MS_ABI instead of (TARGET_64BIT && ix86_abi == MS_ABI). * config/i386/darwin.h (STACK_BOUNDARY): Ditto. * config/i386/cygming.h (STACK_BOUNDARY): Remove. testsuite /Changelog: PR target/87928 * gcc.target/i386/pr87928.c: New test. From-SVN: r266016
2018-11-11csky-linux-elf.h (CC1_SPEC): Support -profile.Xianmiao Qu1-0/+1
2018-11-11 Xianmiao Qu <xianmiao_qu@c-sky.com> * config/csky/csky-linux-elf.h (CC1_SPEC): Support -profile. From-SVN: r266013
2018-11-11csky.h (ASM_PREFERRED_EH_DATA_FORMAT): Define.Xianmiao Qu1-0/+3
2018-11-11 Xianmiao Qu <xianmiao_qu@c-sky.com> * config/csky/csky.h (ASM_PREFERRED_EH_DATA_FORMAT): Define. From-SVN: r266012
2018-11-09re PR target/87221 (cannot build with -pie)Maya Rashish1-3/+9
PR target/87221 * config/netbsd-elf.h (NETBSD_STARTFILE_SPEC): Use crtbeginS.o for PIE. (NETBSD_ENDFILE_SPEC): Use crtendS.o for PIE. From-SVN: r265994
2018-11-09S/390: Allow relative addressing of literal pool entriesIlya Leoshkevich1-35/+80
r265490 allowed the compiler to choose in a more flexible way whether to use load or load-address-relative-long (LARL) instruction. When it chose LARL for literal pool references, the latter ones were rewritten by pass_s390_early_mach to use UNSPEC_LTREF, which assumes base register usage, which in turn is not compatible with LARL. The end result was an ICE because of unrecognizable insn. UNSPEC_LTREF and friends are necessary in order to communicate the dependency on the base register to pass_sched2. When relative addressing is used, no base register is necessary, so in such cases the rewrite must be avoided. gcc/ChangeLog: 2018-11-09 Ilya Leoshkevich <iii@linux.ibm.com> PR target/87762 * config/s390/s390.c (s390_safe_relative_long_p): New function. (annotate_constant_pool_refs): Skip insns which support relative addressing. (annotate_constant_pool_refs_1): New helper function. (find_constant_pool_ref): Skip insns which support relative addression. (find_constant_pool_ref_1): New helper function. (replace_constant_pool_ref): Skip insns which support relative addressing. (replace_constant_pool_ref_1): New helper function. (s390_mainpool_start): Adapt to the new signature. (s390_mainpool_finish): Likewise. (s390_chunkify_start): Likewise. (s390_chunkify_finish): Likewise. (pass_s390_early_mach::execute): Likewise. (s390_prologue_plus_offset): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. From-SVN: r265991
2018-11-09mips.c (mips_loongson_ext2_prefetch_cookie): Handle unused argument better.Jeff Law1-1/+3
* config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): Handle unused argument better. Add gcc_unreachable to silence warning. From-SVN: r265986
2018-11-09arm - minor cleanups for CPU alias supportRichard Earnshaw1-2/+1
A couple of very minor issues with the new support for CPU aliases. * config/arm/parsecpu.awk (/alias/): Tighten invisible alias matching criteria. Remove unused array initializer. From-SVN: r265978
2018-11-09xmmintrin.h (_mm_cvtss_si32): Fix incorrect constraints by introducing a new ↵Bill Schmidt1-10/+14
temporary. 2018-11-09 Bill Schmidt <wschmidt@linux.ibm.com> Jinsong Ji <jji@us.ibm.com> * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix incorrect constraints by introducing a new temporary. (_mm_cvtss_si64): Likewise. Co-Authored-By: Jinsong Ji <jji@us.ibm.com> From-SVN: r265975
2018-11-09Remove extra memory allocation of strings.Martin Liska1-20/+12
2018-11-09 Martin Liska <mliska@suse.cz> * config/aarch64/aarch64.c (aarch64_parse_arch): Do not copy string to a stack buffer. (aarch64_parse_cpu): Likewise. (aarch64_parse_tune): Likewise. From-SVN: r265966
2018-11-09or1k: gcc: initial support for openriscStafford Horne13-0/+3891
2018-11-09 Stafford Horne <shorne@gmail.com> Richard Henderson <rth@twiddle.net> Joel Sherrill <joel@rtems.org> * common/config/or1k/or1k-common.c: New file. * config/or1k/*: New. * config.gcc (or1k*-*-*): New. * configure.ac (or1k*-*-*): New test for openrisc tls. * configure: Regenerated. * doc/install.texi: Document OpenRISC triplets. * doc/invoke.texi: Document OpenRISC arguments. * doc/md.texi: Document OpenRISC. Co-Authored-By: Joel Sherrill <joel@rtems.org> Co-Authored-By: Richard Henderson <rth@twiddle.net> From-SVN: r265963
2018-11-09arm - use the new CPU alias option to simplify the list of CPUs.Richard Earnshaw5-174/+50
This patch simplifies the table of CPUs supported in GCC by making use of the new alias feature. Most of the changes are fairly straight-forward: - arm7tdmi and arm7tdmi-s are the same thing. - arm710t, arm720t and arm740t differ only in features external to the core - arm920 and arm920t are the same thing; arm922t and arm940t differ from arm920t only in features external to the core; ep9312 is an arm920t-derived core that we continue to recognize for legacy reasons. - arm10tdmi and arm1020t differ only in features external to the core. - arm9e, arm946te-s, arm966e-s and arm968e-s differ only in features external to the core. - arm10e, arm1020e and arm1022e differ only in features external to the core. The arm10e/arm1020e/arm1022e change is the only one which changes behaviour of the compiler slightly. Previously, and for no reason that I can remember, the scheduler for arm1020e/arm1022e was not used for arm10e: this was probably an oversight. The unification means that the same scheduler is now used for all three cores. * config/arm/arm-cpus.in (arm7tdmi): Add an alias for arm7tdmi-s. (arm7tdmi-s): Delete CPU. (arm710t): Add aliases for arm720t and arm740t. (arm720t, arm740t): Delete CPUs. (arm920t): Add aliases for arm920, arm922t and arm940t. (arm920, arm922t, arm940t): Delete CPUs. (arm10tdmi): Add alias for arm1020t. (arm1020t): Delete CPU. (arm9e): Add aliases for arm946e-s, arm966e-s and arm968e-s. (arm946e-s, arm966e-s, arm968e-s): Delete CPUs. (arm10e): Add aliases for arm1020e and arm1022e. (arm1020e, arm1022e): Delete CPU. * config/arm/arm.md (generic_sched): Remove entries that are now handled by aliases. (generic_vfp): Likewise. * config/arm/arm1020e.md: Simplify tuning selection based on alias changes. * config/arm/arm-tune.md: Regenerated. * config/arm/arm-tables.opt: Regenerated. From-SVN: r265960
2018-11-09large-addr-aware for biarch non-w64 mingw32Alexandre Oliva1-2/+17
for gcc/ChangeLog * config/i386/mingw32.h (LINK_SPEC_LARGE_ADDR_AWARE): Adjust for non-w64 x86_64 biarch. From-SVN: r265958
2018-11-09[PR87793] reject non-toplevel unspecs in debug loc exprs on x86Alexandre Oliva1-0/+12
Before revision 254025, we'd reject UNSPECs in debug loc exprs. TARGET_CONST_NOT_OK_FOR_DEBUG_P still rejects that by default, on all ports that override it, except for x86, that accepts @gotoff unspecs. We can indeed accept them in top-level expressions, but not as subexpressions: the assembler rejects the difference between two @gotoff symbols, for example. We could simplify such a difference and drop the @gotoffs, provided that the symbols are in the same section; we could also accept @gotoffs plus literal constants. However, accepting those but rejecting such combinations as subexpressions would be ugly, and most likely not worth the trouble: sym@gotoff+litconst hardly makes sense as a standalone expression, and the difference between @gotoffs should be avoided to begin with, as follows. Ideally, the debug loc exprs would use the symbolic data in REG_EQUIV/REG_EQUAL notes, or delegitimized addresses, instead of simplifying the difference between two legitimized addresses so that the occurrences of the GOT register cancel each other. That would require some more elaborate surgery in var-tracking and cselib than would be appropriate at this stage. for gcc/ChangeLog PR target/87793 * config/i386/i386.c (ix86_const_not_ok_for_debug_p): Reject non-toplevel UNSPEC. for gcc/testsuite/ChangeLog PR target/87793 * gcc.dg/pr87793.c: New. From-SVN: r265956
2018-11-09neon.md (div<mode>3): New pattern.Prathamesh Kulkarni1-0/+32
2018-11-09 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> * config/arm/neon.md (div<mode>3): New pattern. testsuite/ * gcc.target/arm/neon-vect-div-1.c: New test. * gcc.target/arm/neon-vect-div-2.c: Likewise. From-SVN: r265948
2018-11-09Add PTWRITE builtins for x86Andi Kleen9-2/+74
Add builtins/intrinsics for PTWRITE. PTWRITE is a new instruction on Intel Gemini Lake/ Goldmont Plus that allows to write values into the Processor Trace log. This allows very light weight instrumentation of programs. The intrinsics are compatible to icc. Automatically enabled for Goldmont Plus. gcc/: 2018-11-08 Andi Kleen <ak@linux.intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_PTWRITE_SET): New. (OPTION_MASK_ISA_PTWRITE_UNSET): New. (ix86_handle_option): Handle OPT_mptwrite. * config/i386/cpuid.h (bit_PTWRITE): Add. * config/i386/driver-i386.c (host_detect_local_cpu): Detect ptwrite. * config/i386/i386-builtin.def (BDESC): Add ptwrite32/64. * config/i386/i386-c.c (ix86_target_macros_internal): Define __PTWRITE__. * config/i386/i386.c (ix86_target_string): Handle ptwrite. (ix86_option_override_internal): Handle PTA_PTWRITE. (ix86_valid_target_attribute_inner_p): Define ptwrite. (def_builtin2): Force UINT64 to be 64bit only. * config/i386/i386.h (TARGET_PTWRITE): Add. (TARGET_PTWRITE_P): Add. (PTA_PTWRITE): Add. * config/i386/i386.md: Define ptwrite. * config/i386/i386.opt: Add -mptwrite. * config/i386/immintrin.h (_ptwrite64): Add. (_ptwrite32): Add * doc/extend.texi: Document __builtin_ia32_ptwrite*. * doc/invoke.texi: Document -mptwrite. gcc/testsuite/: 2018-11-08 Andi Kleen <ak@linux.intel.com> * gcc.target/i386/ptwrite1.c: New test. * gcc.target/i386/ptwrite2.c: New test. From-SVN: r265947
2018-11-08re PR c/87795 (Excessive alignment permitted for functions and labels)Paul Koning7-368/+531
* config/pdp11/constraints.md: Add "Z" series constraints for use with pre-dec and post-inc addressing. * config/pdp11/pdp11-protos.m (expand_block_move): Delete. (pdp11_expand_operands): Add int argument (word count). (pdp11_sp_frame_offset): Delete. (pdp11_cmp_length): New function. (pushpop_regeq): New function. * config/pdp11/pdp11.c (TARGET_STACK_PROTECT_RUNTIME_ENABLED_P): Add hook. (pdp11_expand_prologue, pdp11_expand_epilogue): Rewrite for new frame layout. (pdp11_initial_elimination_offset): Ditto. (pdp11_expand_operands): Add word count argument. Bugfixes. (output_move_multiple): Change how pointer adjustment is done. (pdp11_gen_int_label): Correct format. (output_ascii): Ditto. (pdp11_asm_output_var): Add code for DEC assembler case. (pdp11_asm_print_operand): Bugfix for CONST_DOUBLE holding integer value. (legitimate_const_double_p): Ditto. (pdp11_register_move_cost): Adjust for new register classes. (pdp11_regno_reg_class): Ditto. (expand_block_move): Delete. (pushpop_regeq): New function. (pdp11_legitimate_address_p): Bugfix in check for constant offset. (pdp11_sp_frame_offset): Delete. (pdp11_reg_save_size): New helper function for new frame layout. (output_addr_const_pdp11): Remove CONST_DOUBLE case. (pdp11_expand_shift): Bugfix in check for constant shift count. (pdp11_shift_length): Ditto. (pdp11_assemble_shift): Copy input to pdp11_expand_operands. (pdp11_cmp_length): New function. * config/pdp11/pdp11.h (TARGET_CPU_CPP_BUILTINS): Add macros for some compile options. (FIXED_REGISTERS): Remove HARD_FRAME_POINTER_REGNUM. (CALL_USED_REGISTERS): Ditto. (ELIMINABLE_REGS): Ditto. (REGISTER_NAMES): Ditto. (reg_class): Add classes NOTR0_REG through NOTSP_REG for use by Z constraints. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. Also remove HARD_FRAME_POINTER_REGNUM. (CPU_REG_CLASS): New macro. (CLASS_MAX_NREGS): Adjust for new register classes. (FUNCTION_PROFILER): Make no-op. (may_call_alloca): Remove unused declaration. (ASM_OUTPUT_ALIGN): Add workaround for PR87795. (ASM_OUTPUT_SKIP): Fix format. * config/pdp11/pdp11.md (unspecv): Add UNSPECV_MOVMEM. (HARD_FRAME_POINTER_REGNUM): Remove. (return): Delete. (*rts): Rename. Remove epilogue related checks. (cmpsi, cmpdi): New insn. (cbranch<mode>4): Change to apply to SI and DI modes as well. (mov<mode>): Change constraints to enforce that push/pop destination cannot use the same register as source. (*mov<mode><cc_cc>): Ditto. (movmemhi, movmemhi1, movmemhi_nocc): Change to expand block move at assembly output rather than as RTL expander. (zero_extendqihi2): Bugfix in check for same registers. (adddi3_nocc): Bugfix in check for constant operand. (addsi3_nocc): Ditto. (subdi3_nocc): Ditto. (subsi3_nocc): Ditto. (negdi2_nocc): Copy input to pdp11_expand_operands. (negsi2_nocc): Ditto. (bswap2_nocc): Ditto. * config/pdp11/pdp11.opt (mlra): Fix documentation. * config/pdp11/t-pdp11: Use -Os. From-SVN: r265932
2018-11-08arm - Add support for aliases of CPU namesRichard Earnshaw6-37/+80
This patch adds support for defining an alias for a CPU name that can then be used in conjunction with the -mcpu option in the same way that the primary name can be used. Aliases do not lead to a short-cut of the feature options; they are literally an alternative name for the core CPU. The new entry in arm-cpus.in allows a cpu definition to contain an alias statement, for example begin cpu strongarm alias strongarm110 !strongarm1100 !strongarm1110 ... end cpu strongarm each entry in the list represents another alias for the CPU. If the alias name starts with an exclamation mark, then it will match as for any other alias (sans the ! itself), but it will not be listed in any of the CPU hinting options (the intent is to make the alias essentially undocumented). In the above example, hints would be provided for strongarm and strongarm110, but not for strongarm1100 or strongarm1110. The advantage of using aliases in this way is that it allows us to reduce the number of duplicate table entries and identifier tags used inside the compiler itself. * config/arm/parsecpu.awk (/alias/): New parsing rule. (/begin cpu/): Check that the cpu name hasn't been previously defined. (gen_comm_data): Print out CPU alias tables. (check_cpu): Match aliases when checking the CPU name. * config/arm/arm-protos.h (cpu_alias): New structure. (cpu_option): Add entry for aliases. * config/arm/arm-cpus.in (strongarm): Add aliases for strongarm110 strongarm1100 and strongarm1110. (strongarm110, strongarm1100, strongarm1110): Delete CPU entries. (config/arm/arm-generic.md): Remove redundant references to strongarm110, strongarm1100 and strongarm1110. * common/config/arm/arm-common.c (arm_print_hint_for_cpu_option): Scan aliases for additional hints. (arm_parse_cpu_option_name): Also match a cpu name against the list of aliases. * config/arm/arm-tables.opt: Regenerated. * config/arm/arm-tune.md: Regenerated. From-SVN: r265931
2018-11-07[arm] Add support for Arm AresKyrylo Tkachov3-3/+17
This adds support for the Arm Ares CPU for in the arm port. It implements the Armv8.2-A architecture with the optional features of statistical profiling, dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/arm/arm-cpus.in (ares): New entry. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (ARM Options): Document ares. From-SVN: r265881
2018-11-07[AArch64] Add -mcpu/-mtune support for Arm AresKyrylo Tkachov2-1/+2
This adds support for the Arm Ares CPU for AArch64. It implements the Armv8.2-A architecture with the optional features of statistical profiling, dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/aarch64/aarch64-cores.def (ares): Define. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (AArch64 Options): Document ares value for mtune. From-SVN: r265880
2018-11-07Fix some typo and brain twister logical.Chenghua Xu3-20/+20
gcc/ * config/mips/mips.c: Fix typo in documentation of mips_loongson_ext2_prefetch_cookie. (mips_option_override): fix brain twister logical. * config/mips/mips.h: Fix typo in documentation of ISA_HAS_CTZ_CTO and define pattern. * config/mips/mips.md (prefetch): Hoist EXT2 above the 2EF/EXT block. (prefetch_indexed): Hoist EXT2 above the EXT block. gcc/testsuite/ * gcc.target/mips/loongson-ctz.c: Fix typo. * gcc.target/mips/loongson-dctz.c: Fix typo. From-SVN: r265871
2018-11-07Add support for Loongson 2K1000 processor.Chenghua Xu7-16/+170
gcc/ * config/mips/gs264e.md: New. * config/mips/mips-cpus.def: Define gs264e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs264e. (mips_issue_rate): Add support for gs264e. (mips_multipass_dfa_lookahead): Likewise. * config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs264e. (MIPS_ASE_MSA_SPEC): New. (BASE_DRIVER_SELF_SPECS): march=gs264e implies -mmsa. (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS264E. (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS264E. * config/mips/mips.md: Include gs264e.md. (processor): Add gs264e. * config/mips/mips.opt (MSA): Use Mask instead of Var. * doc/invoke.texi: Add gs264e to supported architectures. From-SVN: r265867
2018-11-07Add support for Loongson 3A2000/3A3000 processor.Chenghua Xu6-13/+165
gcc/ * config/mips/gs464e.md: New. * config/mips/mips-cpus.def: Define gs464e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs464e. (mips_issue_rate): Add support for gs464e. (mips_multipass_dfa_lookahead): Likewise. (mips_option_override): Enable MMI, EXT and EXT2 for gs464e. * config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e. (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E. (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E. * config/mips/mips.md: Include gs464e.md. (processor): Add gs464e. * doc/invoke.texi: Add gs464e to supported architectures. From-SVN: r265866
2018-11-07Add support for Loongson 3A1000 processor.Chenghua Xu7-159/+164
gcc/ * config/mips/loongson3a.md: Rename to ... * config/mips/gs464.md: ... here. * config/mips/mips-cpus.def: Define gs464; Add loongson3a as an alias of gs464 processor. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464 instead of PROCESSOR_LOONGSON_3A. (mips_multipass_dfa_lookahead): Use TUNE_GS464 instead of TUNE_LOONGSON_3A. (mips_option_override): Enable MMI and EXT for gs464. * config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464; Rename TUNE_LOONGSON_3A to TUNE_GS464. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464. (ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4, ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of TARGET_LOONGSON_3A. * config/mips/mips.md: Include gs464.md instead of loongson3a.md. (processor): Add gs464; * doc/invoke.texi: Add gs464 to supported architectures. From-SVN: r265865
2018-11-07Add support for Loongson EXT2 instructions.Chenghua Xu5-5/+90
gcc/ * config/mips/mips-protos.h (mips_loongson_ext2_prefetch_cookie): New prototype. * config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New. (mips_option_override): Enable TARGET_LOONGSON_EXT when TARGET_LOONGSON_EXT2 is true. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_loongson_ext2, __mips_loongson_ext_rev=2. (ISA_HAS_CTZ_CTO): New, true if TARGET_LOONGSON_EXT2. (ISA_HAS_PREFETCH): Include TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2. (ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2. (define_insn "ctz<mode>2"): New insn pattern. (define_insn "prefetch"): Include TARGET_LOONGSON_EXT2. (define_insn "prefetch_indexed_<mode>"): Include TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2. * config/mips/mips.opt (-mloongson-ext2): Add option. * gcc/doc/invoke.texi (-mloongson-ext2): Document. gcc/testsuite/ * gcc.target/mips/loongson-ctz.c: New test. * gcc.target/mips/loongson-dctz.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext2 option. From-SVN: r265864
2018-11-07Add support for Loongson EXT instructions.Chenghua Xu3-9/+25
gcc/ * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_ext. (MIPS_ASE_LOONGSON_EXT_SPEC): New. (BASE_DRIVER_SELF_SPECS): march=loongson3a implies -mloongson-ext. (ASM_SPEC): Add mloongson-ext and mno-loongson-ext. * config/mips/mips.md (mul<mode>3, mul<mode>3_mul3_nohilo, <u>div<mode>3, <u>mod<mode>3, prefetch): Use TARGET_LOONGSON_EXT instead of TARGET_LOONGSON_3A. * config/mips/mips.opt (-mloongson-ext): Add option. * gcc/doc/invoke.texi (-mloongson-ext): Document. gcc/testsuite/ * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext option. (mips-dg-options): Add mips_option_dependency options "-mmicromips" vs "-mno-loongson-ext", From-SVN: r265863
2018-11-07Add support for Loongson MMI instructions.Chenghua Xu7-774/+824
gcc/ * config.gcc (extra_headers): Add loongson-mmiintrin.h. * config/mips/loongson.md: Move to ... * config/mips/loongson-mmi.md: here; Adjustment. * config/mips/loongson.h: Move to ... State as deprecated. Include loongson-mmiintrin.h for back compatibility and warning. * config/mips/loongson-mmiintrin.h: ... here. * config/mips/mips.c (mips_hard_regno_mode_ok_uncached, mips_vector_mode_supported_p, AVAIL_NON_MIPS16): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. (mips_option_override): Make sure MMI use hard float; (mips_shift_truncation_mask, mips_expand_vpc_loongson_even_odd, mips_expand_vpc_loongson_pshufh, mips_expand_vpc_loongson_bcast, mips_expand_vector_init): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. * gcc/config/mips/mips.h (TARGET_LOONGSON_VECTORS): Delete. (TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_mmi. (MIPS_ASE_DSP_SPEC, MIPS_ASE_LOONGSON_MMI_SPEC): New. (BASE_DRIVER_SELF_SPECS): march=loongson2e/2f/3a implies -mloongson-mmi. (SHIFT_COUNT_TRUNCATED): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. * gcc/config/mips/mips.md (MOVE64, MOVE128): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. (Loongson MMI patterns): Include loongson-mmi.md instead of loongson.md. * gcc/config/mips/mips.opt (-mloongson-mmi): New option. * gcc/doc/invoke.texi (-mloongson-mmi): Document. gcc/testsuite/ * gcc.target/mips/loongson-shift-count-truncated-1.c (dg-options): Run under -mloongson-mmi option. Include loongson-mmiintrin.h instead of loongson.h. * gcc.target/mips/loongson-simd.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-mmi option. (mips-dg-options): Add mips_option_dependency options "-mips16" vs "-mno-loongson-mmi", "-mmicromips" vs "-mno-loongson-mmi", "-msoft-float" vs "-mno-loongson-mmi". (mips-dg-init): Add -mloongson-mmi option. * lib/target-supports.exp: Rename check_mips_loongson_hw_available to check_mips_loongson_mmi_hw_available. Rename check_effective_target_mips_loongson_runtime to check_effective_target_mips_loongson_mmi_runtime. (check_effective_target_vect_int): Use mips_loongson_mmi instead of mips_loongson when check et-is-effective-target. (add_options_for_mips_loongson_mmi): New proc. Rename check_effective_target_mips_loongson to check_effective_target_mips_loongson_mmi. (check_effective_target_vect_shift, check_effective_target_whole_vector_shift, check_effective_target_vect_no_int_min_max, check_effective_target_vect_no_align, check_effective_target_vect_short_mult, check_vect_support_and_set_flags):Use mips_loongson_mmi instead of mips_loongson when check et-is-effective-target. From-SVN: r265862
2018-11-06rs6000.md (bswap<mode>2): Force address into register if not in indexed or ↵Aaron Sawdey1-4/+10
indirect form. 2018-11-06 Aaron Sawdey <acsawdey@linux.ibm.com> * config/rs6000/rs6000.md (bswap<mode>2): Force address into register if not in indexed or indirect form. (bswap<mode>2_load): Change predicate to indexed_or_indirect_operand. (bswap<mode>2_store): Ditto. From-SVN: r265852
2018-11-06aarch64 - Set the mode for the unspec in speculation_tracker insn.Richard Earnshaw1-1/+1
The speculation tracker insn in my recent patch set for CVE-2017-5753 was missing a mode on the UNSPEC. Although this didn't break the build, it did cause an unnecessary warning from the MD parsing mechanism that I missed at the time. It's a trivial fix, as follows: * config/aarch64/aarch64.md (speculation_tracker): Set the mode for the UNSPEC. From-SVN: r265849
2018-11-06Fix D compilation on SolarisRainer Orth3-1/+58
* config/default-d.c: Include memmodel.h. * config/sol2-d.c: New file. * config/t-sol2 (sol2-d.o): New rule. * config.gcc <*-*-solaris2*>: Set d_target_objs, target_has_targetdm. From-SVN: r265846
2018-11-06S/390: Introduce relative_long attributeIlya Leoshkevich1-27/+67
In order to properly fix PR87762, we need to distinguish between instructions which support relative addressing and instructions which don't. We could check whether the existing "type" attribute is equal to "larl", but there are notable exceptions (lrl, for example), and changing them makes scheduling worse on z10. We could also check whether the existing "op_type" attribute is equal to "RIL-b" or "RIL-c". However, adding a new attribute provides more flexibility, since we don't depend idiosyncrasies which might be introduced into PoP in the future. gcc/ChangeLog: 2018-11-06 Ilya Leoshkevich <iii@linux.ibm.com> PR target/87762 * config/s390/s390.md: Add relative_long attribute. From-SVN: r265844
2018-11-06msp430.h (REG_CLASS_CONTENTS): Add R0 to REG_CLASS_CONTENTS[GEN_REGS].Jozef Lawrynowicz1-2/+9
2018-11-06 Jozef Lawrynowicz <jozef.l@mittosystems.com> * gcc/config/msp430/msp430.h (REG_CLASS_CONTENTS): Add R0 to REG_CLASS_CONTENTS[GEN_REGS]. (REGNO_REG_CLASS): Return NO_REGS for R2 and R3. * gcc/testsuite/gcc.target/msp430/special-regs.c: New test. From-SVN: r265839
2018-11-06Enable libsanitizer on Solaris (PR sanitizer/80953)Rainer Orth4-2/+57
gcc: PR sanitizer/80953 * config/sol2.h (ASAN_CC1_SPEC): Define. (LD_WHOLE_ARCHIVE_OPTION): Define. (LD_NO_WHOLE_ARCHIVE_OPTION): Define. (ASAN_REJECT_SPEC): Provide default. (LIBASAN_EARLY_SPEC): Define. (LIBTSAN_EARLY_SPEC): Define. (LIBLSAN_EARLY_SPEC): Define. * config/i386/sol2.h (CC1_SPEC): Redefine. (ASAN_REJECT_SPEC): Define. * config/sparc/sparc.c (sparc_asan_shadow_offset): Declare. (TARGET_ASAN_SHADOW_OFFSET): Define. (sparc_asan_shadow_offset): New function. * config/sparc/sol2.h (CC1_SPEC): Append ASAN_CC1_SPEC. (ASAN_REJECT_SPEC): Define. gcc/testsuite: PR sanitizer/80953 * c-c++-common/asan/alloca_loop_unpoisoning.c: Require alloca support. (foo): Use __builtin_alloca. libsanitizer: PR sanitizer/80953 * configure.tgt (sparc*-*-solaris2.11*): Enable. (x86_64-*-solaris2.11* | i?86-*-solaris2.11*): Enable. From-SVN: r265837
2018-11-06S/390: Fix PR87723Andreas Krebbel1-1/+1
gcc/ChangeLog: 2018-11-06 Andreas Krebbel <krebbel@linux.ibm.com> PR target/87723 * config/s390/s390.md ("*r<noxa>sbg_di_rotl"): Remove mode attributes for operands 3 and 4. gcc/testsuite/ChangeLog: 2018-11-06 Andreas Krebbel <krebbel@linux.ibm.com> PR target/87723 * gcc.target/s390/pr87723.c: New test. From-SVN: r265832
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