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2018-03-17[NDS32] Use HOST_WIDE_INT_PRINT_DEC instead of %ld or %d.Kito Cheng1-9/+13
gcc/ * config/nds32/nds32.c (nds32_asm_output_mi_thunk, nds32_print_operand, nds32_print_operand_address): Use HOST_WIDE_INT_PRINT_DEC instead. From-SVN: r258620
2018-03-17[NDS32] Optimize nds32_register_priority.Chung-Ju Wu1-3/+18
gcc/ * config/nds32/nds32.c (nds32_register_priority): Modify cost. From-SVN: r258619
2018-03-17re PR target/84902 (549.fotonik3d_r from SPEC2017 fails verification with ↵Jakub Jelinek1-8/+9
-Ofast -march=native on Zen since r258518) PR target/84902 * config/i386/i386.c (initial_ix86_tune_features, initial_ix86_arch_features): Use unsigned HOST_WIDE_INT rather than unsigned long long. (set_ix86_tune_features): Change ix86_tune_mask from unsigned int to unsigned HOST_WIDE_INT, initialize to HOST_WIDE_INT_1U << ix86_tune rather than 1u << ix86_tune. Formatting fix. (ix86_option_override_internal): Change ix86_arch_mask from unsigned int to unsigned HOST_WIDE_INT, initialize to HOST_WIDE_INT_1U << ix86_arch rather than 1u << ix86_arch. (ix86_function_specific_restore): Likewise. From-SVN: r258618
2018-03-15nios2.md (movsi_internal): Fix thinko in split predicate.Sandra Loosemore1-3/+4
2018-03-15 Sandra Loosemore <sandra@codesourcery.com> gcc/ * config/nios2/nios2.md (movsi_internal): Fix thinko in split predicate. From-SVN: r258575
2018-03-15i386: Don't generate alias for function return thunkH.J. Lu1-60/+35
Function return thunks shouldn't be aliased to indirect branch thunks since indirect branch thunks are placed in COMDAT section and a COMDAT section with indirect branch may not have function return thunk. This patch generates function return thunks directly. gcc/ PR target/84574 * config/i386/i386.c (indirect_thunk_needed): Update comments. (indirect_thunk_bnd_needed): Likewise. (indirect_thunks_used): Likewise. (indirect_thunks_bnd_used): Likewise. (indirect_return_needed): New. (indirect_return_bnd_needed): Likewise. (output_indirect_thunk_function): Add a bool argument for function return. (output_indirect_thunk_function): Don't generate alias for function return thunk. (ix86_code_end): Call output_indirect_thunk_function to generate function return thunks. (ix86_output_function_return): Set indirect_return_bnd_needed and indirect_return_needed instead of indirect_thunk_bnd_needed and indirect_thunk_needed. gcc/testsuite/ PR target/84574 * gcc.target/i386/ret-thunk-9.c: Expect __x86_return_thunk label instead of __x86_indirect_thunk label. From-SVN: r258569
2018-03-15Enable Intel ENCLV support.Olga Makhotina1-9/+62
2018-03-15 Olga Makhotina <olga.makhotina@intel.com> gcc/ * config/i386/sgxintrin.h (_enclv_u32): New intrinsic. (__enclv_bc, __enclv_cd, __enclv_generic): New definitions. (ERDINFO, ETRACKC, ELDBC, ELDUC): New leaves. gcc/testsuite/ * gcc.target/i386/sgx.c (_enclv_u32): Test new intrinsic. From-SVN: r258560
2018-03-15rs6000: Fix for the previous abi_v4_pass_in_fpr changeSegher Boessenkool1-2/+2
I was a bit over-enthusiastic, we still support xilinxfp. * config/rs6000/rs6000.c (abi_v4_pass_in_fpr): Add back the TARGET_DOUBLE_FLOAT and TARGET_SINGLE_FLOAT conditions on the DFmode resp. SFmode cases. From-SVN: r258557
2018-03-15re PR target/84711 (AArch32 big-endian fails when taking subreg of a vector ↵Tamar Christina1-2/+2
mode to a scalar mode.) 2018-03-15 Tamar Christina <tamar.christina@arm.com> PR target/84711 * config/arm/arm.c (arm_can_change_mode_class): Use GET_MODE_UNIT_SIZE instead of GET_MODE_SIZE when comparing Units. gcc/testsuite/ 2018-03-15 Tamar Christina <tamar.christina@arm.com> PR target/84711 * gcc.target/arm/big-endian-subreg.c: New. From-SVN: r258554
2018-03-15re PR target/68256 (Defining TARGET_USE_CONSTANT_BLOCKS_P causes go ↵Vladimir Mezentsev1-5/+3
bootstrap failure on aarch64.) 2018-03-15 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> PR target/68256 * varasm.c (hash_section): Return an unchangeble hash value * config/aarch64/aarch64.c (aarch64_use_blocks_for_constant_p): Return !aarch64_can_use_per_function_literal_pools_p (). From-SVN: r258553
2018-03-15Add builtin_cpu for cannonlake and new isa features.Julia Koval1-1/+11
gcc/ * config/i386/i386.c (F_AVX512VBMI2, F_GFNI, F_VPCLMULQDQ, F_AVX512VNNI, F_AVX512BITALG): New. gcc/testsuite/ * gcc.target/i386/builtin_target.c (check_intel_cpu_model): Add cannonlake. (check_features): Add avx512vbmi2, gfni, vpclmulqdq, avx512vnni, avx512bitalg. libgcc/ * config/i386/cpuinfo.c (get_available_features): Add FEATURE_AVX512VBMI2, FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, FEATURE_AVX512BITALG. * config/i386/cpuinfo.h (processor_features) Add FEATURE_AVX512VBMI2, FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, FEATURE_AVX512BITALG. From-SVN: r258551
2018-03-14re PR target/83451 (FAIL: gfortran.dg/matmul_10.f90 -O3 ↵John David Anglin1-12/+8
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions (ICE)) PR target/83451 * config/pa/pa.c (pa_emit_move_sequence): Always emit secondary reload insn for floating-point loads and stores. From-SVN: r258541
2018-03-14re PR target/84422 (ICE on various builtin test functions when compiled with ↵Carl Love3-18/+18
-mcpu=power7) gcc/ChangeLog: 2018-03-14 Carl Love <cel@us.ibm.com> PR target/84422 * config/rs6000/rs6000-builtin.def: Change expansion for VMULESW to BU_P8V_AV_2. Change expansion for VMULEUW to BU_P8V_AV_2. * config/rs6000/rs6000.c: Change ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW. Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW. Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW. Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW. * config/rs6000/rs6000-c.c: Change ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW. Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW. Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW. Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW. From-SVN: r258539
2018-03-14rs6000-c.c: Add macro definitions for ALTIVEC_BUILTIN_VEC_PERMXOR.Carl Love5-0/+38
gcc/ChangeLog: 2018-03-14 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-c.c: Add macro definitions for ALTIVEC_BUILTIN_VEC_PERMXOR. * config/rs6000/rs6000.h: Add #define for vec_permxor builtin. * config/rs6000/rs6000-builtin.def: Add macro expansions for VPERMXOR. * config/rs6000/altivec.md (altivec_vpermxor): New define expand. * config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Add case UNSPEC_VPERMXOR. * config/doc/extend.texi: Add prototypes for vec_permxor. gcc/testsuite/ChangeLog: 2018-03-14 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-7-runnable.c: New test file. From-SVN: r258530
2018-03-14Split-up -march=icelake on -march=icelake-server and -march=icelake-clientJulia Koval4-54/+89
Split-up -march=icelake on -march=icelake-server and -march=icelake-client gcc/ * config.gcc (icelake-client, icelake-server): New. (icelake): Remove. * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. (initial_ix86_arch_features): Ditto. (PTA_SKYLAKE): Add SGX. (PTA_ICELAKE): Remove. (PTA_ICELAKE_CLIENT): New. (PTA_ICELAKE_SERVER): New. (ix86_option_override_internal): Split up icelake on icelake client and icelake server. (get_builtin_code_for_version): Ditto. (fold_builtin_cpu): Ditto. * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto * config/i386/i386.h (processor_type): Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ * g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake-server. * gcc.target/i386/funcspec-56.inc: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake-client and icelake-server. From-SVN: r258518
2018-03-14re PR target/84844 (ICE in extract_constrain_insn_cached, at recog.c:2217 ↵Jakub Jelinek2-6/+5
(error: insn does not satisfy its constraints)) PR target/84844 Revert 2017-04-20 Uros Bizjak <ubizjak@gmail.com> PR target/78090 * config/i386/constraints.md (Yc): New register constraint. * config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed): Use Yc constraint for alternative 2 of operand 0. Remove preferred_for_speed attribute. * gcc.target/i386/pr84844.c: New test. From-SVN: r258515
2018-03-13RISC-V: Add and document the "-mno-relax" optionPalmer Dabbelt2-0/+10
RISC-V relies on aggressive linker relaxation to get good code size. As a result no text symbol addresses can be known until link time, which means that alignment must be handled during the link. This alignment pass is essentially just another linker relaxation, so this has the unfortunate side effect that linker relaxation is required for correctness on many RISC-V targets. The RISC-V assembler has supported an ".option norelax" for a long time because there are situations in which linker relaxation is a bad idea -- the canonical example is when trying to materialize the initial value of the global pointer into a register, which would otherwise be relaxed to a NOP. We've been relying on users who want to disable relaxation for an entire link to pass "-Wl,--no-relax", but that still relies on the linker relaxing R_RISCV_ALIGN to handle alignment despite it not being strictly necessary. This patch adds a GCC option, "-mno-relax", that disable linker relaxation by adding ".option norelax" to the top of every generated assembly file. The assembler is smart enough to handle alignment at assemble time for files that have never emitted a relaxable relocation, so this is sufficient to really disable all relaxations in the linker, which results in significantly faster link times for large objects. This also has the side effect of allowing toolchains that don't support linker relaxation (LLVM and the Linux module loader) to function correctly. Toolchains that don't support linker relaxation should default to "-mno-relax" and error when presented with any R_RISCV_ALIGN relocation as those need to be handled for correctness. gcc/ChangeLog 2018-03-13 Palmer Dabbelt <palmer@sifive.com> * config/riscv/riscv.opt (mrelax): New option. * config/riscv/riscv.c (riscv_file_start): Emit ".option "norelax" when riscv_mrelax is disabled. * doc/invoke.texi (RISC-V): Document "-mrelax" and "-mno-relax". From-SVN: r258499
2018-03-13re PR target/84743 (default widths for parallel reassociation now hurt ↵Aaron Sawdey1-1/+1
rather than help) 2018-03-13 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> PR target/84743 * config/rs6000/rs6000.c (rs6000_reassociation_width): Disable parallel reassociation for int modes. From-SVN: r258495
2018-03-13[SLP/AArch64] Fix unpack handling for big-endian SVERichard Sandiford2-40/+85
I hadn't realised that on big-endian targets, VEC_UNPACK*HI_EXPR unpacks the low-numbered lanes and VEC_UNPACK*LO_EXPR unpacks the high-numbered lanes. This meant that both the SVE patterns and the handling of fully-masked loops were wrong. The patch deals with that by making sure that all vec_unpack* optabs are define_expands, using BYTES_BIG_ENDIAN to choose the appropriate define_insn. This in turn meant that we can get rid of the duplication between the signed and unsigned patterns for predicates. (We provide implementations of both the signed and unsigned optabs because the sign doesn't matter for predicates: every element contains only one significant bit.) Also, the float unpacks need to unpack one half of the input vector, but the unpacked upper bits are "don't care". There are two obvious ways of handling that: use an unpack (filling with zeros) or use a ZIP (filling with a duplicate of the low bits). The code previously used unpacks, but the sequence involved a subreg that is semantically an element reverse on big-endian targets. Using the ZIP patterns avoids that, and at the moment there's no reason to prefer one over the other for performance reasons, so the patch switches to ZIP unconditionally. As the comment says, it would be easy to optimise this later if UUNPK turns out to be better for some implementations. 2018-03-13 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * tree-vect-loop-manip.c (vect_maybe_permute_loop_masks): Reverse the choice between VEC_UNPACK_LO_EXPR and VEC_UNPACK_HI_EXPR for big-endian. * config/aarch64/iterators.md (hi_lanes_optab): New int attribute. * config/aarch64/aarch64-sve.md (*aarch64_sve_<perm_insn><perm_hilo><mode>): Rename to... (aarch64_sve_<perm_insn><perm_hilo><mode>): ...this. (*extend<mode><Vwide>2): Rename to... (aarch64_sve_extend<mode><Vwide>2): ...this. (vec_unpack<su>_<perm_hilo>_<mode>): Turn into a define_expand, renaming the old pattern to... (aarch64_sve_punpk<perm_hilo>_<mode>): ...this. Only define unsigned packs. (vec_unpack<su>_<perm_hilo>_<SVE_BHSI:mode>): Turn into a define_expand, renaming the old pattern to... (aarch64_sve_<su>unpk<perm_hilo>_<SVE_BHSI:mode>): ...this. (*vec_unpacku_<perm_hilo>_<mode>_no_convert): Delete. (vec_unpacks_<perm_hilo>_<mode>): Take BYTES_BIG_ENDIAN into account when deciding which SVE instruction the optab should use. (vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Expect zips rather than unpacks. * gcc.target/aarch64/sve/unpack_fcvt_unsigned_1.c: Likewise. * gcc.target/aarch64/sve/unpack_float_1.c: Likewise. From-SVN: r258489
2018-03-13[AArch64] Add a tlsdesc call pattern for SVERichard Sandiford1-3/+77
tlsdesc calls are guaranteed to preserve all Advanced SIMD registers, but are not guaranteed to preserve the SVE extension of them. The calls also don't preserve the SVE predicate registers. The long-term plan for handling the SVE vector registers is CLOBBER_HIGH, which adds a clobber equivalent of TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The pattern can then directly model the fact that the low 128 bits are preserved and the upper bits are clobbered. However, it's too late now for that to be included in GCC 8, so this patch conservatively treats the whole vector register as being clobbered. This has the obvious disadvantage that compiling for SVE can make NEON code worse, but I don't think there's much we can do about that until CLOBBER_HIGH is in. 2018-03-13 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * config/aarch64/aarch64.md (V4_REGNUM, V8_REGNUM, V12_REGNUM) (V20_REGNUM, V24_REGNUM, V28_REGNUM, P1_REGNUM, P2_REGNUM, P3_REGNUM) (P4_REGNUM, P5_REGNUM, P6_REGNUM, P8_REGNUM, P9_REGNUM, P10_REGNUM) (P11_REGNUM, P12_REGNUM, P13_REGNUM, P14_REGNUM): New define_constants. (tlsdesc_small_<mode>): Turn a define_expand and use tlsdesc_small_sve_<mode> for SVE. Rename original define_insn to... (tlsdesc_small_advsimd_<mode>): ...this. (tlsdesc_small_sve_<mode>): New pattern. gcc/testsuite/ * gcc.target/aarch64/sve/tls_1.c: New test. * gcc.target/aarch64/sve/tls_2.C: Likewise. From-SVN: r258488
2018-03-13[AArch64] Add SVE mul_highpart patternsRichard Sandiford2-1/+35
One advantage of the new permute handling compared to the old way is that we can now easily take advantage of the vectoriser's divmod patterns for SVE. 2018-03-13 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * config/aarch64/iterators.md (UNSPEC_SMUL_HIGHPART) (UNSPEC_UMUL_HIGHPART): New constants. (MUL_HIGHPART): New int iteraor. (su): Handle UNSPEC_SMUL_HIGHPART and UNSPEC_UMUL_HIGHPART. * config/aarch64/aarch64-sve.md (<su>mul<mode>3_highpart): New define_expand. (*<su>mul<mode>3_highpart): New define_insn. gcc/testsuite/ * gcc.target/aarch64/sve/mul_highpart_1.c: New test. * gcc.target/aarch64/sve/mul_highpart_1_run.c: Likewise. From-SVN: r258487
2018-03-13re PR target/84827 (ICE in extract_insn, at recog.c:2311)Jakub Jelinek1-1/+2
PR target/84827 * config/i386/i386.md (round<mode>2): For 387 fancy math, disable pattern if -ftrapping-math -fno-fp-int-builtin-inexact. * gcc.target/i386/pr84827.c: New test. From-SVN: r258477
2018-03-13re PR target/84786 ([miscompilation] vunpcklpd accessing xmm16-22 targeting KNL)Jakub Jelinek1-3/+3
PR target/84786 * config/i386/sse.md (sse2_loadhpd): Use Yv constraint rather than v on the last operand. * gcc.target/i386/avx512f-pr84786-1.c: New test. * gcc.target/i386/avx512f-pr84786-2.c: New test. From-SVN: r258475
2018-03-12[PATCH][AARCH64]Fix immediate alternative of movhf_aarch64 pattern.Renlin Li1-1/+1
gcc/ 2018-03-12 Renlin Li <renlin.li@arm.com> * config/aarch64/aarch64.md (movhf_aarch64): Fix mode argument to aarch64_output_scalar_simd_mov_immediate. gcc/testsuite/ 2018-03-12 Renlin Li <renlin.li@arm.com> * gcc.target/aarch64/movi_hf.c: New. * gcc.target/aarch64/f16_mov_immediate_1.c: Update. * gcc.target/aarch64/f16_mov_immediate_2.c: Update. From-SVN: r258459
2018-03-12rs6000: sysv: Don't pass SFmode in varargs in FPRsSegher Boessenkool1-6/+6
This makes the float32-basic.c testcase work on sysv (32-bit Linux). "float" is promoted to "double" for varargs. The ABI also only defines the use of double precision in varargs. But _Float32 is not promoted. Since there is no way of passing single-precision float in FPRs we should pass SFmode in GPRs (or memory) instead. This is similar to the 64-bit ABI. From-SVN: r258454
2018-03-12[NDS32] Implement TARGET_MD_ASM_ADJUST hook.Chung-Ju Wu1-0/+14
gcc/ * config/nds32/nds32.c (nds32_md_asm_adjust): New function. (TARGET_MD_ASM_ADJUST): Define. From-SVN: r258443
2018-03-12[NDS32] Refine prologue and epilogue code generation.Monk Chiang3-309/+238
gcc/ * config/nds32/nds32.c (nds32_compute_stack_frame, nds32_emit_stack_push_multiple, nds32_emit_stack_pop_multiple, nds32_emit_stack_v3push, nds32_emit_stack_v3pop, nds32_emit_adjust_frame, nds32_expand_prologue, nds32_expand_epilogue, nds32_expand_prologue_v3push, nds32_expand_epilogue_v3pop): Refine. * config/nds32/nds32.h (NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM, NDS32_LAST_CALLEE_SAVE_GPR_REGNUM, NDS32_V3PUSH_AVAILABLE_P): New. * config/nds32/nds32.md (prologue, epilogue): Use macro NDS32_V3PUSH_AVAILABLE_P to do checking. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> Co-Authored-By: Kito Cheng <kito.cheng@gmail.com> From-SVN: r258442
2018-03-11[NDS32] Add new option -mvh.Kito Cheng2-0/+6
gcc/ * config/nds32/nds32.c (nds32_cpu_cpp_builtins): Modify to define __NDS32_VH__ macro. * config/nds32/nds32.opt (mvh): New option. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r258427
2018-03-11[NDS32] Add new function nds32_cpu_cpp_builtins and use it for ↵Kito Cheng3-32/+53
TARGET_CPU_CPP_BUILTINS. gcc/ * config/nds32/nds32-protos.h (nds32_cpu_cpp_builtins): Declare function. * config/nds32/nds32.c (nds32_cpu_cpp_builtins): New function. * config/nds32/nds32.h (TARGET_CPU_CPP_BUILTINS): Modify its definition. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r258426
2018-03-11[NDS32] Implement strlensi pattern.Kito Cheng3-0/+77
gcc/ * config/nds32/nds32-memory-manipulation.c (nds32_expand_strlen): New function. * config/nds32/nds32-multiple.md (strlensi): New pattern. * config/nds32/nds32-protos.h (nds32_expand_strlen): Declare function. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r258425
2018-03-11[NDS32] Add intrinsic function for ffb, ffmism and flmism.Monk Chiang4-0/+60
gcc/ * config/nds32/constants.md (unspec_element): Add UNSPEC_FFB, UNSPEC_FFMISM and UNSPEC_FLMISM. * config/nds32/nds32-intrinsic.c (bdesc_2arg): Add builtin description for ffb, ffmism and flmism. * config/nds32/nds32-intrinsic.md (unspec_ffb): Define new pattern. (unspec_ffmism): Ditto. (unspec_flmism): Ditto. (nds32_expand_builtin_impl): Check if string extension is available. * config/nds32/nds32.h (nds32_builtins): Add NDS32_BUILTIN_FFB, NDS32_BUILTIN_FFMISM and NDS32_BUILTIN_FLMISM. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> Co-Authored-By: Kito Cheng <kito.cheng@gmail.com> From-SVN: r258424
2018-03-10i386: Fix a typo: Enforcment -> EnforcementH.J. Lu1-3/+3
PR target/84807 * config/i386/i386.opt: Replace Enforcment with Enforcement. From-SVN: r258414
2018-03-09re PR target/83969 (ICE in final_scan_insn, at final.c:2997 (error: could ↵Peter Bergner2-12/+11
not split insn) for powerpc targets) gcc/ PR target/83969 * config/rs6000/rs6000.c (rs6000_offsettable_memref_p): New prototype. Add strict argument and use it. (rs6000_split_multireg_move): Update for new strict argument. (mem_operand_gpr): Disallow all non-offsettable addresses. * config/rs6000/rs6000.md (*movdi_internal64): Use YZ constraint. gcc/testsuite/ PR target/83969 * gcc.target/powerpc/pr83969.c: New test. From-SVN: r258400
2018-03-09re PR target/84772 (powerpc-spe: Spurious "is used uninitialized" warning, ↵Jakub Jelinek2-0/+2
or possibly incorrect codegen for va_arg(long double)) PR target/84772 * config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Mark va_arg_tmp temporary TREE_ADDRESSABLE before gimplification of BUILT_IN_MEMCPY. * config/powerpcspe/powerpcspe.c (rs6000_gimplify_va_arg): Likewise. * gcc.dg/pr84772.c: New test. From-SVN: r258399
2018-03-09[arm] PR target/83193: Do not print arch/cpu hints twice on invalid -march/-mcpuKyrylo Tkachov1-2/+2
Currently when handling an invalid -march or -mcpu option on a toolchain without an explicit --with-mode configuration and compiling without an explicit -mthumb or -marm the arm specs end up calling arm_target_thumb_only to determine the "thumbness" of the target, which involves parsing the architecture or cpu name. But the functions doing that parsing also emit error messages and hints on invalid arguments. Later when we parse the architecture or cpu string to as part of the canonicalisation process (arm_canon_arch_option) we end up emitting the errors again. The solution in this patch is to silence the errors during the arm_target_thumb_only processing so that they are not emitted twice. arm_canon_arch_option is guaranteed to run as well, so it can emit the errors and hints that it needs. Bootstrapped and tested on arm-none-linux-gnueabihf. Checked that we emit the arch/cpu hints for invalid -march/-mcpu options only once when no "thumbness" options were specified during configuration or invocation. PR target/83193 * common/config/arm/arm-common.c (arm_parse_arch_option_name): Accept complain bool parameter. Only emit errors if it is true. (arm_parse_cpu_option_name): Likewise. (arm_target_thumb_only): Adjust callers of the above. * config/arm/arm-protos.h (arm_parse_cpu_option_name): Adjust prototype to take a default true bool parameter. (arm_parse_arch_option_name): Likewise. From-SVN: r258389
2018-03-09re PR target/84763 (ICE in i386_pe_seh_cold_init)Eric Botcazou1-4/+20
PR target/84763 * config/i386/winnt.c (i386_pe_seh_cold_init): Use small pre-allocation when the function accesses prior frames. From-SVN: r258381
2018-03-08[AArch64] PR target/84748: Mark *compare_cstore<mode>_insn as clobbering CC regKyrylo Tkachov1-1/+2
In this wrong-code PR the combine pass ends up moving a CC-using instruction past a *compare_cstore<mode>_insn insn_and_split. After reload the *compare_cstore<mode>_insn splitter ends up generating a SUBS instruction that clobbers the condition flags, and things go bad. The solution is simple, the *compare_cstore<mode>_insn pattern should specify that it clobbers the CC register so that combine (or any other pass) does not assume that it can move CC-using patterns across it. This patch does that and fixes the testcase. The testcase FAILs on GCC 8 only, but the buggy pattern is in GCC 6 onwards, so we should backport this as a latent bug fix after it's had some time to bake in trunk. Bootstrapped and tested on aarch64-none-linux-gnu. PR target/84748 * config/aarch64/aarch64.md (*compare_cstore<mode>_insn): Mark pattern as clobbering CC_REGNUM. * gcc.c-torture/execute/pr84748.c: New test. From-SVN: r258366
2018-03-07rs6000: -mreadonly-in-sdata (PR82411)Segher Boessenkool2-0/+9
This adds a new option -mreadonly-in-sdata (on by default) that controls whether readonly data can be put in sdata. (For EABI this does nothing, readonly data is put in sdata2 as usual). PR target/82411 * config/rs6000/rs6000.c (rs6000_elf_in_small_data_p): Don't put readonly data in sdata, if that is disabled. * config/rs6000/sysv4.opt (mreadonly-in-sdata): New option. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mreadonly-in-sdata option. gcc/testsuite/ PR target/82411 * gcc.target/powerpc/ppc-sdata-2.c: Skip if -mno-readonly-in-sdata. From-SVN: r258340
2018-03-07re PR target/84277 (A lot of new acats testsuite failures)Eric Botcazou4-13/+117
PR target/84277 * except.h (output_function_exception_table): Adjust prototype. * except.c (output_function_exception_table): Remove FNNAME parameter and add SECTION parameter. Ouput one part of the table at a time. * final.c (final_scan_insn_1) <NOTE_INSN_SWITCH_TEXT_SECTIONS>: Output the first part of the exception table and emit unwind directives. * config/i386/i386-protos.h (i386_pe_end_cold_function): Declare. (i386_pe_seh_cold_init): Likewise. * config/i386/cygming.h (ASM_DECLARE_COLD_FUNCTION_NAME): New macro. (ASM_DECLARE_COLD_FUNCTION_SIZE): Likewise. * config/i386/i386.c (x86_expand_epilogue): Fix wording in comment. (ix86_output_call_insn): Emit a nop in one more case for SEH. * config/i386/winnt.c: Include except.h. (struct seh_frame_state): Add reg_offset, after_prologue and in_cold_section fields. (i386_pe_seh_end_prologue): Set seh->after_prologue. (i386_pe_seh_cold_init): New function. (i386_pe_seh_fini): Add COLD parameter and bail out if it is not equal to seh->in_cold_section. (seh_emit_push): Record the offset of the push. (seh_emit_save): Record the offet of the save. (i386_pe_seh_unwind_emit): Deal with NOTE_INSN_SWITCH_TEXT_SECTIONS. Test seh->after_prologue to disregard the epilogue. (i386_pe_end_function): Pass FALSE to i386_pe_seh_fini. (i386_pe_end_cold_function): New function. From-SVN: r258338
2018-03-07re PR target/84565 (ICE in extract_insn, at recog.c:2304 on aarch64)Jakub Jelinek1-1/+1
PR fortran/84565 * config/aarch64/predicates.md (aarch64_simd_reg_or_zero): Use aarch64_simd_or_scalar_imm_zero rather than aarch64_simd_imm_zero. * gfortran.dg/pr84565.f90: New test. From-SVN: r258333
2018-03-07pa.h (ASM_GENERATE_INTERNAL_LABEL): Revise to use sprint_ul.John David Anglin2-6/+26
* config/pa/pa.h (ASM_GENERATE_INTERNAL_LABEL): Revise to use sprint_ul. (ASM_OUTPUT_ADDR_VEC_ELT): Revise for above change. (ASM_OUTPUT_ADDR_DIFF_ELT): Likewise. * config/pa/pa64-hpux.h (ASM_GENERATE_INTERNAL_LABEL): Revise as above. From-SVN: r258312
2018-03-06[ARC] Cleanup unused functions.Claudiu Zissulescu3-473/+4
Remove unused pieces of code. gcc/ 2018-03-06 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_finalize_pic): Remove function. (arc_must_save_register): We use single base PIC register, remove checks to save/restore the PIC register. (arc_expand_prologue): Likewise. * config/arc/arc-protos.h (arc_set_default_type_attributes): Remove. (arc_verify_short): Likewise. (arc_attr_type): Likewise. * config/arc/arc.c (arc_set_default_type_attributes): Remove. (walk_stores): Likewise. (arc_address_cost): Make it static. (arc_verify_short): Likewise. (branch_dest): Likewise. (arc_attr_type): Likewise. * config/arc/arc.c (TARGET_ADJUST_INSN_LENGTH): Remove. (TARGET_INSN_LENGTH_PARAMETERS): Likewise. (arc_final_prescan_insn): Remove inserting the nops due to hardware hazards. It is done in reorg step. (insn_length_variant_t): Remove. (insn_length_parameters_t): Likewise. (arc_insn_length_parameters): Likewise. (arc_get_insn_variants): Likewise. * config/arc/arc.h (TARGET_UPSIZE_DBR): Remove. From-SVN: r258275
2018-03-06rs6000-builtin.def (rs6000_speculation_barrier): Rename to ↵Bill Schmidt2-2/+2
ppc_speculation_barrier. [gcc] 2018-03-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000-builtin.def (rs6000_speculation_barrier): Rename to ppc_speculation_barrier. * config/rs6000/rs6000.c (rs6000_init_builtins): Rename builtin to __builtin_ppc_speculation_barrier. [gcc/testsuite] 2018-03-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/spec-barr-1.c: Change called function name to __builtin_ppc_speculation_barrier. From-SVN: r258268
2018-03-05rs6000: Don't align tiny loops to 32 bytes for POWER9Segher Boessenkool1-2/+1
For POWER4..POWER8 we align loops of 5..8 instructions to 32 bytes (instead of to 16 bytes) because that executes faster. This is no longer the case on POWER9, so we can just as well only align to 16 bytes. * config/rs6000/rs6000.c (rs6000_loop_align): Don't align tiny loops to 32 bytes when compiling for POWER9. From-SVN: r258260
2018-03-05re PR target/84564 (error: unable to find a register to spill with ↵Jakub Jelinek1-2/+3
-mforce-indirect-call) PR target/84564 * config/i386/i386.c (ix86_function_ok_for_sibcall): Check for regparm >= 3 with no arg reg available also for calls with flag_force_indirect_call. Pass decl to ix86_function_regparm. * gcc.target/i386/pr84564.c: New test. From-SVN: r258256
2018-03-05re PR target/84524 (-O3 causes behavior change)Jakub Jelinek1-3/+3
PR target/84524 * config/i386/sse.md (*<code><mode>3): Replace <mask_prefix3> with orig,vex. (*<plusminus_insn><mode>3): Likewise. Remove <mask_operand3> uses. * gcc.c-torture/execute/pr84524.c: New test. * gcc.target/i386/avx512bw-pr84524.c: New test. From-SVN: r258252
2018-03-05re PR target/84264 (ICE in rs6000_emit_le_vsx_store, at ↵Peter Bergner1-2/+9
config/rs6000/rs6000.c:10367 starting with r256656) gcc/ PR target/84264 * config/rs6000/vector.md (mov<mode>): Disallow altivec memory operands. gcc/testsuite/ PR target/84264 * g++.dg/pr84264.C: New test. From-SVN: r258251
2018-03-05[AArch64] PR84114: Avoid reassociating FMAWilco Dijkstra1-3/+4
As discussed in the PR, the reassociation phase runs before FMAs are formed and so can significantly reduce FMA opportunities. Although reassociation could be switched off, it helps in many cases, so a better alternative is to only avoid reassociation of floating point additions. This fixes the testcase and gives 1% speedup on SPECFP2017, fixing the performance regression. gcc/ PR tree-optimization/84114 * config/aarch64/aarch64.c (aarch64_reassociation_width) Avoid reassociation of FLOAT_MODE addition. From-SVN: r258248
2018-03-05Enable WBOINVD and PCONFIG instructions.Olga Makhotina12-3/+172
2018-03-05 Olga Makhotina <olga.makhotina@intel.com> Enable WBOINVD and PCONFIG instructions. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCONFIG_SET, OPTION_MASK_ISA_PCONFIG_UNSET, OPTION_MASK_ISA_WBNOINVD_SET, OPTION_MASK_ISA_WBNOINVD_UNSET): New definitions. (ix86_handle_option): Handle -mpconfig and -mwbnoinvd. * config.gcc (pconfigintrin.h, wbnoinvdintrin.h) : Add headers. * config/i386/cpuid.h (bit_PCONFIG, bit_WBNOINVD): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mpconfig and -mwbnoinvd. * config/i386/i386-builtin.def (__builtin_ia32_wbnoinvd, __builtin_ia32_wbinvd): New builtins. (SPECIAL_ARGS2): New. * config/i386/i386-c.c (__WBNOINVD__, __PCONFIG__): New. (SPECIAL_ARGS2): New. * config/i386/i386.c (ix86_target_string): Add -mpconfig and -mwbnoinvd. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_init_mmx_sse_builtins): Add special_args2. * config/i386/i386.h (TARGET_PCONFIG, TARGET_PCONFIG_P, TARGET_WBNOINVD, TARGET_WBNOINVD_P): New. * config/i386/i386.md (UNSPECV_WBINVD, UNSPECV_WBNOINVD): New. (define_insn "wbinvd", define_insn "wbnoinvd"): New. * config/i386/i386.opt: Add -mpconfig and -mwbnoinvd. * config/i386/immintrin.h (_wbinvd): New intrinsic. * config/i386/pconfigintrin.h: New file. * config/i386/wbnoinvdintrin.h: Ditto. * config/i386/x86intrin.h: Add headers pconfigintrin.h and wbnoinvdintrin.h. * doc/invoke.texi (-mpconfig, -mwbnoinvd): New. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpconfig and -mwbnoinvd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-23.c: Add pconfig and wbnoinvd. * gcc.target/i386/wbinvd-1.c: New test. * gcc.target/i386/wbnoinvd-1.c: Ditto. * gcc.target/i386/pconfig-1.c: Ditto. From-SVN: r258247
2018-03-05[NDS32] Implment setmem pattern.Kito Cheng3-0/+439
gcc/ * config/nds32/nds32-protos.h (nds32_expand_setmem): Declare. * config/nds32/nds32-multiple.md (setmemsi): Define. * config/nds32/nds32-memory-manipulation.c (nds32_gen_dup_4_byte_to_word_value): New. (emit_setmem_word_loop): New. (emit_setmem_byte_loop): New. (nds32_expand_setmem_loop): New. (nds32_expand_setmem_loop_v3m): New. (nds32_expand_setmem_unroll): New. (nds32_expand_setmem): New. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r258239
2018-03-04[NDS32] Rename nds32_expand_movmemqi to nds32_expand_movmemsi and rewrite ↵Kito Cheng3-56/+399
its implementation. gcc/ *config/nds32/nds32-memory-manipulation.c (nds32_emit_load_store): New. (nds32_emit_post_inc_load_store): New. (nds32_emit_mem_move): New. (nds32_emit_mem_move_block): New. (nds32_expand_movmemsi_loop_unknown_size): New. (nds32_expand_movmemsi_loop_known_size): New. (nds32_expand_movmemsi_loop): New. (nds32_expand_movmemsi_unroll): New. (nds32_expand_movmemqi): Rename ... (nds32_expand_movmemsi): ... to this. *config/nds32/nds32-multiple.md (movmemqi): Rename ... (movmemsi): ... to this. *config/nds32/nds32-protos.h (nds32_expand_movmemqi): Rename ... (nds32_expand_movmemsi): ... to this. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r258235
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