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2016-04-13i386.md (kunpckhi): Swap operands.Ilya Enkovich2-7/+7
gcc/ * config/i386/i386.md (kunpckhi): Swap operands. (kunpcksi): Likewise. (kunpckdi): Likewise. * config/i386/sse.md (vec_pack_trunc_qi): Likewise. (vec_pack_trunc_<mode>): Likewise. gcc/testsuite/ * gcc.target/i386/avx512bw-kunpckdq-2.c: New test. * gcc.target/i386/avx512bw-kunpckwd-2.c: New test. * gcc.target/i386/avx512f-kunpckbw-2.c: New test. From-SVN: r234938
2016-04-12re PR target/70630 (sparc bootstrap failure: sparc.c:4919:6: error: suggest ↵Eric Botcazou1-6/+11
explicit braces to avoid ambiguous 'else') 2016-04-12 Eric Botcazou <ebotcazou@adacore.com> PR target/70630 * config/sparc/sparc.c (sparc_compute_frame_size): Add parentheses. From-SVN: r234918
2016-04-12i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Bump the upper SIMDLEN ↵Jakub Jelinek1-16/+23
limits... * config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Bump the upper SIMDLEN limits, so that if the return type or characteristic type if the return type is void can be passed in all available SSE2/AVX/AVX2/AVX512-F registers, the SIMDLEN is allowed. * c-c++-common/cilk-plus/SE/ef_error2.c (func2): Use vectorlength 128 instead of 32. From-SVN: r234913
2016-04-12re PR middle-end/70680 (OpenMP SIMD linear variable privatized too eagerly)Michael Meissner1-4/+4
[gcc] 2016-04-12 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/70680 * config/rs6000/rs6000.md (ieee_128bit_vsx_neg<mode>2_internal): Do not use "=" constraint on an input constraint. (ieee_128bit_vsx_abs<mode>2_internal): Likewise. (ieee_128bit_vsx_nabs<mode>2_internal): Likewise. (ieee_128bit_vsx_nabs<mode>2): Correct splitter so that it generates (neg (abs ...)) instead of (abs ...). [gcc/testsuite] 2016-04-12 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/70680 * gcc.target/powerpc/pr70640.c: New test. From-SVN: r234910
2016-04-11re PR target/70381 (On powerpc, -mfloat128 is on by default for all VSX systems)Michael Meissner1-2/+2
[gcc] 2016-04-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/70381 * config/rs6000/rs6000.c (rs6000_opt_masks): Disable using the target attribute and pragma from changing the -mfloat128 and -mfloat128-hardware options. * doc/extend.texi (Additional Floating Types): Document PowerPC __float128 restrictions. [libgcc] 2016-04-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/70381 * configure.ac (powerpc*-*-linux*): Rework tests to build __float128 emulation routines to not depend on using #pragma GCC target to enable -mfloat128. * configure: Regnerate. [gcc/testsuite] 2016-04-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/70381 * gcc.target/powerpc/float128-1.c: New tests to make sure the __float128 emulator is built and runs. * gcc.target/powerpc/float128-1.c: Likewise. * lib/target-supports.exp (check_ppc_float128_sw_available): Rework tests for __float128 software and hardware availability. Fix exit condition to return 0 on success. From-SVN: r234884
2016-04-11[Patch AArch64 3/3] Fix up for pr70133James Greenhalgh1-77/+110
gcc/ PR target/70133 * config/aarch64/driver-aarch64.c (aarch64_get_extension_string_for_isa_flags): New. (arch_extension): Rename to... (aarch64_arch_extension): ...This. (ext_to_feat_string): Rename to... (aarch64_extensions): ...This. (aarch64_core_data): Keep track of architecture extension flags. (cpu_data): Rename to... (aarch64_cpu_data): ...This. (aarch64_arch_driver_info): Keep track of architecture extension flags. (get_arch_name_from_id): Rename to... (get_arch_from_id): ...This, change return type. (host_detect_local_cpu): Update and reformat for renames, handle extensions through common infrastructure. From-SVN: r234877
2016-04-11[Patch AArch64 2/3] Rework the code to print extension strings (pr70133)James Greenhalgh4-98/+55
gcc/ PR target/70133 * config/aarch64/aarch64-common.c (aarch64_option_extension): Keep track of a canonical flag name. (all_extensions): Likewise. (arch_to_arch_name): Also track extension flags enabled by the arch. (all_architectures): Likewise. (aarch64_parse_extension): Move to here. (aarch64_get_extension_string_for_isa_flags): Take a new argument, rework. (aarch64_rewrite_selected_cpu): Update for above change. * config/aarch64/aarch64-option-extensions.def: Rework the way flags are handled, such that the single explicit value enabled by an extension is kept seperate from the implicit values it also enables. * config/aarch64/aarch64-protos.h (aarch64_parse_opt_result): Move to here. (aarch64_parse_extension): New. * config/aarch64/aarch64.c (aarch64_parse_opt_result): Move from here to config/aarch64/aarch64-protos.h. (aarch64_parse_extension): Move from here to common/config/aarch64/aarch64-common.c. (aarch64_option_print): Update. (aarch64_declare_function_name): Likewise. (aarch64_start_file): Likewise. * config/aarch64/driver-aarch64.c (arch_extension): Keep track of the canonical flag for extensions. * config.gcc (aarch64*-*-*): Extend regex for capturing extension flags. gcc/testsuite/ PR target/70133 * gcc.target/aarch64/mgeneral-regs_4.c: Fix expected output. * gcc.target/aarch64/target_attr_15.c: Likewise. From-SVN: r234876
2016-04-11[Patch AArch64 1/3] Enable CRC by default for armv8.1-aJames Greenhalgh1-1/+1
gcc/ * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8_1): Also add AARCH64_FL_CRC. From-SVN: r234875
2016-04-08Complete changes to "Ignore -ftree-parallelize-loops={0,1} using gt"Thomas Schwinge6-11/+12
Apply the r225764 and r233573 changes to all relevant spec strings. gcc/ * config/arc/arc.h (LINK_COMMAND_SPEC): Use gt to ignore -ftree-parallelize-loops={0,1}. * config/darwin.h (LINK_COMMAND_SPEC_A): Likewise. * config/i386/mingw32.h (GOMP_SELF_SPECS): Likewise. * config/ia64/hpux.h (LIB_SPEC): Likewise. * config/pa/pa-hpux11.h (LIB_SPEC): Likewise. * config/pa/pa64-hpux.h (LIB_SPEC): Likewise. From-SVN: r234831
2016-04-08[ARM] PR target/70566 Check that condition register is dead in tst-imm -> ↵Kyrylo Tkachov1-2/+4
lsls-imm Thumb2 peepholes PR target/70566 * config/arm/thumb2.md (tst + branch-> lsls + branch peephole below *orsi_not_shiftsi_si): Require that condition register is dead after the peephole. (second peephole after the above): Likewise. * gcc.c-torture/execute/pr70566.c: New test. From-SVN: r234825
2016-04-07cgraph.h (struct cgraph_simd_clone): Add mask_mode field.Jakub Jelinek1-1/+6
* cgraph.h (struct cgraph_simd_clone): Add mask_mode field. * omp-low.c (simd_clone_init_simd_arrays, simd_clone_adjust): Handle node->simdclone->mask_mode != VOIDmode masks. (simd_clone_adjust_argument_types): Likewise. Move sc var definition earlier, use it instead of node->simdclone. * config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Set clonei->mask_mode. * c-c++-common/attr-simd.c: Add scan-assembler* directives for AVX512F clones. * c-c++-common/attr-simd-2.c: Likewise. * c-c++-common/attr-simd-4.c: Likewise. * gcc.dg/gomp/simd-clones-2.c: Likewise. * gcc.dg/gomp/simd-clones-3.c: Likewise. From-SVN: r234816
2016-04-06sse.md (shuffletype): Add V32HI and V4TI modes.Uros Bizjak1-3/+5
* config/i386/sse.md (shuffletype): Add V32HI and V4TI modes. (ssescalarsize): Add V8SF, V4SF, V4DF and V2DF modes. From-SVN: r234784
2016-04-06i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Add support for ↵Jakub Jelinek1-6/+35
AVX512F clones... * config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Add support for AVX512F clones, include them by default for exported OpenMP declare simd functions. For AVX2 allow simdlen 32 and use it if charasteric type is 8-bit, for AVX512F allow simdlen up to 128. * lib/target-supports.exp (check_effective_target_vect_simd_clones): Check for avx512f effective targets instead of avx2. * gcc.dg/gomp/declare-simd-1.c: Add scan-assembler-times directives for AVX512F clones. * gcc.dg/gomp/declare-simd-3.c: Likewise. * g++.dg/gomp/declare-simd-1.C: Likewise. * g++.dg/gomp/declare-simd-3.C: Likewise. * g++.dg/gomp/declare-simd-4.C: Likewise. From-SVN: r234780
2016-04-05predicates.md (integer_store_memory_operand): Accept REG+D operands with a ↵John David Anglin1-0/+6
large offset when reload_in_progress is true. * config/pa/predicates.md (integer_store_memory_operand): Accept REG+D operands with a large offset when reload_in_progress is true. (floating_point_store_memory_operand): Likewise. From-SVN: r234765
2016-04-05re PR target/70510 (ICE: output_operand: invalid %-code with -mavx512bw ↵Uros Bizjak1-1/+2
-masm=intel when emitting vpbroatcast) PR target/70510 * config/i386/sse.md (iptr): Add V64QI, V32HI, V16SI and V8DI modes. testsuite/ChangeLog: PR target/70510 * gcc.target/i386/pr70510.c: New test. From-SVN: r234752
2016-04-05re PR target/70525 (generating 'vpandn' without the mode suffix, gnu as ↵Jakub Jelinek1-43/+29
fails to assemble (-mavx512bw)) PR target/70525 * config/i386/sse.md (*andnot<mode>3): Simplify assertions. Use vpandn<ssemodesuffix> for V16SI/V8DImode, vpandnq for V32HI/V64QImode, don't use <mask_operand3_1>, fix up formatting. (*andnot<mode>3_mask): Remove insn with VI12_AVX512VL iterator. * gcc.target/i386/pr70525.c: New test. From-SVN: r234739
2016-04-03re PR target/70416 ([SH]: error: 'asm' operand requires impossible reload ↵Oleg Endo1-3/+12
when building ruby2.3) gcc/ PR target/70416 PR target/67391 * config/sh/sh.md (*addsi3): Allow pattern when reload_in_progress is set, but not for SP_REG operands. gcc/testsuite/ PR target/70416 PR target/67391 * gcc.target/sh/torture/pr70416.c: New. From-SVN: r234702
2016-04-01[AArch64] Fix SIMD predicateEvandro Menezes1-1/+1
Fix the predicate "aarch64_simd_reg_or_zero" to correctly validate the "Y" constraint (scalar FP 0.0 immediate). * gcc/config/aarch64/predicates.md (aarch64_simd_reg_or_zero): Add the "const_double" to the list of operand constraints. From-SVN: r234685
2016-04-01re PR rtl-optimization/70467 (Useless "and [esp],-1" emitted on AND with ↵Jakub Jelinek1-2/+16
uint64_t variable) PR rtl-optimization/70467 * config/i386/i386.md (*add<dwi>3_doubleword, *sub<dwi>3_doubleword): If low word of the last operand is 0, just emit addition/subtraction for the high word. * gcc.target/i386/pr70467-2.c: New test. From-SVN: r234679
2016-04-01PR70404 S/390: Fix insv expansion.Andreas Krebbel1-1/+1
While the expander accepts general_operand as src operand the risbg pattern only immediate_operand. Unfortunately the expander called force_reg only for VOIDmode constants missing things like e.g. symbol_refs. Fixed with the attached patch. gcc/ChangeLog: 2016-04-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com> PR target/70404 * config/s390/s390.c (s390_expand_insv): Check for everything constant instead of just VOIDmode stuff. From-SVN: r234678
2016-04-01re PR target/70496 (inadvertent change to ASM_APP_OFF for .arm / .thumb ↵Ramana Radhakrishnan1-1/+2
directives.) Fix PR target/70496 While doing the unified asm rewrite - I inadvertently changed the meaning of ASM_APP_OFF which causes failures when folks who know what they are doing switch between arm and thumb states within a function. The intent of the unified asm rewrite was not to affect any inline assembler code in that it would remain in divided syntax by default and switching back to unified asm in normal compiled code after the inline assembler block. Thanks to Jim Wilson for pointing it out on the linaro list. Fixed thusly and a test is added. Tested arm-none-eabi cross and applied. Ramana 2016-04-01 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/70496 * config/arm/arm.h (ASM_APP_OFF): Handle TARGET_ARM and TARGET_THUMB. 2016-04-01 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/70496 * gcc.target/arm/pr70496.c: New test. From-SVN: r234675
2016-03-31[Patch ARM] Delete ASM_OUTPUT_DEF and fall back to default .set directiveJames Greenhalgh1-11/+0
gcc/ * config/arm/linux-elf.h (ASM_OUTPUT_DEF): Delete. From-SVN: r234638
2016-03-31re PR target/70442 (gcc ICE at -O2 and above on valid code on ↵Ilya Enkovich1-3/+6
x86_64-linux-gnu in "extract_insn") gcc/ PR target/70442 * config/i386/i386.c (scalar_chain::convert_op): Fix description. (scalar_chain::convert_insn): Call convert_op for reg moves to handle undefined registers. gcc/testsuite/ PR target/70442 * gcc.dg/pr70442.c: New test. From-SVN: r234637
2016-03-31re PR target/70453 (gcc generates invalid instruction vextractu64x4 (should ↵Kirill Yukhin1-1/+1
be: vextracti64x4)) Fix PR target/70453. gcc/ * config/i386/sse.md (define_mode_attr shuffletype): Fix typo. gcc/testsuite/ * gcc.target/i386/pr70453.c: New test. From-SVN: r234634
2016-03-30re PR target/70421 (wrong code with v16si vector and useless cast at -O ↵Jakub Jelinek1-1/+6
-mavx512f) PR target/70421 * config/i386/i386.c (ix86_expand_vector_set): Fix up argument order in gen_blendm expander. * gcc.dg/torture/pr70421.c: New test. * gcc.target/i386/avx512f-pr70421.c: New test. From-SVN: r234569
2016-03-30re PR target/62254 (gcc-4.9 ICEs on linux kernel zlib for armv3)Nick Clifton1-4/+17
PR target/62254 * config/arm/arm.c (arm_reload_out_hi): Add code to handle the case where we are already provided with an SImode SUBREG. From-SVN: r234568
2016-03-30Properly check conflict between DRAP register and __builtin_eh_returnH.J. Lu1-3/+5
Since %ecx can't be used for both DRAP register and __builtin_eh_return, we need to check if crtl->drap_reg uses %ecx before using %ecx for __builtin_eh_return. PR target/70439 * config/i386/i386.c (ix86_expand_epilogue): Properly check conflict between DRAP register and __builtin_eh_return. From-SVN: r234559
2016-03-29re PR target/63890 (Compiling trivial program with -O -p leads to misaligned ↵Mike Stump1-1/+2
stack) PR target/63890 * config/i386/i386.h (ACCUMULATE_OUTGOING_ARGS): Use when profiling and TARGET_MACHO. * tree-vrp.c (register_edge_assert_for_2): For NAME != CST1 From-SVN: r234545
2016-03-29[Hurd] Specs maintenanceThomas Schwinge2-10/+2
gcc/ * config/gnu.h (CPP_SPEC, LIB_SPEC): Don't override. * config/i386/gnu.h (STARTFILE_SPEC): Use gcrt1.o instead of gcrt0.o if linking dynamically. From-SVN: r234535
2016-03-29ft32.opt (mnodiv): New.James Bowman2-4/+8
* config/ft32/ft32.opt (mnodiv): New. * config/ft32/ft32.md (*divsi3, *modsi3): Qualify with TARGET_NODIV. * doc/invoke.texi (FT32 Options -mnodiv): New. * libgcc/config/ft32/lib1funcs.S (*divsi3, *modsi3): New. From-SVN: r234516
2016-03-28re PR target/70406 (ICE: in extract_insn, at recog.c:2287 (unrecognizable ↵Kirill Yukhin1-3/+3
insn) with -mtune=pentium2 -mavx512f) PR target/70406 gcc/ * config/i386/i386.md (define_split, andn): Fix modes. gcc/testsuite/ * gcc.target/i386/pr70406.c: New test. From-SVN: r234500
2016-03-25re PR target/70120 ([aarch64] -g causes Assembler messages: Error: unaligned ↵Richard Henderson3-0/+18
opcodes detected in executable segment) 2016-03-25 Richard Henderson <rth@redhat.com> PR target/70120 * config/aarch64/aarch64.c (aarch64_asm_output_pool_epilogue): New. * config/aarch64/aarch64-protos.h: Declare it. * config/aarch64/aarch64.h (ASM_OUTPUT_POOL_EPILOGUE): New. PR target/70120 * gcc.target/aarch64/pr70120-1.c: New. * gcc.target/aarch64/pr70120-2.c: New. * gcc.target/aarch64/pr70120-3.c: New. From-SVN: r234486
2016-03-25[RS6000] PR70052, ICE compiling _Decimal128 test caseAlan Modra3-12/+23
gcc/ PR target/70052 * config/rs6000/constraints.md (j): Simplify. * config/rs6000/predicates.md (easy_fp_constant): Exclude decimal float 0.D. * config/rs6000/rs6000.md (zero_fp): New mode_attr. (mov<mode>_hardfloat, mov<mode>_hardfloat32, mov<mode>_hardfloat64, mov<mode>_64bit_dm, mov<mode>_32bit): Use zero_fp in place of j in all constraint alternatives. (movtd_64bit_nodm): Delete "j" constraint alternative. gcc/testsuite/ * gcc.dg/dfp/pr70052.c: New test. From-SVN: r234479
2016-03-25re PR target/70319 (FAIL: gcc.dg/sso/q2.c -O1 -fno-inline execution test)John David Anglin1-2/+3
PR target/70319 * config/pa/pa.md (bswapdi2): Use a scratch register. From-SVN: r234475
2016-03-24i386.md (*anddi3_doubleword): Generate AND insn using ↵Uros Bizjak1-2/+2
ix86_expand_binary_operator instead of gen_andsi3. * config/i386/i386.md (*anddi3_doubleword): Generate AND insn using ix86_expand_binary_operator instead of gen_andsi3. From-SVN: r234456
2016-03-23re PR target/70381 (On powerpc, -mfloat128 is on by default for all VSX systems)Michael Meissner1-1/+0
2016-03-23 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/70381 * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Do not set -mfloat128 here. From-SVN: r234441
2016-03-23re PR target/69917 (gcc.target/i386/chkp-hidden-def.c FAILs)Ilya Enkovich2-3/+7
gcc/ PR target/69917 * config/i386/sol2.h (ASM_OUTPUT_DEF_FROM_DECLS): Follow transparent alias chain for decl assembler name. * config/sol2.c (solaris_assemble_visibility): Likewise. From-SVN: r234423
2016-03-23[ARM] Reduce size of arm1020e automatonKyrylo Tkachov1-5/+6
* config/arm/arm1020e.md (1020call_op): Reduce reservation duration. (v10_fdivs): Likewise. (v10_fdivd): Likewise. From-SVN: r234422
2016-03-23[ARM] PR driver/70132: Avoid double fclose in driver-arm.cKyrylo Tkachov1-6/+5
PR driver/70132 * config/arm/driver-arm.c (host_detect_local_cpu): Reorder exit logic to not call fclose twice on file. From-SVN: r234419
2016-03-23re PR target/70321 (STV generates less optimized code)Jakub Jelinek1-16/+56
PR target/70321 * config/i386/i386.md (*anddi3_doubleword, *<code>di3_doubleword): Optimize TARGET_STV splitters, if high or low word of last argument is 0 or -1. From-SVN: r234416
2016-03-22re PR target/70302 (crash on valid code at -O2 and -O3 in 32-bit mode on ↵Ilya Enkovich1-0/+14
x86_64-linux-gnu (in convert_op, at config/i386/i386.c:3414)) 2016-03-22 Ilya Enkovich <enkovich.gnu@gmail.com> PR target/70302 * config/i386/i386.c (scalar_chain::convert_op): Support uninitialized register usage case. PR target/70302 * gcc.target/i386/pr70302.c: New test. From-SVN: r234406
2016-03-22Fix endianness issue for moxieboxAnthony Green1-0/+6
From-SVN: r234404
2016-03-22Remove duplicated AVX-512VL bit check.Kirill Yukhin1-3/+0
gcc/ * config/i386/i386.c (def_builtin): Remove duplicated functionality. From-SVN: r234400
2016-03-22re PR target/70325 (ICE on __builtin_ia32_storedquqi256_mask)Kirill Yukhin1-4/+15
PR target/70325 gcc/ * config/i386/i386.c (def_builtin): Handle OPTION_MASK_ISA_AVX512VL to be and-ed with other bits. (const struct builtin_description bdesc_special_args[]): Remove duplicate ISA bits. gcc/testsuite/ * gcc.target/i386/pr70325.c: New test. From-SVN: r234395
2016-03-22re PR target/70329 (wrong code with -mavx512bw and 64byte vectors)Jakub Jelinek1-4/+12
PR target/70329 * config/i386/i386.c (ix86_expand_vecop_qihi): Don't bother computing d.perm[i] for i >= d.nelt. If not full_interleave, compute d.perm[i] in a way that works also for AVX512BW. * gcc.target/i386/avx512bw-pr70329-1.c: New test. * gcc.target/i386/avx512bw-pr70329-2.c: New test. From-SVN: r234394
2016-03-22re PR target/70300 (ICE: in extract_constrain_insn, at recog.c:2190 (insn ↵Jakub Jelinek1-5/+16
does not satisfy its constraints) with -mtune=amdfam10 -mavx512bw) PR target/70300 * config/i386/i386.md (cvtsd2ss splitter): Unpack in destination instead of source if operands[1] is xmm16 and above and !TARGET_AVX512VL. Use avx512f_vec_dupv16sf_1 instead of vec_interleave_lowv4sf if we need to unpack xmm16 and above. * gcc.target/i386/pr70300.c: New test. From-SVN: r234393
2016-03-21re PR target/70327 (ICE: in extract_insn, at recog.c:2287 (unrecognizable ↵Uros Bizjak1-10/+10
insn) with -mavx512ifma and v4ti argument) PR target/70327 * config/i386/i386.md (movxi): Use ix86_expand_vector_move instead of ix86_expand_move. (movoi): Ditto. (movti): Use general_operand for operand 1 predicate. testsuite/ChangeLog: PR target/70327 * gcc.target/i386/pr70327.c: New test. From-SVN: r234380
2016-03-21re PR target/70296 (Incorrect handling of vector X; if X is function-like macro)Jakub Jelinek1-1/+15
PR target/70296 * include/cpplib.h (cpp_fun_like_macro_p): New prototype. * macro.c (cpp_fun_like_macro_p): New function. * config/rs6000/rs6000-c.c (rs6000_macro_to_expand): If IDENT is function-like macro, peek following token(s) if it is followed by CPP_OPEN_PAREN token with optional padding in between, and if not, don't treat it like a macro. * gcc.target/powerpc/altivec-36.c: New test. From-SVN: r234371
2016-03-21[nvptx] Don't emit sorry for the stabs debug formatThomas Schwinge1-4/+0
* config/nvptx/nvptx.c (nvptx_option_override): Don't emit sorry for the stabs debug format. Co-Authored-By: Alexander Monakov <amonakov@ispras.ru> From-SVN: r234370
2016-03-21re PR target/70293 ([ICE, AVX-512] Wrong reg constraints in vec_dup)Kirill Yukhin1-1/+2
PR target/70293 gcc/ * config/i386 (define_insn "*vec_dup<mode>"/AVX2): Block third alternative for AVX-512VL target, gcc/testsuite/ * gcc.target/i386/pr70293.c: New test. From-SVN: r234363
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