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AgeCommit message (Expand)AuthorFilesLines
2023-12-13amdgcn: Work around XNACK register allocation problemAndrew Stubbs4-4/+33
2023-12-13amdgcn: Support XNACK modeAndrew Stubbs5-136/+179
2023-12-13aarch64: Add missing driver-aarch64 dependenciesAndrew Carlotti1-1/+3
2023-12-13ARC: Add *extvsi_n_0 define_insn_and_split for PR 110717.Roger Sayle1-0/+20
2023-12-13RISC-V:Add crypto vector implied ISA info.Feng Wang1-6/+15
2023-12-13RISC-V: Postpone full available optimization [VSETVL PASS]Juzhe-Zhong1-2/+12
2023-12-13i386: Fix ICE on __builtin_ia32_pabsd128 without lhs [PR112962]Jakub Jelinek1-2/+8
2023-12-13aarch64: Implement the ACLE instruction/data prefetch functions.Victor Do Nascimento3-0/+167
2023-12-13rs6000: using pli for constant splittingJiufu Guo1-0/+7
2023-12-13rs6000: accurate num_insns_constant_gprJiufu Guo1-138/+146
2023-12-13RISC-V: Apply vla vs. vls mode heuristic vector COST modelJuzhe-Zhong3-2/+177
2023-12-13RISC-V: Refactor Dynamic LMUL codesJuzhe-Zhong2-70/+52
2023-12-12aarch64,arm: Fix branch-protection= parsingSzabolcs Nagy5-164/+112
2023-12-12aarch64,arm: Remove accepted_branch_protection_stringSzabolcs Nagy3-27/+1
2023-12-12RISC-V: Disable RVV VCOMPRESS avl propagationPan Li1-10/+25
2023-12-12LoongArch: Fix warnings building libgccXi Ruoyao1-10/+10
2023-12-12LoongArch: Allow -mcmodel=extreme and model attribute with -mexplicit-relocs=...Xi Ruoyao1-9/+16
2023-12-12Don't assume it's AVX_U128_CLEAN after call_insn whose abi.mode_clobber(V4DIm...liuhongt1-3/+19
2023-12-12i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]Hongyu Wang1-4/+8
2023-12-12RISC-V: Add avail interface into function_group_infoFeng Wang5-475/+503
2023-12-12RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]Juzhe-Zhong3-40/+52
2023-12-12LoongArch: Fix eh_return epilogue for normal returns.Yang Yujie3-13/+46
2023-12-11strub: disable on rl78Alexandre Oliva1-0/+5
2023-12-11aarch64: Fix wrong code for bfloat when f16 is enabled [PR 111867]Andrew Pinski1-0/+4
2023-12-11[PATCH] wrong code on m68k with -mlong-jump-table-offsets and -malign-int (PR...Mikael Pettersson3-6/+6
2023-12-11aarch64: enable mixed-types for aarch64 simdclonesAndre Vieira1-47/+127
2023-12-11RISC-V: Robostify shuffle index used by vrgather and fix regressionJuzhe-Zhong1-32/+48
2023-12-11aarch64: arm_neon.h - Fix -Wincompatible-pointer-types errorsVictor Do Nascimento1-13/+21
2023-12-11RISC-V: Recognize stepped series in expand_vec_perm_const.Robin Dapp1-2/+64
2023-12-11RISC-V: Support highest overlap for wv instructionsJuzhe-Zhong1-42/+46
2023-12-11RISC-V: Fix ICE in extract_single_sourceJuzhe-Zhong1-0/+2
2023-12-11RISC-V: Remove poly selftest when --preference=fixed-vlmaxJuzhe-Zhong1-1/+13
2023-12-11Support vpcmov for V4HF/V4BF/V2HF/V2BF under TARGET_XOP.liuhongt1-0/+22
2023-12-11rs6000: Guard fctid on PowerPC64 and PowerPC476Haochen Gui2-2/+4
2023-12-11rs6000: Enable lrint<mode>si2 on old archs with stfiwx enabledHaochen Gui1-1/+29
2023-12-10aarch64: Fix invalid subregs for BE svread/write_zaRichard Sandiford3-2/+26
2023-12-10aarch64: Fix SMSTART/SMSTOP save/restore for BERichard Sandiford1-6/+9
2023-12-10[committed] Support uaddv and usubv on the H8Jeff Law1-0/+77
2023-12-10[committed] Provide patterns for signed bitfield extractions on H8Jeff Law3-1/+113
2023-12-10[committed] Fix length computation of single bit bitfield extraction on H8Jeff Law1-1/+1
2023-12-10[committed] Fix length computation for logical shifts on H8Jeff Law1-0/+5
2023-12-09RISC-V: Fix VLS mode movmiaslign bugJuzhe-Zhong1-21/+2
2023-12-08RISC-V: Add vectorized strcmp and strncmp.Robin Dapp3-5/+163
2023-12-08RISC-V: Add vectorized strlen.Robin Dapp3-12/+34
2023-12-08aarch64: Some tweaks to the early-ra passRichard Sandiford1-20/+69
2023-12-08Revert "arm: vld1q_types_x2 ACLE intrinsics"Richard Earnshaw3-139/+0
2023-12-08Revert "arm: vld1q_types_x3 ACLE intrinsics"Richard Earnshaw3-156/+0
2023-12-08Revert "arm: vld1q_types_x4 ACLE intrinsics"Richard Earnshaw3-159/+0
2023-12-08Revert "arm: vst1_types_x2 ACLE intrinsics"Richard Earnshaw3-125/+0
2023-12-08Revert "arm: vst1_types_x3 ACLE intrinsics"Richard Earnshaw3-125/+0
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