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2019-12-30Arrange to preinclude yvals.h ahead of stdint on VxWorks 7Olivier Hainque2-0/+40
On Vxworks 7, includers of stdint.h (which we currently "provide") need yvals.h to have been included ahead. Instead of altering the common stdint-gcc.h with unpleasant vxworks specific bits to do that, we arrange to provide stdint-gcc.h on its own along with a stdint.h wrapper which preincludes yvals.h on vx7 then includes stdint-gcc.h. 2019-12-30 Olivier Hainque <hainque@adacore.com> * config/vxworks/stdint.h: New file. Include _yvals.h then stdint-gcc.h. * config/t-vxworks: Arrange to install the stdint.h wrapper. * config.gcc (*-*-vxworks*): Add stdint-gcc.h to $extra_headers so it gets copied. Set use_gcc_stdint to request _not_ crafting stdint.h through the common Makefile rules. From-SVN: r279791
2019-12-30Add missing file expected with rev 279781Olivier Hainque1-0/+37
* config/vxworks-c.c: New file. From-SVN: r279790
2019-12-30Add missing files expected with rev 279784Olivier Hainque6-0/+207
* config/vxworks/_yvals.h: New file. * config/vxworks/_yvals-wrapper.h: New file. * config/vxworks/math.h: Use it to wrap the VxWorks math.h header. * config/vxworks/complex.h: Likewise. * config/vxworks/setjmp.h: Likewise. * config/vxworks/inttypes.h: Likewise. From-SVN: r279787
2019-12-30Add missing file expected with rev 279783Olivier Hainque1-0/+54
* config/vxworks/_vxworks-versions.h: New File. From-SVN: r279786
2019-12-30Add missing file expected with rev 279781Olivier Hainque1-0/+32
From-SVN: r279785
2019-12-30Simplify the compilation commands for config/vxworks.cOlivier Hainque1-3/+3
2019-12-30 Olivier Hainque <hainque@adacore.com> * config/t-vxworks: Rework the vxworks.o compilation rules to use $(COMPILE). From-SVN: r279782
2019-12-30Setup TARGET_C_PREINCLUDE for VxWorksJoel Brobecker1-0/+4
This patch modifies the C & C++ VxWorks compiler to predefine the __STDC_ macros verified by gcc.dg/c99-predef-1.c in the testsuite. 2019-12-13 Joel Brobecker <brobecker@adacore.com> * config.gcc <*-*-vxworks*>: Add vxworks-c.o to c_target_objs and cxx_target_objs. Set target_has_targetcm to "yes". Add vxworks-predef.h to extra_headers. * config/t-vxworks (vxworks-c.o): New target. * config/vxworks-c.c: New file. * config/vxworks/vxworks-predef.h: New file. From-SVN: r279781
2019-12-30Refine definitions for wchar_t/wint_t on VxWorksAlexandre Oliva1-6/+21
This change refines the VxWorks macro definitions configuring wchar_t to accommodate the VxWorks7 environment, where wchar_t is now typically a 32bit type. We also ensure that the definitions for wint_t are always based on those for wchar_t, so the two remain in sync in environments where WCHAR_TYPE is redefined for a specific CPU architecture. 2019-12-30 Alexandre Oliva <oliva@adacore.com> Olivier Hainque <hainque@adacore.com> * config/vx-common.h (WCHAR_TYPE_SIZE): 32 on VxWorks 7. (WCHAR_TYPE): Pick accordingly. (WINT_TYPE_SIZE): Define in terms of WCHAR_TYPE_SIZE. (WINT_TYPE): Define in terms of WCHAR_TYPE. Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r279780
2019-12-30Identify sections in vx-common.hOlivier Hainque1-6/+14
2019-12-30 Olivier Hainque <hainque@adacore.com> * config/vx-common.h: Minor reorganization and add sectioning comments. From-SVN: r279779
2019-12-30Define STARTFILE_PREFIX_SPEC for powerpc VxWorks < 7Doug Rupp1-0/+7
2019-12-30 Doug Rupp <rupp@adacore.com> * config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Define. From-SVN: r279778
2019-12-30Improve recursion protection for VxWorks limits.hOlivier Hainque1-3/+34
2019-12-30 Olivier Hainque <hainque@adacore.com> Jerome Lambourg <labourg@adacore.com> * config/t-vxworks: Arrange to alter/restore glimits.h before/after stmp-int-hdrs, so it uses a different macro name to protect itself against recursive inclusions. Co-Authored-By: Jerome Lambourg <lambourg@adacore.com> From-SVN: r279777
2019-12-30Fix builtin functions needlessly using VIEW_CONVERT_EXPRs on their operands.Peter Bergner2-225/+386
gcc/ PR target/92923 * config/rs6000/rs6000-builtin.def (VAND, VANDC, VNOR, VOR, VXOR): Delete. (EQV_V16QI_UNS, EQV_V8HI_UNS, EQV_V4SI_UNS, EQV_V2DI_UNS, EQV_V1TI_UNS, NAND_V16QI_UNS, NAND_V8HI_UNS, NAND_V4SI_UNS, NAND_V2DI_UNS, NAND_V1TI_UNS, ORC_V16QI_UNS, ORC_V8HI_UNS, ORC_V4SI_UNS, ORC_V2DI_UNS, ORC_V1TI_UNS, VAND_V16QI_UNS, VAND_V16QI, VAND_V8HI_UNS, VAND_V8HI, VAND_V4SI_UNS, VAND_V4SI, VAND_V2DI_UNS, VAND_V2DI, VAND_V4SF, VAND_V2DF, VANDC_V16QI_UNS, VANDC_V16QI, VANDC_V8HI_UNS, VANDC_V8HI, VANDC_V4SI_UNS, VANDC_V4SI, VANDC_V2DI_UNS, VANDC_V2DI, VANDC_V4SF, VANDC_V2DF, VNOR_V16QI_UNS, VNOR_V16QI, VNOR_V8HI_UNS, VNOR_V8HI, VNOR_V4SI_UNS, VNOR_V4SI, VNOR_V2DI_UNS, VNOR_V2DI, VNOR_V4SF, VNOR_V2DF, VOR_V16QI_UNS, VOR_V16QI, VOR_V8HI_UNS, VOR_V8HI, VOR_V4SI_UNS, VOR_V4SI, VOR_V2DI_UNS, VOR_V2DI, VOR_V4SF, VOR_V2DF, VXOR_V16QI_UNS, VXOR_V16QI, VXOR_V8HI_UNS, VXOR_V8HI, VXOR_V4SI_UNS, VXOR_V4SI, VXOR_V2DI_UNS, VXOR_V2DI, VXOR_V4SF, VXOR_V2DF): Add definitions. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins) <ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VNOR, ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VXOR>: Remove. <ALTIVEC_BUILTIN_VAND_V4SF, ALTIVEC_BUILTIN_VAND_V2DF, ALTIVEC_BUILTIN_VAND_V2DI, ALTIVEC_BUILTIN_VAND_V2DI_UNS, ALTIVEC_BUILTIN_VAND_V4SI_UNS, ALTIVEC_BUILTIN_VAND_V4SI, ALTIVEC_BUILTIN_VAND_V8HI_UNS, ALTIVEC_BUILTIN_VAND_V8HI, ALTIVEC_BUILTIN_VAND_V16QI, ALTIVEC_BUILTIN_VAND_V16QI_UNS, ALTIVEC_BUILTIN_VANDC_V4SF, ALTIVEC_BUILTIN_VANDC_V2DF, ALTIVEC_BUILTIN_VANDC_V2DI, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, ALTIVEC_BUILTIN_VANDC_V4SI, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, ALTIVEC_BUILTIN_VANDC_V8HI, ALTIVEC_BUILTIN_VANDC_V16QI, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, ALTIVEC_BUILTIN_VNOR_V4SF, ALTIVEC_BUILTIN_VNOR_V2DF, ALTIVEC_BUILTIN_VNOR_V2DI, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, ALTIVEC_BUILTIN_VNOR_V4SI, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, ALTIVEC_BUILTIN_VNOR_V8HI, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, ALTIVEC_BUILTIN_VNOR_V16QI, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, ALTIVEC_BUILTIN_VOR_V4SF, ALTIVEC_BUILTIN_VOR_V2DF, ALTIVEC_BUILTIN_VOR_V2DI, ALTIVEC_BUILTIN_VOR_V2DI_UNS, ALTIVEC_BUILTIN_VOR_V4SI_UNS, ALTIVEC_BUILTIN_VOR_V4SI, ALTIVEC_BUILTIN_VOR_V8HI_UNS, ALTIVEC_BUILTIN_VOR_V8HI, ALTIVEC_BUILTIN_VOR_V16QI, ALTIVEC_BUILTIN_VOR_V16QI_UNS, ALTIVEC_BUILTIN_VXOR_V4SF, ALTIVEC_BUILTIN_VXOR_V2DF, ALTIVEC_BUILTIN_VXOR_V2DI, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, ALTIVEC_BUILTIN_VXOR_V4SI, ALTIVEC_BUILTIN_VXOR_V8HI, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, ALTIVEC_BUILTIN_VXOR_V16QI, ALTIVEC_BUILTIN_VXOR_V16QI_UNS>: Add definitions. <P8V_BUILTIN_EQV_V16QI, P8V_BUILTIN_EQV_V8HI, P8V_BUILTIN_EQV_V4SI, P8V_BUILTIN_EQV_V2DI, P8V_BUILTIN_NAND_V16QI, P8V_BUILTIN_NAND_V8HI, P8V_BUILTIN_NAND_V4SI, P8V_BUILTIN_NAND_V2DI, P8V_BUILTIN_ORC_V16QI, P8V_BUILTIN_ORC_V8HI, P8V_BUILTIN_ORC_V4SI, P8V_BUILTIN_ORC_V2DI>: Change unsigned usages to use the new *_UNS definition names. (rs6000_gimple_fold_builtin) <ALTIVEC_BUILTIN_VAND_V16QI_UNS, ALTIVEC_BUILTIN_VAND_V16QI, ALTIVEC_BUILTIN_VAND_V8HI_UNS, ALTIVEC_BUILTIN_VAND_V8HI, ALTIVEC_BUILTIN_VAND_V4SI_UNS, ALTIVEC_BUILTIN_VAND_V4SI, ALTIVEC_BUILTIN_VAND_V2DI_UNS, ALTIVEC_BUILTIN_VAND_V2DI, ALTIVEC_BUILTIN_VAND_V4SF, ALTIVEC_BUILTIN_VAND_V2DF, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, ALTIVEC_BUILTIN_VANDC_V16QI, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, ALTIVEC_BUILTIN_VANDC_V8HI, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, ALTIVEC_BUILTIN_VANDC_V4SI, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, ALTIVEC_BUILTIN_VANDC_V2DI, ALTIVEC_BUILTIN_VANDC_V4SF, ALTIVEC_BUILTIN_VANDC_V2DF, P8V_BUILTIN_NAND_V16QI_UNS, P8V_BUILTIN_NAND_V8HI_UNS, P8V_BUILTIN_NAND_V4SI_UNS, P8V_BUILTIN_NAND_V2DI_UNS, P8V_BUILTIN_NAND_V2DI, ALTIVEC_BUILTIN_VOR_V16QI_UNS, ALTIVEC_BUILTIN_VOR_V16QI, ALTIVEC_BUILTIN_VOR_V8HI_UNS, ALTIVEC_BUILTIN_VOR_V8HI, ALTIVEC_BUILTIN_VOR_V4SI_UNS, ALTIVEC_BUILTIN_VOR_V4SI, ALTIVEC_BUILTIN_VOR_V2DI_UNS, ALTIVEC_BUILTIN_VOR_V2DI, ALTIVEC_BUILTIN_VOR_V4SF, ALTIVEC_BUILTIN_VOR_V2DF, P8V_BUILTIN_ORC_V16QI_UNS, P8V_BUILTIN_ORC_V8HI_UNS, P8V_BUILTIN_ORC_V4SI_UNS, P8V_BUILTIN_ORC_V2DI_UNS, P8V_BUILTIN_ORC_V2DI, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, ALTIVEC_BUILTIN_VXOR_V16QI, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, ALTIVEC_BUILTIN_VXOR_V8HI, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, ALTIVEC_BUILTIN_VXOR_V4SI, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, ALTIVEC_BUILTIN_VXOR_V2DI, ALTIVEC_BUILTIN_VXOR_V4SF, ALTIVEC_BUILTIN_VXOR_V2DF, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, ALTIVEC_BUILTIN_VNOR_V16QI, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, ALTIVEC_BUILTIN_VNOR_V8HI, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, ALTIVEC_BUILTIN_VNOR_V4SI, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, ALTIVEC_BUILTIN_VNOR_V2DI, ALTIVEC_BUILTIN_VNOR_V4SF, ALTIVEC_BUILTIN_VNOR_V2DF>: Use new definition names. (builtin_function_type) <ALTIVEC_BUILTIN_VAND_V16QI_UNS, ALTIVEC_BUILTIN_VAND_V8HI_UNS, ALTIVEC_BUILTIN_VAND_V4SI_UNS, ALTIVEC_BUILTIN_VAND_V2DI_UNS, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, ALTIVEC_BUILTIN_VOR_V16QI_UNS, ALTIVEC_BUILTIN_VOR_V8HI_UNS, ALTIVEC_BUILTIN_VOR_V4SI_UNS, ALTIVEC_BUILTIN_VOR_V2DI_UNS, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, P8V_BUILTIN_EQV_V16QI_UNS, P8V_BUILTIN_EQV_V8HI_UNS, P8V_BUILTIN_EQV_V4SI_UNS, P8V_BUILTIN_EQV_V2DI_UNS, P8V_BUILTIN_EQV_V1TI_UNS, P8V_BUILTIN_NAND_V16QI_UNS, P8V_BUILTIN_NAND_V8HI_UNS, P8V_BUILTIN_NAND_V4SI_UNS, P8V_BUILTIN_NAND_V2DI_UNS, P8V_BUILTIN_NAND_V1TI_UNS, P8V_BUILTIN_ORC_V16QI_UNS, P8V_BUILTIN_ORC_V8HI_UNS, P8V_BUILTIN_ORC_V4SI_UNS, P8V_BUILTIN_ORC_V2DI_UNS, P8V_BUILTIN_ORC_V1TI_UNS>: Handle unsigned builtins. gcc/testsuite/ PR target/92923 * gcc.target/powerpc/pr92923-1.c: New test. * gcc.target/powerpc/pr92923-2.c: Likewise. From-SVN: r279772
2019-12-29re PR target/93078 (Missing fma and round functions auto-vectorization with ↵Jakub Jelinek3-25/+18
x86-64 (sse2)) PR target/93078 * config/i386/i386-builtins.c (ix86_builtin_vectorized_function): Remove CASE_CFN_RINT handling. * config/i386/i386-builtin.def (IX86_BUILTIN_RINTPD, IX86_BUILTIN_RINTPS, IX86_BUILTIN_RINTPD256, IX86_BUILTIN_RINTPS256): Remove. * config/i386/sse.md (nearbyint<mode>2, rint<mode>2): New expanders with VF iterator. * gcc.target/i386/sse4_1-pr93078.c: New test. * gcc.target/i386/avx-pr93078.c: New test. * gcc.target/i386/avx512f-pr93078.c: New test. From-SVN: r279754
2019-12-27[AArch64] Fix typo in V_INT_CONTAINERRichard Sandiford1-1/+1
All VNx2 V_INT_CONTAINER entries should map to VNx2DI. The lower-case version was already correct. 2019-12-27 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (V_INT_CONTAINER): Fix VNx2SF entry. gcc/testsuite/ * gcc.target/aarch64/sve/mixed_size_11.c: New test. From-SVN: r279743
2019-12-24rs6000: re-enable web and rnreg with -funroll-loopsJiufu Guo1-4/+11
Previously, limited unrolling was enabled at O2 for powerpc in r278034. At that time, -fweb and -frename-registers were not enabled together with -funroll-loops even for -O3. After that, we notice there are some performance degradations on SPEC2006fp which caused by without web and rnreg. This patch enable -fweb and -frename-registers for -funroll-loops to align original behavior before r278034. gcc/ 2019-12-23 Jiufu Guo <guojiufu@linux.ibm.com> * config/rs6000/rs6000.c (rs6000_option_override_internal): Enable -fweb and -frename-registers with -funroll-loops From-SVN: r279725
2019-12-20Rename signed integer 16/34-bit macros.Michael Meissner3-14/+12
2019-12-20 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/predicates.md (cint34_operand): Use SIGNED_INTEGER_34BIT_P macro. * config/rs6000/rs6000.c (num_insns_constant_gpr): Use the SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P macros. (address_to_insn_form): Use the SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P macros. * config/rs6000/rs6000.h (SIGNED_INTEGER_NBIT_P): New macro. (SIGNED_INTEGER_16BIT_P): Rename SIGNED_16BIT_OFFSET_P to be SIGNED_INTEGER_34BIT_P. (SIGNED_INTEGER_34BIT_P): Rename SIGNED_34BIT_OFFSET_P to be SIGNED_INTEGER_34BIT_P. From-SVN: r279677
2019-12-20re PR target/92841 (Optimize -fstack-protector-strong code generation a bit)Jakub Jelinek1-3/+4
PR target/92841 * config/i386/i386.md (*stack_protect_set_3): For pic_32bit_operand always use lea{q}, no matter what value which_alternative has. * gcc.target/i386/pr92841-2.c: New test. From-SVN: r279633
2019-12-20re PR target/93002 (while(i--) optimization)Jakub Jelinek1-0/+30
PR target/93002 * config/i386/i386.md (dec reg; cmp $-1, reg; jne lab): New define_peephole2. * gcc.target/i386/pr93002.c: New test. From-SVN: r279632
2019-12-19Allow constants in amdgcn extends and truncatesAndrew Stubbs1-12/+12
2019-12-19 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>): Change input predcate to gcn_alu_operand. (extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>): Likewise. (truncv64di<mode>2): Likewise. (truncv64di<mode>2_exec): Likewise. (<convop><mode>v64di2): Likewise. (<convop><mode>v64di2_exec): Likewise. From-SVN: r279587
2019-12-19Use V64SI for all amdgcn add-with-carry insnsAndrew Stubbs1-7/+7
2019-12-19 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ... (*plus_carry_dpp_shr_v64si): ... this, and replace all VEC_1REG_INT_MODE with V64SI. From-SVN: r279584
2019-12-19[AArch64] Fix handling of npatterns>1 constants for partial SVE modesRichard Sandiford2-4/+21
For partial SVE vectors of element X, we want to treat duplicates of single X elements in the same way as for full vectors of X. But if a constant instead contains a repeating pattern of X elements, the transition from one value to the next must happen at container boundaries rather than element boundaries. E.g. a VNx4HI should in that case contain the same number of constants as a VNx4SI. Fixing this means that we need a reinterpret from the container-based mode to the partial mode; e.g. in the above example we need a reinterpret from VNx4SI to VNx4HI. We can't use subregs for that because they're forbidden by aarch64_can_change_class_mode; we should handle them in the same way as for big-endian instead. 2019-12-19 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): When handling partial SVE vectors, use the container mode rather than the element mode if the constant isn't a single-element duplicate. * config/aarch64/aarch64-sve.md (@aarch64_sve_reinterpret<mode>): Check targetm.can_change_mode_class instead of BYTES_BIG_ENDIAN. gcc/testsuite/ * gcc.target/aarch64/sve/mixed_size_9.c: New test. From-SVN: r279580
2019-12-19Implement sub-dword add/sub on amdgcnAndrew Stubbs1-16/+16
2019-12-19 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (addv64si3<exec_clobber>): Rename to ... (add<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. (addv64si3_dup<exec_clobber>): Rename to ... (add<mode>3_dup<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. (subv64si3<exec_clobber>): Rename to ... (sub<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. From-SVN: r279574
2019-12-19[AArch64] Reject invalid subregs involving partial SVE modesRichard Sandiford1-3/+22
When adding partial SVE modes, I'd remembered to handle reloads in a similar way to full big-endian SVE vectors, but forgot the just-as-important mode-change rules. 2019-12-19 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_can_change_mode_class): Don't allow changes between partial SVE modes and other kinds of mode. Don't allow changes between two partial SVE modes if they have different container or element sizes. gcc/testsuite/ * gcc.target/aarch64/sve/mixed_size_8.c: New test. From-SVN: r279572
2019-12-19[AArch64] Handle arguments and return types with partial SVE modesRichard Sandiford1-20/+75
Partial SVE modes can be picked up and used by the vector_size(N) attribute.[*] This means that we need to cope with arguments and return values with partial SVE modes, which previously triggered asserts like: /* Generic vectors that map to SVE modes with -msve-vector-bits=N are passed by reference, not by value. */ gcc_assert (!aarch64_sve_mode_p (mode)); The ABI for these types is fixed from pre-SVE days, and must in any case be the same for all -msve-vector-bits=N values. All we need to do is ensure that the vectors are passed and returned in the traditional way. [*] Advanced SIMD always wins for 64-bit and 128-bit vectors though. 2019-12-19 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_function_value_1): New function, split out from... (aarch64_function_value): ...here. Handle partial SVE modes by pretending that they have the associated/traditional integer mode, then wrap the result in the real mode. (aarch64_layout_arg): Take an orig_mode argument and pass it to aarch64_function_arg_alignment. Handle partial SVE modes analogously to aarch64_function_value. (aarch64_function_arg): Update call accordingly. (aarch64_function_arg_advance): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/pcs/gnu_vectors_3.c: New test. From-SVN: r279571
2019-12-18[AArch64] Fixup core tuningsWilco Dijkstra1-6/+6
Several tuning settings in cores.def are not consistent. Set the tuning for Cortex-A76AE and Cortex-A77 to neoversen1 so it is the same as for Cortex-A76 and Neoverse N1. Set the tuning for Neoverse E1 to cortexa73 so it's the same as for Cortex-A65. Set the scheduler for Cortex-A65 and Cortex-A65AE to cortexa53. gcc/ * config/aarch64/aarch64-cores.def: ("cortex-a76ae"): Use neoversen1 tuning. ("cortex-a77"): Likewise. ("cortex-a65"): Use cortexa53 scheduler. ("cortex-a65ae"): Likewise. ("neoverse-e1"): Use cortexa73 tuning. From-SVN: r279526
2019-12-18* config/avr/avr-mcus.def: Typo.Georg-Johann Lay1-21/+21
From-SVN: r279524
2019-12-17Generate PADDI to add large constants if -mcpu=future.Michael Meissner2-6/+9
2019-12-12 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/predicates.md (add_operand): Allow eI constants. * config/rs6000/rs6000.md (add<mode>3): Add alternative to generate PADDI for 34-bit constants if -mcpu=future. From-SVN: r279476
2019-12-17Use PLI to load up 32-bit SImode constants if -mcpu=future.Michael Meissner1-8/+8
2019-12-17 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/rs6000.md (movsi_internal1): Add alternative to use PLI to load up 32-bit constants if -mcpu=future. From-SVN: r279475
2019-12-17Use PLI to load up large constants if -mcpu=future.Michael Meissner2-6/+11
2019-12-17 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/rs6000.c (num_insns_constant_gpr): Return 1 if the constant can be loaded with PLI if -mcpu=future. * config/rs6000/rs6000.md (movdi_internal64): Add alternative to use PLI to load up 34-bit constants if -mcpu=future. From-SVN: r279474
2019-12-17re PR target/92841 (Optimize -fstack-protector-strong code generation a bit)Jakub Jelinek1-2/+100
PR target/92841 * config/i386/i386.md (@stack_protect_set_1_<mode>, @stack_protect_test_1_<mode>): Use output_asm_insn. (*stack_protect_set_2_<mode>, *stack_protect_set_3): New define_insns and corresponding define_peephole2s. * gcc.target/i386/pr92841.c: New test. From-SVN: r279468
2019-12-17[ARM] Add support for -mpure-code in thumb-1 (v6m)Christophe Lyon4-19/+147
This patch extends support for -mpure-code to all thumb-1 processors, by removing the need for MOVT. Symbol addresses are built using upper8_15, upper0_7, lower8_15 and lower0_7 relocations, and constants are built using sequences of movs/adds and lsls instructions. The extension of the *thumb1_movhf pattern uses always the same size (6) although it can emit a shorter sequence when possible. This is similar to what *arm32_movhf already does. CASE_VECTOR_PC_RELATIVE is now false with -mpure-code, to avoid generating invalid assembly code with differences from symbols from two different sections (the difference cannot be computed by the assembler). Tests pr45701-[12].c needed a small adjustment to avoid matching upper8_15 when looking for the r8 register. Test no-literal-pool.c is augmented with __fp16, so it now uses -mfp16-format=ieee. Test thumb1-Os-mult.c generates an inline code sequence with -mpure-code and computes the multiplication by using a sequence of add/shift rather than using the multiply instruction, so we skip it in presence of -mpure-code. With -mcpu=cortex-m0, the pure-code/no-literal-pool.c fails because code like: static char *p = "Hello World"; char * testchar () { return p + 4; } generates 2 indirections (I removed non-essential directives/code) .section .rodata .LC0: .ascii "Hello World\000" .data p: .word .LC0 .section .rodata .LC2: .word p .section .text,"0x20000006",%progbits testchar: push {r7, lr} add r7, sp, #0 movs r3, #:upper8_15:#.LC2 lsls r3, #8 adds r3, #:upper0_7:#.LC2 lsls r3, #8 adds r3, #:lower8_15:#.LC2 lsls r3, #8 adds r3, #:lower0_7:#.LC2 ldr r3, [r3] ldr r3, [r3] adds r3, r3, #4 movs r0, r3 mov sp, r7 @ sp needed pop {r7, pc} By contrast, when using -mcpu=cortex-m4, the code looks like: .section .rodata .LC0: .ascii "Hello World\000" .data p: .word .LC0 testchar: push {r7} add r7, sp, #0 movw r3, #:lower16:p movt r3, #:upper16:p ldr r3, [r3] adds r3, r3, #4 mov r0, r3 mov sp, r7 pop {r7} bx lr I haven't found yet how to make code for cortex-m0 apply upper/lower relocations to "p" instead of .LC2. The current code looks functional, but could be improved. 2019-10-18 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-protos.h (thumb1_gen_const_int): Add new prototype. * config/arm/arm.c (arm_option_check_internal): Remove restriction on MOVT for -mpure-code. (thumb1_gen_const_int): New function. (thumb1_legitimate_address_p): Support -mpure-code. (thumb1_rtx_costs): Likewise. (thumb1_size_rtx_costs): Likewise. (arm_thumb1_mi_thunk): Likewise. * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Likewise. * config/arm/thumb1.md (thumb1_movsi_symbol_ref): New. (*thumb1_movhf): Support -mpure-code. gcc/testsuite/ * gcc.target/arm/pr45701-1.c: Adjust for -mpure-code. * gcc.target/arm/pr45701-2.c: Likewise. * gcc.target/arm/pure-code/no-literal-pool.c: Add tests for __fp16. * gcc.target/arm/pure-code/pure-code.exp: Remove thumb2 and movt conditions. * gcc.target/arm/thumb1-Os-mult.c: Skip if -mpure-code is used. From-SVN: r279463
2019-12-17Add extract_last for amdgcnAndrew Stubbs1-0/+42
2019-12-17 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (extract_last_<mode>): New expander. (fold_extract_last_<mode>): New expander. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_vect_fold_extract_last): Add amdgcn. From-SVN: r279459
2019-12-17Add clz and ctz for amdgcnAndrew Stubbs2-2/+32
2019-12-17 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.h (CLZ_DEFINED_VALUE_AT_ZERO): Define. (CTZ_DEFINED_VALUE_AT_ZERO): Define. * config/gcn/gcn.md (s_mnemonic): Add clz and ctz. (expander): Likewise. (countzeros): New code iterator. (<expander>si2): New insn pattern. (<expander>di2): New insn pattern. From-SVN: r279458
2019-12-17Add abs pattern to handle {si,di} mode abs to avoid pmax/cmove conversion.Hongyu Wang3-0/+48
2019-12-17 Hongyu Wang <hongyu.wang@intel.com> gcc/ PR target/92651 * config/i386/i386.h (TARGET_EXPAND_ABS): New macro. * config/i386/x86-tune.def (X86_TUNE_EXPAND_ABS): New. * config/i386/i386.md (abs<SWI48x>2): New define_expand. gcc/testsuite * gcc.target/i386/pr92651.c: New testcase. From-SVN: r279452
2019-12-17Use add for a = a + b and a = b + a when possible.H.J. Lu1-9/+18
Since except for Bonnell, 01 fb add %edi,%ebx is faster and shorter than 8d 1c 1f lea (%rdi,%rbx,1),%ebx we should use add for a = a + b and a = b + a when possible if not optimizing for Bonnell. Tested on x86-64. 2019-12-17 H.J. Lu <hjl.tools@gmail.com> gcc/ PR target/92807 * config/i386/i386.c (ix86_lea_outperforms): Check !TARGET_BONNELL. (ix86_avoid_lea_for_addr): When not optimizing for Bonnell, use add for a = a + b and a = b + a. gcc/testsuite/ PR target/92807 * gcc.target/i386/pr92807-1.c: New test. From-SVN: r279451
2019-12-16rs6000: Use symbolic names for the CR fields in more casesSegher Boessenkool1-2/+2
It turns out we still used hardcoded register numbers for the CR fields in some cases, and they now use the wrong numbers since we renumbered most of the registers. So let's use the symbolic names, instead. * config/rs6000/rs6000.md (movsi_to_cr_one): Use CR0_REGNO instead of hardcoding the (old, expired) register number. (*mtcrfsi): Ditto. From-SVN: r279443
2019-12-16MSP430: Add new msp430-elfbare targetJozef Lawrynowicz3-2/+27
contrib/ChangeLog: 2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config-list.mk: Add msp430-elfbare. gcc/ChangeLog: 2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config.gcc: s/msp430*-*-*/msp430-*-*. Handle msp430-*-elfbare. * config/msp430/msp430-devices.c (TARGET_SUBDIR): Define. (_MSPMKSTR): Define. (__MSPMKSTR): Define. (rest_of_devices_path): Use TARGET_SUBDIR value in string. * config/msp430/msp430.c (msp430_option_override): Error if -fuse-cxa-atexit is used when it has been disabled at configure time. * config/msp430/t-msp430: Define TARGET_SUBDIR when building msp430-devices.o. * doc/install.texi: Document msp430-*-elf and msp430-*-elfbare. * doc/invoke.texi: Update documentation about which path devices.csv is searched for. gcc/testsuite/ChangeLog: 2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com> * g++.dg/init/dso_handle1.C: Require cxa_atexit support. * g++.dg/init/dso_handle2.C: Likewise. * g++.dg/other/cxa-atexit1.C: Likewise. * gcc.target/msp430/msp430.exp: Update csv-using-installed.c test to handle msp430-elfbare configuration. libgcc/ChangeLog: 2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config.host: s/msp430*-*-elf/msp430-*-elf*. Override default "extra_parts" variable. * configure: Regenerate. * configure.ac: Disable TM clone registry by default for msp430-elfbare. From-SVN: r279442
2019-12-16Fix PR92950: Wrong code emitted for movv1qiAndreas Krebbel1-7/+5
The backend emits 16 bit memory loads for single element character vector. As a result the character will not be right justified in the GPR. gcc/ChangeLog: 2019-12-16 Andreas Krebbel <krebbel@linux.ibm.com> PR target/92950 * config/s390/vector.md ("mov<mode>" for V_8): Replace lh, lhy, and lhrl with llc. gcc/testsuite/ChangeLog: 2019-12-16 Andreas Krebbel <krebbel@linux.ibm.com> PR target/92950 * gcc.target/s390/vector/pr92950.c: New test. From-SVN: r279410
2019-12-14[Darwin, PPC] Use Darwin9 bundle header for Rosetta builds.Iain Sandoe2-11/+14
On Darwin10 it's possible to make a 32b PPC build using the 'Rosetta' emulator. However, these builds need to make use of Darwin9 crts (for exes, dylibs and bundles). This adds the change to cater for bundles. gcc/ChangeLog: 2019-12-14 Iain Sandoe <iain@sandoe.co.uk> * config/darwin.h (DARWIN_EXTRA_SPECS): Add new bundle spec. (DARWIN_BUNDLE1_SPEC): New. (STARTFILE_SPEC): Use darwin bundle spec. * config/rs6000/darwin.h (DARWIN_BUNDLE1_SPEC): New. (DARWIN_DYLIB1_SPEC): Delete duplicate. From-SVN: r279393
2019-12-13[Darwin, PPC] Use Darwin9 dylib header for Rosetta builds.Iain Sandoe1-0/+6
On Darwin10 it's possible to make a 32b PPC build using the 'Rosetta' emulator. However, these builds need to make use of Darwin9 crts (for exes and dylibs). This adds the change to cater for dylibs. gcc/ChangeLog: 2019-12-13 Iain Sandoe <iain@sandoe.co.uk> * config/rs6000/darwin.h (DARWIN_DYLIB1_SPEC): New. From-SVN: r279381
2019-12-13Sub-dword vector multiply for amdgcnAndrew Stubbs1-11/+11
2019-12-13 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (mulv64si3<exec>): Rename to ... (mul<mode>3<exec>): ... this, and implement sub-dword patterns. (mulv64si3_dup<exec>): Rename to ... (mul<mode>3_dup<exec>): ... this, and implement sub-dword patterns. From-SVN: r279374
2019-12-13Sub-dword vector extend and truncate for amdgcnAndrew Stubbs2-34/+142
2019-12-13 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (sdwa): New mode attribute. (VCVT_FROM_MODE): Rename to ... (VCVT_MODE): ... this. (VCVT_TO_MODE): Delete mode iterator. (VCVT_FMODE): New mode iterator. (VCVT_IMODE): Likewise. (<cvt_name><VCVT_FROM_MODE:mode><VCVT_TO_MODE:mode>2<exec>): Change ... (<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): ... to this. (<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): New. (zero_convert): New code iterator. (convop): New code attribute. (<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>) : New. (extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>) : New. (vec_truncatev64div64si): Rename to ... (truncv64di<mode>2): ... this and implement sub-dword patterns. (vec_truncatev64div64si_exec): Rename to ... (truncv64di<mode>2_exec): ... this and implement sub-dword patterns. (<convop><mode>v64di2): New insn_and_split. (<convop><mode>v64di2_exec): Likewise. (mask_gather_load<mode>): Update truncate names. (mask_scatter_store<mode>): Likewise. * config/gcn/gcn.c (gcn_expand_scaled_offsets): Update truncate names. From-SVN: r279372
2019-12-13[AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16Dennis Zhang4-6/+47
2019-12-13 Dennis Zhang <dennis.zhang@arm.com> gcc/ * config/aarch64/aarch64-arches.def (armv8.6-a): New. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled. * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New. (fp): Disabling fp also disables i8mm and bf16. (simd): Disabling simd also disables i8mm. * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro. (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise. (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise. (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options and add a new table to list permissible values for ARCH. gcc/testsuite/ * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm and bf16 features. From-SVN: r279370
2019-12-13[rs6000] Adjust vectorization cost for scalar COND_EXPRKewen Lin1-0/+24
We found that the vectorization cost modeling on scalar COND_EXPR is a bit off on rs6000. One typical case is 548.exchange2_r, -Ofast -mcpu=power9 -mrecip -fvect-cost-model=unlimited is better than -Ofast -mcpu=power9 -mrecip (the default is -fvect-cost-model=dynamic) by 1.94%. Scalar COND_EXPR is expanded into compare + branch or compare + isel normally, either of them should be priced more than the simple FXU operation. This patch is to add additional vectorization cost onto scalar COND_EXPR on top of builtin_vectorization_cost. The idea to use additional cost value 2 instead of the others: 1) try various possible value candidates from 1 to 5, 2 is the best measured on Power9. 2) from latency view, compare takes 3 cycles and isel takes 2 on Power9, it's 2.5 times of simple FXU instruction which takes cost 1 in the current modeling, it's close. 3) get fine SPEC2017 ratio on Power8 as well. gcc/ChangeLog * config/rs6000/rs6000.c (adjust_vectorization_cost): New function. (rs6000_add_stmt_cost): Call adjust_vectorization_cost and update stmt_cost. From-SVN: r279336
2019-12-13re PR target/92904 (varargs for __int128 is placed at an unaligned location ↵Jakub Jelinek1-0/+6
and uses movdqa for the load) PR target/92904 * config/i386/i386.c (ix86_gimplify_va_arg): If need_intregs and not need_temp, decrease alignment of the read because the GPR save area only guarantees 8-byte alignment. * gcc.c-torture/execute/pr92904.c: New test. From-SVN: r279327
2019-12-12Add support for some more AVR devices from avrxmega3 family.Georg-Johann Lay1-0/+11
* config/avr/avr-mcus.def (attiny1604, attiny1606, attiny1607) (attiny402, attiny404, attiny406) (attiny804, attiny806, attiny807) (attiny202, attiny204): Add AVR_MCU lines to support them. * doc/avr-mmcu.texi: Regenerate. From-SVN: r279309
2019-12-12[ARC] generate signaling FDCMPF for hard float comparisonsVineet Gupta5-3/+33
PR 92846: ARC gcc generates FDCMP instructions which raises Invalid operation for signaling NaN only. This causes glibc iseqsig() primitives to fail (in the current ongoing glibc port to ARC) So break up the hard float compares into tw categories and for unordered compares generate the FDCMPF instructions which raised exception for either NaNs. With this fix testsuite/gcc.dg/torture/pr52451.c passes for ARC. Also no regressions for the glibc math testsuite, only 6 additional passes for test*iseqsig gcc/ xxxx-xx-xx Vineet Gupta <vgupta@synopsys.com> * config/arc/arc-modes.def (CC_FPUE): New Mode CC_FPUE which helps codegen generate exceptions even for quiet NaN. * config/arc/arc.c (arc_init_reg_tables): Handle New CC_FPUE mode. (get_arc_condition_code): Likewise. (arc_select_cc_mode): LT, LE, GT, GE to use the New CC_FPUE mode. * config/arc/arc.h (REVERSE_CONDITION): Handle New CC_FPUE mode. * config/arc/predicates.md (proper_comparison_operator): Likewise. * config/arc/fpu.md (cmpsf_fpu_trap): New Pattern for CC_FPUE. (cmpdf_fpu_trap): Likewise. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> From-SVN: r279274
2019-12-12[ARC] Use hardware support for double-precision compare instructions.Claudiu Zissulescu1-2/+2
Allow the compiler to use the double-precision compare instructions. xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (iterator SDF): Check TARGET_FP_DP_BASE. (cstoredi4): Use TARGET_HARD_FLOAT. From-SVN: r279273
2019-12-11MSP430: Add -fno-exceptions multilibJozef Lawrynowicz2-6/+14
ChangeLog: 2019-12-11 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config-ml.in (msp430-*-*): Support --disable-no-exceptions configure flag. gcc/ChangeLog: 2019-12-11 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/msp430/msp430.h (STARTFILE_SPEC) [!fexceptions]: Use crtbegin_no_eh.o if building for the C language. [fno-exceptions]: Use crtbegin_no_eh.o if building for any language except C. (ENDFILE_SPEC) [!fexceptions]: Use crtend_no_eh.o if building for the C language. [fno-exceptions]: Use crtend_no_eh.o if building for any language except C. * config/msp430/t-msp430: Add -fno-exceptions multilib. * doc/install.texi: Document --disable-no-exceptions multilib configure option. * doc/sourcebuild.texi: Document exceptions_enabled effective target. gcc/testsuite/ChangeLog: 2019-12-11 Jozef Lawrynowicz <jozef.l@mittosystems.com> * lib/gcc-dg.exp: Add dg-prune messages for when exception handling is disabled. * lib/target-supports.exp (check_effective_target_exceptions_enabled): New. libgcc/ChangeLog: 2019-12-11 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config.host: Add crt{begin,end}_no_eh.o to "extra_parts". * config.host (msp430*-*-elf): Add crt{begin,end}_no_eh.o to "extra_parts". From-SVN: r279246
2019-12-11arm: Fix an incorrect warning when -mcpu=cortex-a55 is used with ↵Richard Earnshaw2-28/+41
-mfloat-abi=soft When a CPU such as cortex-a55 is used with the soft-float ABI variant, the compiler is incorrectly issuing a warning about a mismatch between the architecture (generated internally) and the CPU. This is not expected or intended. The problem stems from the fact that we generate (correctly) an architecture for a soft-float compilation, but then try to compare it against the one recorded for the CPU. Normally we strip out the floating point information before doing that comparison, but we currently only do that for the features that can be affected by the -mfpu option. For a soft-float environment we also need to strip out any bits that depend on having floating-point present. So this patch implements that and does a bit of housekeeping at the same time: - in arm-cpus.in it is not necessary for a CPU to specify both +dotprod and +simd in its architecture specification, since +dotprod implies +simd. - I've refactored the ALL_SIMD fgroup in arm-cpus.in to create a new subgroup ALL_SIMD_EXTERNAL and containing the bits that were previously added directly to ALL_SIMD. Similarly, I've added an ALL_FPU_EXTERNAL subgroup. - in arm.c rename fpu_bitlist and all_fpubits to fpu_bitlist_internal and all_fpubits_internal for consistency with the fgroup bits which they contain. * config/arm/arm-cpus.in (ALL_SIMD_EXTERNAL): New fgroup. (ALL_SIMD): Use it. (ALL_FPU_EXTERNAL): New fgroup. (ALL_FP): Use it. (cortex-a55, cortex-a75, cortex-a76, cortex-a76ae): Remove redundant +simd from architecture specification. (cortex-a77, neoverse-n1, cortex-a75.cortex-a55): Likewise. * config/arm/arm.c (isa_all_fpubits, fpu_bitlist): Rename to ... (isa_all_fpubits_internal, fpu_bitlist_internal): ... these. (isa_all_fpbits): New bitmap. (arm_option_override): Initialize it. (arm_configure_build_target): If the target isa does not have any FP enabled, do not warn about mismatches in FP-related feature bits. From-SVN: r279219
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