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2014-05-06* config/i386/sse.md (*mov<mode>_internal)Joseph Myers1-13/+20
(*<sse>_loadu<ssemodesuffix><avxsizesuffix><mask_name>) (*<sse2_avx_avx512f>_loaddqu<mode><mask_name>) (<sse>_andnot<mode>3, <code><mode>3, *andnot<mode>3) (*<code><mode>3, *andnot<mode>3<mask_name>) (<mask_codefor><code><mode>3<mask_name>): Only consider TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL for modes of size 16. From-SVN: r210124
2014-05-06Merge in wide-int.Kenneth Zadeck18-170/+167
From-SVN: r210113
2014-05-06avr.c (avr_can_eliminate): Mark unused argument.Jan-Benedict Glaw1-1/+1
2014-05-06 Jan-Benedict Glaw <jbglaw@lug-owl.de> * config/avr/avr.c (avr_can_eliminate): Mark unused argument. From-SVN: r210108
2014-05-06tree-pass.h (TODO_verify_ssa, [...]): Remove.Richard Biener6-7/+5
2014-05-06 Richard Biener <rguenther@suse.de> * tree-pass.h (TODO_verify_ssa, TODO_verify_flow, TODO_verify_stmts, TODO_verify_rtl_sharing): Remove. (TODO_verify_all): Adjust. * asan.c: Remove references to TODO_verify_ssa, TODO_verify_flow, TODO_verify_stmts and TODO_verify_rtl_sharing. * bb-reorder.c: Likewise. * cfgexpand.c: Likewise. * cprop.c: Likewise. * cse.c: Likewise. * function.c: Likewise. * fwprop.c: Likewise. * gcse.c: Likewise. * gimple-ssa-isolate-paths.c: Likewise. * gimple-ssa-strength-reduction.c: Likewise. * ipa-split.c: Likewise. * loop-init.c: Likewise. * loop-unroll.c: Likewise. * lower-subreg.c: Likewise. * modulo-sched.c: Likewise. * postreload-gcse.c: Likewise. * predict.c: Likewise. * recog.c: Likewise. * sched-rgn.c: Likewise. * store-motion.c: Likewise. * tracer.c: Likewise. * trans-mem.c: Likewise. * tree-call-cdce.c: Likewise. * tree-cfg.c: Likewise. * tree-cfgcleanup.c: Likewise. * tree-complex.c: Likewise. * tree-eh.c: Likewise. * tree-emutls.c: Likewise. * tree-if-conv.c: Likewise. * tree-into-ssa.c: Likewise. * tree-loop-distribution.c: Likewise. * tree-object-size.c: Likewise. * tree-parloops.c: Likewise. * tree-pass.h: Likewise. * tree-sra.c: Likewise. * tree-ssa-ccp.c: Likewise. * tree-ssa-copy.c: Likewise. * tree-ssa-copyrename.c: Likewise. * tree-ssa-dce.c: Likewise. * tree-ssa-dom.c: Likewise. * tree-ssa-dse.c: Likewise. * tree-ssa-forwprop.c: Likewise. * tree-ssa-ifcombine.c: Likewise. * tree-ssa-loop-ch.c: Likewise. * tree-ssa-loop-ivcanon.c: Likewise. * tree-ssa-loop.c: Likewise. * tree-ssa-math-opts.c: Likewise. * tree-ssa-phiopt.c: Likewise. * tree-ssa-phiprop.c: Likewise. * tree-ssa-pre.c: Likewise. * tree-ssa-reassoc.c: Likewise. * tree-ssa-sink.c: Likewise. * tree-ssa-strlen.c: Likewise. * tree-ssa-tail-merge.c: Likewise. * tree-ssa-uncprop.c: Likewise. * tree-switch-conversion.c: Likewise. * tree-tailcall.c: Likewise. * tree-vect-generic.c: Likewise. * tree-vectorizer.c: Likewise. * tree-vrp.c: Likewise. * tsan.c: Likewise. * var-tracking.c: Likewise. * bt-load.c: Likewise. * cfgcleanup.c: Likewise. * combine-stack-adj.c: Likewise. * combine.c: Likewise. * compare-elim.c: Likewise. * config/epiphany/resolve-sw-modes.c: Likewise. * config/i386/i386.c: Likewise. * config/mips/mips.c: Likewise. * config/s390/s390.c: Likewise. * config/sh/sh_treg_combine.cc: Likewise. * config/sparc/sparc.c: Likewise. * dce.c: Likewise. * dse.c: Likewise. * final.c: Likewise. * ifcvt.c: Likewise. * mode-switching.c: Likewise. * passes.c: Likewise. * postreload.c: Likewise. * ree.c: Likewise. * reg-stack.c: Likewise. * regcprop.c: Likewise. * regrename.c: Likewise. * web.c: Likewise. From-SVN: r210106
2014-05-05picochip-protos.h (picochip_regno_nregs): Change int argument to enum ↵Jan-Benedict Glaw2-4/+4
machine_mode. 2014-05-05 Jan-Benedict Glaw <jbglaw@lug-owl.de> * config/picochip/picochip-protos.h (picochip_regno_nregs): Change int argument to enum machine_mode. (picochip_class_max_nregs): Ditto. * config/picochip/picochip.c (picochip_regno_nregs): Ditto. (picochip_class_max_nregs): Ditto. From-SVN: r210065
2014-05-05target.def: Add new target hook.Andreas Krebbel1-0/+11
2014-05-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * target.def: Add new target hook. * doc/tm.texi: Regenerate. * targhooks.h (default_keep_leaf_when_profiled): Add prototype. * targhooks.c (default_keep_leaf_when_profiled): New function. * config/s390/s390.c (s390_keep_leaf_when_profiled): New function. (TARGET_KEEP_LEAF_WHEN_PROFILED): Define. 2014-05-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gcc.target/s390/leaf-profile.c: New testcase. From-SVN: r210061
2014-05-04rs6000.h (RS6000_BTM_HARD_FLOAT): New define.Peter Bergner3-6/+23
gcc/ * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define. (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT. (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT. * config/rs6000/rs6000-builtin.def (BU_MISC_1): Use RS6000_BTM_HARD_FLOAT. (BU_MISC_2): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle RS6000_BTM_HARD_FLOAT. (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp is explicitly used. (rs6000_invalid_builtin): Add hard floating builtin support. (rs6000_expand_builtin): Relax the gcc_assert to allow the new hard float builtins. (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT. gcc/testsuite/ * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float. (dg-require-effective-target): Change target to powerpc_fprs. * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp. (dg-require-effective-target): Change target to dfprt. From-SVN: r210054
2014-05-03sh_optimize_sett_clrt.cc (sh_optimize_sett_clrt::execute): Add missing ↵Oleg Endo1-5/+5
function* argument. * config/sh/sh_optimize_sett_clrt.cc (sh_optimize_sett_clrt::execute): Add missing function* argument. From-SVN: r210040
2014-05-03mips.c (mips_isa_rev): New variable.Richard Sandiford2-57/+29
gcc/ * config/mips/mips.c (mips_isa_rev): New variable. (mips_set_architecture): Set it. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Set __mips_isa_rev from mips_isa_rev. (ISA_HAS_MUL3, ISA_HAS_FP_CONDMOVE, ISA_HAS_8CC, ISA_HAS_FP4) (ISA_HAS_PAIRED_SINGLE, ISA_HAS_MADD_MSUB, ISA_HAS_FP_RECIP_RSQRT) (ISA_HAS_CLZ_CLO, ISA_HAS_ROR, ISA_HAS_WSBH, ISA_HAS_PREFETCH) (ISA_HAS_SEB_SEH, ISA_HAS_EXT_INS, ISA_HAS_MXHC1) (ISA_HAS_HILO_INTERLOCKS, ISA_HAS_SYNCI, MIN_FPRS_PER_FMT): Reexpress conditions in terms of mips_isa_rev. (mips_isa_rev): Declare. From-SVN: r210038
2014-05-03sh-mem.cc: Use tabs instead of spaces.Oleg Endo1-149/+146
* config/sh/sh-mem.cc: Use tabs instead of spaces. (prob_unlikely, prob_likely): Make variables const. From-SVN: r210037
2014-05-03avr.c (avr_adjust_insn_length): Handle JUMP_TABLE_DATA.Denis Chertykov1-2/+2
* config/avr/avr.c (avr_adjust_insn_length): Handle JUMP_TABLE_DATA. From-SVN: r210035
2014-05-03sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases.Oleg Endo1-0/+16
* config/sh/sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases. From-SVN: r210033
2014-05-03sh.h (ROUND_ADVANCE): Delete macro.Oleg Endo2-58/+67
* config/sh/sh.h (ROUND_ADVANCE): Delete macro. (ROUND_REG, PASS_IN_REG_P): Move and rename macros to ... * config/sh/sh.c (sh_round_reg, sh_pass_in_reg_p): ... these new functions. (sh_arg_partial_bytes, sh_function_arg, sh_function_arg_advance, sh_setup_incoming_varargs): Replace usage of PASS_IN_REG_P with sh_pass_in_reg_p. Replace usage of ROUND_REG with sh_round_reg. Use CEIL instead of ROUND_ADVANCE. From-SVN: r210032
2014-05-03re PR target/61026 (sh-rtems4.11 build of 4.9.0 fails on FreeBSD 10 c++ ↵Oleg Endo1-4/+4
(clang).) PR target/61026 * config/sh/sh.c: Include stdlib headers before everything else. From-SVN: r210028
2014-05-02One-line tidy of bit-twiddle expression in aarch64.cAlan Lawrence1-1/+2
* config/aarch64/aarch64.c (aarch64_expand_vec_perm_1): Tidy bit-flip expression. From-SVN: r210005
2014-05-02defaults.h (HONOR_REG_ALLOC_ORDER): Change HONOR_REG_ALLOC_ORDER to a C ↵Kito Cheng2-2/+2
expression marco. 2014-02-26 Kito Cheng <kito@0xlab.org> * defaults.h (HONOR_REG_ALLOC_ORDER): Change HONOR_REG_ALLOC_ORDER to a C expression marco. * ira-color.c (HONOR_REG_ALLOC_ORDER) : Ditto. * config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Ditto. * config/nds32/nds32.h (HONOR_REG_ALLOC_ORDER): Ditto. * doc/tm.texi (HONOR_REG_ALLOC_ORDER): Update document for HONOR_REG_ALLOC_ORDER. * doc/tm.texi.in (HONOR_REG_ALLOC_ORDER): Ditto. From-SVN: r210000
2014-05-01arc.c (TARGET_LRA_P): Undef before redefine.Jan-Benedict Glaw1-0/+1
2014-05-01 Jan-Benedict Glaw <jbglaw@lug-owl.de> * config/arc/arc.c (TARGET_LRA_P): Undef before redefine. From-SVN: r209979
2014-05-01arc.c (arc_select_cc_mode): Fix typo.Jan-Benedict Glaw1-1/+1
2014-05-01 Jan-Benedict Glaw <jbglaw@lug-owl.de> * config/arc/arc.c (arc_select_cc_mode): Fix typo. From-SVN: r209978
2014-04-30Rewrite AArch64 UZP Intrinsics using __builtin_shuffle.Alan Lawrence1-461/+432
gcc/testsuite/ChangeLog: * gcc.target/aarch64/vuzps32_1.c: Expect zip1/2 insn rather than uzp1/2. * gcc.target/aarch64/vuzpu32_1.c: Likewise. * gcc.target/aarch64/vuzpf32_1.c: Likewise. gcc/ChangeLog: * config/aarch64/arm_neon.h (vuzp1_f32, vuzp1_p8, vuzp1_p16, vuzp1_s8, vuzp1_s16, vuzp1_s32, vuzp1_u8, vuzp1_u16, vuzp1_u32, vuzp1q_f32, vuzp1q_f64, vuzp1q_p8, vuzp1q_p16, vuzp1q_s8, vuzp1q_s16, vuzp1q_s32, vuzp1q_s64, vuzp1q_u8, vuzp1q_u16, vuzp1q_u32, vuzp1q_u64, vuzp2_f32, vuzp2_p8, vuzp2_p16, vuzp2_s8, vuzp2_s16, vuzp2_s32, vuzp2_u8, vuzp2_u16, vuzp2_u32, vuzp2q_f32, vuzp2q_f64, vuzp2q_p8, vuzp2q_p16, vuzp2q_s8, vuzp2q_s16, vuzp2q_s32, vuzp2q_s64, vuzp2q_u8, vuzp2q_u16, vuzp2q_u32, vuzp2q_u64): Replace temporary asm with __builtin_shuffle. From-SVN: r209943
2014-04-30arc.opt (mlra): Move comment above option name to avoid mis-parsing as ↵Joern Rennecke1-1/+1
language options. * config/arc/arc.opt (mlra): Move comment above option name to avoid mis-parsing as language options. From-SVN: r209939
2014-04-30Simplify Solaris 2 configurationRainer Orth8-345/+205
* config/sol2-10.h (TARGET_LIBC_HAS_FUNCTION): Move ... * config/sol2.h: ... here. * config/sol2-10.h: Remove. * config/sol2-bi.h (WCHAR_TYPE, WCHAR_TYPE_SIZE, WINT_TYPE) (WINT_TYPE_SIZE, MULTILIB_DEFAULTS, DEF_ARCH32_SPEC) (DEF_ARCH64_SPEC, ASM_CPU_DEFAULT_SPEC, LINK_ARCH64_SPEC_BASE) (LINK_ARCH64_SPEC, ARCH_DEFAULT_EMULATION, TARGET_LD_EMULATION) (LINK_ARCH_SPEC, SUBTARGET_EXTRA_SPECS): Move ... * config/sol2.h: ... here. (SECTION_NAME_FORMAT): Don't redefine. (STARTFILE_ARCH32_SPEC): Rename to ... (STARTFILE_ARCH_SPEC): ... this. (ASM_OUTPUT_ALIGNED_COMMON): Move ... * config/sparc/sol2.h: ... here. (SECTION_NAME_FORMAT): Don't undef. * config/i386/sol2.h (ASM_CPU_DEFAULT_SPEC) (SUBTARGET_EXTRA_SPECS): Remove. * config/sparc/sol2.h (ASM_CPU_DEFAULT_SPEC): Remove. * config/i386/sol2-bi.h (TARGET_SUBTARGET_DEFAULT) (MD_STARTFILE_PREFIX): Remove. (SUBTARGET_OPTIMIZATION_OPTIONS, ASM_CPU32_DEFAULT_SPEC) (ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC, ASM_SPEC, DEFAULT_ARCH32_P) (ARCH64_SUBDIR, ARCH32_EMULATION, ARCH64_EMULATION) (ASM_COMMENT_START, JUMP_TABLES_IN_TEXT_SECTION) (ASM_OUTPUT_DWARF_PCREL, ASM_OUTPUT_ALIGNED_COMMON) (USE_IX86_FRAME_POINTER, USE_X86_64_FRAME_POINTER): Move ... * config/i386/sol2.h: ... here. (TARGET_SUBTARGET_DEFAULT, SIZE_TYPE, PTRDIFF_TYPE): Remove. * config/i386/sol2-bi.h: Remove. * config/sol2.h (MD_STARTFILE_PREFIX): Remove. (LINK_ARCH32_SPEC_BASE): Remove /usr/ccs/lib/libp, /usr/ccs/lib. * config/i386/t-sol2-64: Rename to ... * config/i386/t-sol2: ... this. * config/sparc/t-sol2-64: Rename to ... * config/sparc/t-sol2: ... this. * config.gcc (*-*-solaris2*): Split sol2_tm_file into sol2_tm_file_head, sol2_tm_file_tail. Include ${cpu_type}/sol2.h before sol2.h. Remove sol2-10.h. (i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*): Include i386/x86-64.h between sol2_tm_file_head and sol2_tm_file_tail. Remove i386/sol2-bi.h, sol2-bi.h from tm_file. Reflect i386/t-sol2-64 renaming. (sparc*-*-solaris2*): Remove sol2-bi.h from tm_file. Reflect sparc/t-sol2-64 renaming. From-SVN: r209931
2014-04-29arm_neon.h (vzip1_f32, [...]): Replace inline __asm__ with __builtin_shuffle.Alan Lawrence1-462/+438
* config/aarch64/arm_neon.h (vzip1_f32, vzip1_p8, vzip1_p16, vzip1_s8, vzip1_s16, vzip1_s32, vzip1_u8, vzip1_u16, vzip1_u32, vzip1q_f32, vzip1q_f64, vzip1q_p8, vzip1q_p16, vzip1q_s8, vzip1q_s16, vzip1q_s32, vzip1q_s64, vzip1q_u8, vzip1q_u16, vzip1q_u32, vzip1q_u64, vzip2_f32, vzip2_p8, vzip2_p16, vzip2_s8, vzip2_s16, vzip2_s32, vzip2_u8, vzip2_u16, vzip2_u32, vzip2q_f32, vzip2q_f64, vzip2q_p8, vzip2q_p16, vzip2q_s8, vzip2q_s16, vzip2q_s32, vzip2q_s64, vzip2q_u8, vzip2q_u16, vzip2q_u32, vzip2q_u64): Replace inline __asm__ with __builtin_shuffle. From-SVN: r209906
2014-04-29msp430.md (umulsidi): Fix typo.Nick Clifton2-3/+3
* config/msp430/msp430.md (umulsidi): Fix typo. (mulhisi3): Enable even inside interrupt handlers. * config/msp430/msp430.c (msp430_print_operand): %O: Allow for the bigger return address pushed in large mode. From-SVN: r209898
2014-04-29arc.c (arc_select_cc_mode): Fix parentheses.Nick Clifton3-20/+24
* config/arc/arc.c (arc_select_cc_mode): Fix parentheses. (arc_init_reg_tables): Use a machine_mode enum to iterate over available modes. * config/m32r/m32r.c (init_reg_tables): Likewise. * config/m32c/m32c.c (m32c_illegal_subreg_p): Use a machine_mode enum to hold the modes. From-SVN: r209894
2014-04-29aarch64.md (mov<mode>cc): New for GPF.Zhenqiang Chen1-0/+19
2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org> * config/aarch64/aarch64.md (mov<mode>cc): New for GPF. 2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org> * gcc.target/aarch64/fcsel_1.c: New test case. From-SVN: r209889
2014-04-28[AArch64] Improve vst4_lane intrinsicsJames Greenhalgh6-125/+340
gcc/ * config/aarch64/aarch64-builtins.c (aarch64_types_storestruct_lane_qualifiers): New. (TYPES_STORESTRUCT_LANE): Likewise. * config/aarch64/aarch64-simd-builtins.def (st2_lane): New. (st3_lane): Likewise. (st4_lane): Likewise. * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New. (vec_store_lanesci_lane<mode>): Likewise. (vec_store_lanesxi_lane<mode>): Likewise. (aarch64_st2_lane<VQ:mode>): Likewise. (aarch64_st3_lane<VQ:mode>): Likewise. (aarch64_st4_lane<VQ:mode>): Likewise. * config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE. * config/aarch64/arm_neon.h (__ST2_LANE_FUNC): Rewrite using builtins, update use points to use new macro arguments. (__ST3_LANE_FUNC): Likewise. (__ST4_LANE_FUNC): Likewise. * config/aarch64/iterators.md (V_TWO_ELEM): New. (V_THREE_ELEM): Likewise. (V_FOUR_ELEM): Likewise. From-SVN: r209880
2014-04-28[AArch64] Relax modes_tieable_p and cannot_change_mode_classJames Greenhalgh3-3/+35
gcc/ * config/aarch64/aarch64-protos.h (aarch64_modes_tieable_p): New. * config/aarch64/aarch64.c (aarch64_cannot_change_mode_class): Weaken conditions. (aarch64_modes_tieable_p): New. * config/aarch64/aarch64.h (MODES_TIEABLE_P): Use it. From-SVN: r209878
2014-04-28sync.md (AINT mode_iterator): Move definition.Pat Haugen3-17/+93
* config/rs6000/sync.md (AINT mode_iterator): Move definition. (loadsync_<mode>): Change mode. (load_quadpti, store_quadpti): New. (atomic_load<mode>, atomic_store<mode>): Add support for TI mode. * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. From-SVN: r209873
2014-04-28configure.ac: Tweak GAS check for LEON instructions on SPARC.Eric Botcazou2-1/+22
* configure.ac: Tweak GAS check for LEON instructions on SPARC. * configure: Regenerate. * config/sparc/sparc.opt (muser-mode): New option. * config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable for LEON3. (atomic_compare_and_swap_leon3_1): New instruction for LEON3. * doc/invoke.texi (SPARC options): Document -muser-mode. From-SVN: r209850
2014-04-26Fix out-of-bounds array accesses in ldexpxf3.Tom de Vries1-5/+6
2014-04-26 Tom de Vries <tom@codesourcery.com> * config/i386/i386.md (define_expand "ldexpxf3"): Fix out-of-bounds array accesses. From-SVN: r209824
2014-04-25Set MODE to SI for alternative 12 in *movsf_internalH.J. Lu1-1/+1
PR target/60969 * config/i386/i386.md (*movsf_internal): Set MODE to SI for alternative 12. From-SVN: r209811
2014-04-25[ARM] Enable tail call optimization for long callJiong Wang3-10/+10
gcc/ * config/arm/predicates.md (call_insn_operand): Add long_call check. * config/arm/arm.md (sibcall, sibcall_value): Force the address to reg for long_call. * config/arm/arm.c (arm_function_ok_for_sibcall): Remove long_call restriction. gcc/testsuite * gcc.target/arm/tail-long-call.c: New test. From-SVN: r209808
2014-04-25[ARM] Initialise T16-related fields in Cortex-A8 tuning struct.Kyrylo Tkachov1-1/+2
* config/arm/arm.c (arm_cortex_a8_tune): Initialise T16-related fields. From-SVN: r209806
2014-04-25[ARM] Wrap long literals in HOST_WIDE_INT_C in aarch-common.cKyrylo Tkachov1-2/+6
* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): Use HOST_WIDE_INT_C for mask literal. (aarch_rev16_shleft_mask_imm_p): Likewise. From-SVN: r209797
2014-04-25re PR target/60941 (miscompilation of firefox javascript interpreter)Eric Botcazou1-13/+0
PR target/60941 * config/sparc/sparc.md (ashlsi3_extend): Delete. From-SVN: r209790
2014-04-25re PR target/56540 (No __SIZEOF__XXX__ macro for __float128)Marc Glisse1-0/+7
2014-04-25 Marc Glisse <marc.glisse@inria.fr> PR preprocessor/56540 * config/i386/i386-c.c (ix86_target_macros): Define __SIZEOF_FLOAT80__ and __SIZEOF_FLOAT128__. From-SVN: r209789
2014-04-25Remove LIB_TLS_SPEC on SolarisRainer Orth1-1/+0
* configure.ac (tga_func): Remove. (LIB_TLS_SPEC): Remove. * configure: Regenerate. * config.in: Regenerate. * config/sol2.h (LIB_SPEC): Don't use LIB_TLS_SPEC. From-SVN: r209785
2014-04-24extend.texi (PowerPC Built-in Functions): Document new powerpc extended ↵Michael Meissner7-15/+606
divide, bcd, pack/unpack 128-bit, builtin functions. [gcc] 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> * doc/extend.texi (PowerPC Built-in Functions): Document new powerpc extended divide, bcd, pack/unpack 128-bit, builtin functions. (PowerPC AltiVec/VSX Built-in Functions): Likewise. * config/rs6000/predicates.md (const_0_to_3_operand): New predicate to match 0..3 integer constants. * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros to support adding miscellaneous builtin functions. (BU_DFP_MISC_2): Likewise. (BU_P7_MISC_1): Likewise. (BU_P7_MISC_2): Likewise. (BU_P8V_MISC_3): Likewise. (BU_MISC_1): Likewise. (BU_MISC_2): Likewise. (DIVWE): Add extended divide builtin functions. (DIVWEO): Likewise. (DIVWEU): Likewise. (DIVWEUO): Likewise. (DIVDE): Likewise. (DIVDEO): Likewise. (DIVDEU): Likewise. (DIVDEUO): Likewise. (DXEX): Add decimal floating-point builtin functions. (DXEXQ): Likewise. (DDEDPD): Likewise. (DDEDPDQ): Likewise. (DENBCD): Likewise. (DENBCDQ): Likewise. (DIEX): Likewise. (DIEXQ): Likewise. (DSCLI): Likewise. (DSCLIQ): Likewise. (DSCRI): Likewise. (DSCRIQ): Likewise. (CDTBCD): Add new BCD builtin functions. (CBCDTD): Likewise. (ADDG6S): Likewise. (BCDADD): Likewise. (BCDADD_LT): Likewise. (BCDADD_EQ): Likewise. (BCDADD_GT): Likewise. (BCDADD_OV): Likewise. (BCDSUB): Likewise. (BCDSUB_LT): Likewise. (BCDSUB_EQ): Likewise. (BCDSUB_GT): Likewise. (BCDSUB_OV): Likewise. (PACK_TD): Add new pack/unpack 128-bit type builtin functions. (UNPACK_TD): Likewise. (PACK_TF): Likewise. (UNPACK_TF): Likewise. (UNPACK_TF_0): Likewise. (UNPACK_TF_1): Likewise. (PACK_V1TI): Likewise. (UNPACK_V1TI): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add support for decimal floating point builtin functions. (rs6000_expand_ternop_builtin): Add checks for the new builtin functions that take constant arguments. (rs6000_invalid_builtin): Add decimal floating point builtin support. (rs6000_init_builtins): Setup long double, _Decimal64, and _Decimal128 types for new builtin functions. (builtin_function_type): Set the unsigned flags appropriately for the new builtin functions. (rs6000_opt_masks): Add support for decimal floating point builtin functions. * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal floating point builtin functions. (RS6000_BTM_COMMON): Likewise. (RS6000_BTI_long_double): Likewise. (RS6000_BTI_dfloat64): Likewise. (RS6000_BTI_dfloat128): Likewise. (long_double_type_internal_node): Likewise. (dfloat64_type_internal_node): Likewise. (dfloat128_type_internal_node): Likewise. * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA 2.07 bcd arithmetic instructions. (UNSPEC_BCDSUB): Likewise. (UNSPEC_BCD_OVERFLOW): Likewise. (UNSPEC_BCD_ADD_SUB): Likewise. (bcd_add_sub): Likewise. (BCD_TEST): Likewise. (bcd<bcd_add_sub>): Likewise. (bcd<bcd_add_sub>_test): Likewise. (bcd<bcd_add_sub>_test2): Likewise. (bcd<bcd_add_sub>_<code>): Likewise. (peephole2 for combined bcd ops): Likewise. * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new decimal floating point builtin functions. (UNSPEC_DENBCD): Likewise. (UNSPEC_DXEX): Likewise. (UNSPEC_DIEX): Likewise. (UNSPEC_DSCLI): Likewise. (UNSPEC_DSCRI): Likewise. (D64_D128): Likewise. (dfp_suffix): Likewise. (dfp_ddedpd_<mode>): Likewise. (dfp_denbcd_<mode>): Likewise. (dfp_dxex_<mode>): Likewise. (dfp_diex_<mode>): Likewise. (dfp_dscli_<mode>): Likewise. (dfp_dscri_<mode>): Likewise. * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD builtin functions. (UNSPEC_CDTBCD): Likewise. (UNSPEC_CBCDTD): Likewise. (UNSPEC_DIVE): Add support for new extended divide builtin functions. (UNSPEC_DIVEO): Likewise. (UNSPEC_DIVEU): Likewise. (UNSPEC_DIVEUO): Likewise. (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to pack/unpack 128-bit types. (UNSPEC_PACK_128BIT): Likewise. (idiv_ldiv): New mode attribute to set the 32/64-bit divide type. (udiv<mode>3): Use idiv_ldiv mode attribute. (div<mode>3): Likewise. (addg6s): Add new BCD builtin functions. (cdtbcd): Likewise. (cbcdtd): Likewise. (UNSPEC_DIV_EXTEND): Add support for new extended divide instructions. (div_extend): Likewise. (div<div_extend>_<mode>"): Likewise. (FP128_64): Add support for new builtin functions to pack/unpack 128-bit types. (unpack<mode>): Likewise. (unpacktf_0): Likewise. (unpacktf_1): Likewise. (unpack<mode>_dm): Likewise. (unpack<mode>_nodm): Likewise. (pack<mode>): Likewise. (unpackv1ti): Likewise. (packv1ti): Likewise. [gcc/testsuite] 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/pack01.c: New test to test the new pack and unpack builtin functionss for 128-bit types. * gcc.target/powerpc/pack02.c: Likewise. * gcc.target/powerpc/pack03.c: Likewise. * gcc.target/powerpc/extend-divide-1.c: New test to test extended divide builtin functionss. * gcc.target/powerpc/extend-divide-2.c: Likewise. * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin functions. * gcc.target/powerpc/bcd-2.c: Likewise. * gcc.target/powerpc/bcd-3.c: Likewise. * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP builtin functionss. * gcc.target/powerpc/dfp-builtin-2.c: Likewise. From-SVN: r209768
2014-04-24avr.c: Add comment on why -fdelete-null-pointer-checks is disabled.Vishnu K S1-0/+6
2014-04-24 Vishnu K S <Vishnu.k_s@atmel.com> * gcc/config/avr/avr.c: Add comment on why -fdelete-null-pointer-checks is disabled. 2014-04-24 Vishnu K S <Vishnu.k_s@atmel.com> * gcc/testsuite/gcc.dg/tree-ssa/isolate-1.c: Skip test if keeps_null_pointer_checks. * gcc/testsuite/gcc.dg/tree-ssa/isolate-2.c: Ditto * gcc/testsuite/gcc.dg/tree-ssa/isolate-3.c: Ditto * gcc/testsuite/gcc.dg/tree-ssa/isolate-4.c: Ditto * gcc/testsuite/gcc.dg/tree-ssa/isolate-5.c: Ditto From-SVN: r209767
2014-04-24[multiple changes]Jeff Law1-1/+3
2014-04-24 Segher Boessenkool <segher@kernel.crashing.org> PR target/60822 * config/m68k/m68k.md (extendplussidi): Don't allow memory for operand 1. 2014-04-24 Jeff Law <law@redhat.com> PR target/60822 * gcc.c-torture/pr60822.c: New test. * gcc.c-torture/pr60822.x: New test. From-SVN: r209759
2014-04-24fixup sh bustage after r209483Trevor Saunders1-3/+3
When making pass::execute functions take a function * argument I missed the sh_treg_combine pass, so fix that here. gcc/ * config/sh/sh_treg_combine.c (sh_treg_combine::execute): Take function * argument. From-SVN: r209751
2014-04-24[AArch64] Enable TBL for big-endian.Alan Lawrence1-5/+0
gcc/ChangeLog: 2014-04-11 Alan Lawrence <alan.lawrence@arm.com> * config/aarch64/aarch64.c (aarch64_evpc_tbl): Enable for bigendian. gcc/testsuite/ChangeLog: 2014-04-11 Alan Lawrence <alan.lawrence@arm.com> * lib/target-supports.exp (check_effective_target_vect_perm): Return true for aarch64_be. From-SVN: r209749
2014-04-24[AArch64] Reverse TBL indices for big-endian.Tejas Belagod1-1/+9
2014-04-24 Tejas Belagod <tejas.belagod@arm.com> * config/aarch64/aarch64.c (aarch64_evpc_tbl): Reverse order of elements for big-endian. From-SVN: r209742
2014-04-24Only redefine ASM_PREFERRED_EH_DATA_FORMAT if necessary on Solaris/x86Rainer Orth1-1/+3
* config/i386/sol2.h (ASM_PREFERRED_EH_DATA_FORMAT): Only redefine if not HAVE_AS_IX86_DIFF_SECT_DELTA. From-SVN: r209740
2014-04-24[AArch64] Wire up TARGET_SIMD and TARGET_FLOAT properlyKyrylo Tkachov1-6/+6
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Check TARGET_SIMD rather than TARGET_GENERAL_REGS_ONLY. (TARGET_SIMD): Take AARCH64_ISA_SIMD into account. (TARGET_FLOAT): Take AARCH64_ISA_FP into account. (TARGET_CRYPTO): Take TARGET_SIMD into account. From-SVN: r209737
2014-04-24[AArch64] Vectorise bswap[16,32,64]Kyrylo Tkachov4-1/+39
* config/aarch64/aarch64-builtins.c (aarch64_builtin_vectorized_function): Handle BUILT_IN_BSWAP16, BUILT_IN_BSWAP32, BUILT_IN_BSWAP64. * config/aarch64/aarch64-simd.md (bswap<mode>): New pattern. * config/aarch64/aarch64-simd-builtins.def: Define vector bswap builtins. * config/aarch64/iterator.md (VDQHSD): New mode iterator. (Vrevsuff): New mode attribute. * lib/target-supports.exp (check_effective_target_vect_bswap): New. * gcc.dg/vect/vect-bswap16: New test. * gcc.dg/vect/vect-bswap32: Likewise. * gcc.dg/vect/vect-bswap64: Likewise. From-SVN: r209736
2014-04-24arm.h (machine_function): Define variable after_arm_reorg here.Terry Guo2-9/+4
2014-04-24 Terry Guo <terry.guo@arm.com> * config/arm/arm.h (machine_function): Define variable after_arm_reorg here. * config/arm/arm.c (after_arm_reorg): Remove the definition. (arm_split_constant): Update the way to access variable after_arm_reorg. (arm_reorg): Ditto. (arm_output_function_epilogue): Remove the reset of after_arm_reorg. From-SVN: r209735
2014-04-23[AARCH64] Use standard patterns for stack protection.Venkataramanan Kumar1-0/+63
From-SVN: r209712
2014-04-23[AArch64] Fully support rotate on logical operations.Richard Earnshaw2-2/+29
From-SVN: r209711
2014-04-23[ARM] Initialize new tune_params valuesJames Greenhalgh1-2/+4
gcc/ * config/arm/arm.c (arm_cortex_a57_tune): Initialize all fields. (arm_cortex_a12_tune): Likewise. From-SVN: r209710
generated by cgit v1.1 at 2025-02-25 17:58:03 +0000