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2013-04-25[AArch64] Change iterator for neg<mode>2 from VDQM to VDQ.James Greenhalgh1-2/+2
2013-04-25[AArch64] Make vabs<q>_f<32, 64> a tree/gimple intrinsic.James Greenhalgh5-33/+45
2013-04-25[AArch64] Implement TARGET_GIMPLE_FOLD_BUILTIN for aarch64 backend.James Greenhalgh6-5/+92
2013-04-25gcc/Naveen H.S1-0/+12
2013-04-25aarch64.md (*ngc<mode>): New pattern.Naveen H.S1-0/+21
2013-04-25arm.c (neon_builtin_type_mode): Add T_V4HF.Kyrylo Tkachov8-31/+153
2013-04-25[AArch64] Fix printf format warning in aarch64_print_operandJames Greenhalgh1-1/+1
2013-04-25re PR target/57052 (missed optimization with rotate and mask)Alan Modra1-58/+626
2013-04-25config.host: Match little-endian powerpc-linux.Alan Modra8-83/+101
2013-04-25rs6000.c (rs6000_secondary_reload_inner): Use replace_equiv_address_nv.Alan Modra1-1/+1
2013-04-25rs6000.c (rs6000_emit_set_long_const): Tidy.Alan Modra1-24/+9
2013-04-24Handle -mx32 in x86-64 ASM_SPECH.J. Lu1-1/+1
2013-04-24[AArch64] Fix vld1<q>_* asm constraints in arm_neon.hJames Greenhalgh1-240/+240
2013-04-24micromips.md (jraddiusp): New pattern.Catherine Moore2-1/+26
2013-04-24fix comment pastoAlan Modra1-1/+1
2013-04-23mips.md (*movhi_internal, [...]): New operands.Catherine Moore1-6/+8
2013-04-23aarch64.md (*mov<mode>_aarch64): Add simd attribute.Sofiane Naci1-0/+1
2013-04-22re PR rtl-optimization/57032 (internal compiler error: Max. number of generat...Uros Bizjak1-3/+0
2013-04-22[AArch64] Map standard pattern names to NEON intrinsics directly.James Greenhalgh4-450/+411
2013-04-22[AArch64] Support vrecp<esx> neon intrinsics in RTL.James Greenhalgh6-141/+153
2013-04-22re PR target/56995 (sh4 -mfmovd: ICE in find_costs_and_classes)Christian Bruel2-9/+3
2013-04-19arm.c (load_multiple_sequence, [...]): Fix spelling in two comments.Greta Yorsh1-2/+2
2013-04-19re PR target/56797 (internal compiler error: in extract_insn, at recog.c:2150)Greta Yorsh1-0/+7
2013-04-19cortex-m4-fpu.md (cortex_m4_v): Delete cpu unit.Terry Guo1-6/+12
2013-04-18* config/i386/predicates.md (call_rex64_ms_sysv_operation): Fix comment.Uros Bizjak1-1/+1
2013-04-18i386.c (x86_64_ms_sysv_extra_clobbered_registers): New array.Uros Bizjak4-51/+67
2013-04-172013-04-17 Greta Yorsh <Greta.Yorsh at arm.com>Greta Yorsh1-28/+151
2013-04-172013-04-17 Greta Yorsh <Greta.Yorsh at arm.com>Greta Yorsh1-0/+4
2013-04-17* config/arm/cortex-m4.md: Add a new bypass.Terry Guo1-0/+4
2013-04-17aarch64.md (*adds_<optab><mode>_multp2): New pattern.Naveen H.S1-0/+72
2013-04-17aarch64.md (*adds_mul_imm_<mode>): New pattern.Naveen H.S1-0/+34
2013-04-16re PR target/56948 (PPC V2DI ICE when loading zero into GPRs)David Edelsohn1-11/+13
2013-04-16Prologue/epilogue using STRD/LDRD in ARM modeGreta Yorsh1-2/+288
2013-04-15arm.c (const_ok_for_dimode_op): Handle AND case.Kyrylo Tkachov5-42/+79
2013-04-15Use -z ignore instead of --as-needed on SolarisRainer Orth1-0/+5
2013-04-15i386.opt: New option mstack-protector-guard=.Andrew Hsieh5-4/+30
2013-04-15re PR target/56890 (invalid fdtox instruction in 64-bit mode with -O2)Eric Botcazou1-12/+15
2013-04-15* config/arm/arm.c (thumb_far_jump_used_p): Fix typo in comments.Joey Ye1-2/+2
2013-04-15arm.c (thumb1_final_prescan_insn): Assert lr save for real far jump.Joey Ye1-0/+27
2013-04-12i386.c (ix86_hard_regno_mode_ok): Use ANY_QI_REGNO_P in QImode checks.Uros Bizjak1-3/+3
2013-04-12re PR rtl-optimization/56903 (gcc is 4.8.0 fails to compile netdev.c from the...Vladimir Makarov1-0/+5
2013-04-12arm.md (mov_scc,mov_negscc,mov_notscc): Convert define_insn into define_insn_...Greta Yorsh1-9/+29
2013-04-12arm.c (gen_operands_ldrd_strd): Initialize "base".Greta Yorsh1-1/+1
2013-04-12tree-pass.h (TODO_do_not_ggc_collect): New.Richard Biener1-1/+1
2013-04-12aarch64.c (aarch64_select_cc_mode): Allow NEG code in CC_NZ mode.Naveen H.S2-1/+17
2013-04-11[AArch64] Define REVERSIBLE_CC_MODE.Naveen H.S1-0/+2
2013-04-11[PATCH, AARCH64] Fix unrecognizable insn issue with vcond against 0.0fJames Greenhalgh1-5/+29
2013-04-10sparc.c: Include tree-pass.h.Steven Bosscher2-106/+139
2013-04-10Fix sparc assembler specs for supersparc and hypersparc.David S. Miller1-0/+2
2013-04-10Improve cstore code generation on 64-bit sparc.David S. Miller3-96/+69
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