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2019-11-16[AArch64] Add autovec support for partial SVE vectorsRichard Sandiford5-167/+381
2019-11-16[AArch64] Replace SVE_PARTIAL with SVE_PARTIAL_IRichard Sandiford2-12/+12
2019-11-16[AArch64] Add "FULL" to SVE mode iterator namesRichard Sandiford3-1195/+1243
2019-11-16[AArch64] Enable VECT_COMPARE_COSTS by default for SVERichard Sandiford2-1/+13
2019-11-16Optionally pick the cheapest loop_vec_infoRichard Sandiford5-6/+13
2019-11-15m68k: add musl supportSzabolcs Nagy1-0/+3
2019-11-15microblaze: fix PR65649Nick Clifton1-2/+2
2019-11-15[amdgcn] Unfix registers for frame pointerKwok Cheung Yeung1-2/+2
2019-11-15[amdgcn] Update lower bounds for the number of registers in non-leaf kernelsKwok Cheung Yeung1-6/+14
2019-11-15[amdgcn] Restrict registers available to non-kernel functionsKwok Cheung Yeung2-30/+39
2019-11-15[amdgcn] Reinitialize registers for every functionKwok Cheung Yeung1-0/+2
2019-11-15[amdgcn] Use first lane of v1 for zero offsetKwok Cheung Yeung1-14/+3
2019-11-15[rs6000] Use VIEW_CONVERT_EXPR to reinterpret vectors (PR 92515)Richard Sandiford1-3/+6
2019-11-15[amdgcn] Fix handling of VCC_CONDITIONAL_REGKwok Cheung Yeung1-1/+5
2019-11-14Update the arm-*-vxworks* supportJerome Lambourg2-19/+14
2019-11-14Housekeeping on TARGET_OS_CPP_BUILTINS for arm-vxworksJerome Lambourg1-35/+37
2019-11-14Base support for vxworks 7 on aarch64Doug Rupp2-0/+93
2019-11-14Introduce vxworks specific crtstuff supportJerome Lambourg2-10/+29
2019-11-14Common ground work for vxworks7 ports updatesPat Bernardi2-6/+28
2019-11-14Vectorise conversions between differently-sized integer vectorsRichard Sandiford2-0/+20
2019-11-14[AArch64] Support vectorising with multiple vector sizesRichard Sandiford1-0/+45
2019-11-14Replace autovectorize_vector_sizes with autovectorize_vector_modesRichard Sandiford5-42/+42
2019-11-14Pass the data vector mode to get_mask_modeRichard Sandiford3-15/+10
2019-11-14Remove build_{same_sized_,}truth_vector_typeRichard Sandiford2-2/+2
2019-11-14Add build_truth_vector_type_for_modeRichard Sandiford1-2/+2
2019-11-14Replace mode_for_int_vector with related_int_vector_modeRichard Sandiford2-5/+5
2019-11-14arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__Richard Henderson6-0/+151
2019-11-14arm: Rename CC_NOOVmode to CC_NZmodeRichard Henderson6-123/+123
2019-11-14arm: Fix the "c" constraintRichard Henderson1-2/+3
2019-11-14aarch64: Add "c" constraintRichard Henderson1-0/+4
2019-11-14Enable VPOPCNTDQ for icelake-{client,server} and tigerlake.Martin Liska1-1/+1
2019-11-14i386-options.c (ix86_omp_device_kind_arch_isa): Don't change sse4.2 to sse4_2...Jakub Jelinek2-9/+3
2019-11-13Sanitize the constant argument for rotr<mode>3Dragan Mladjenovic1-2/+2
2019-11-13Use a single worker for OpenACC on AMD GCNAndrew Stubbs2-3/+3
2019-11-13GCN mkoffloadAndrew Stubbs2-0/+729
2019-11-13Move gcn-run heap into GPU memory.Andrew Stubbs1-16/+48
2019-11-13[AArch64] Use aarch64_sve_int_mode in SVE ACLE codeRichard Sandiford1-1/+1
2019-11-13re PR target/92055 ([avr] Support 64-bit double)Georg-Johann Lay1-2/+1
2019-11-12rs6000: Use ULL on big hexadecimal literalSegher Boessenkool1-1/+1
2019-11-12rs6000: Handle unordered for xscmpexp[dq]p without NaNs (PR92449)Segher Boessenkool1-0/+12
2019-11-12Use more SET_OPTION_IF_UNSET.Martin Liska1-18/+16
2019-11-12Remove option_default_params and option_validate_param hooks.Martin Liska1-7/+5
2019-11-12Remove last leftover usage of params* files.Martin Liska1-2/+0
2019-11-12Remove gcc/params.* files.Martin Liska16-16/+0
2019-11-12Apply mechanical replacement (generated patch).Martin Liska11-241/+173
2019-11-12[RS6000] PC-relative TLS supportAlan Modra3-8/+61
2019-11-12[RS6000] Remove TARGET_TLS_MARKERS and require binutils 2.20Alan Modra5-164/+37
2019-11-11Add prefixed insn support for stack_protect_setdi & stack_protect_testdiMichael Meissner2-6/+81
2019-11-11re PR bootstrap/92433 (r276645 breaks bootstrap on powerpc)Jakub Jelinek1-5/+5
2019-11-11[ARC] Fix movsi_ne pattern.Claudiu Zissulescu1-11/+11