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AgeCommit message (Expand)AuthorFilesLines
2019-11-30cgraph.h (symtab_node): Add symver flag.Jan Hubicka1-0/+11
2019-11-30[C] Add a target hook that allows targets to verify type usageRichard Sandiford3-0/+64
2019-11-29rs6000: Fix formatting of *mov{si,di}_internal.*Segher Boessenkool1-96/+96
2019-11-28rs6000: Use memory_operand for all simple {l,st}*brx instructionsSegher Boessenkool1-4/+4
2019-11-28Must use push insn to pass varargs arguments of DFmode because otherwise the ...Georg-Johann Lay1-1/+1
2019-11-28[rs6000] Fix PR92566 by checking VECTOR_UNIT_NONE_PKewen Lin1-24/+5
2019-11-28sse.md (avx512f_maskcmp<mode>3): Refine VF to VF_AVX512VL.Hongtao Liu1-2/+2
2019-11-28Reformat movdi_internal64.Michael Meissner1-30/+48
2019-11-27Reformat movsi_internal.Michael Meissner1-30/+49
2019-11-27Do not define DFP builtin functions, if DFP has been disabled.Peter Bergner1-0/+14
2019-11-27m68k.c (m68k_output_compare_fp): Restore differences between Coldfire and reg...Bernd Schmidt2-3/+11
2019-11-26S/390: Add undef for MUSL_DYNAMIC_LINKERxxRobin Dapp1-0/+2
2019-11-25config/gcn/mkoffload.c – remove unused static varsTobias Burnus1-11/+0
2019-11-25Convert m68k to not use cc0Bernd Schmidt5-1993/+1494
2019-11-25[amdgcn] Silence warnings + add gcc_unreachable()Tobias Burnus1-3/+3
2019-11-25Build double32 / long-double32 multilibs if needed.Georg-Johann Lay3-40/+107
2019-11-25[rs6000] Refactor FP vector comparison operatorsKewen Lin1-160/+105
2019-11-24Fix ix86 rtx costs for the pr30315 testcase (PR target/30315)Bernd Schmidt1-0/+9
2019-11-23re PR inline-asm/92615 (ICE in extract_insn)Jakub Jelinek1-3/+7
2019-11-22Limit LDS usage.Andrew Stubbs1-4/+12
2019-11-22Use GFX9 granulated sgprs count correctly.Andrew Stubbs1-1/+9
2019-11-22[ARC] Fix failing pr77309 for ARC700Claudiu Zissulescu1-23/+29
2019-11-21rs6000: Don't split FP comparisons at expand timeSegher Boessenkool4-57/+130
2019-11-20AMD GCN symbol output with null cfunJulian Brown1-2/+4
2019-11-20rs6000: Fix UNORDERED without NaNs, for DFP (PR92573)Segher Boessenkool1-0/+6
2019-11-20[ARC] Register ARC specific passes with a .def file.Claudiu Zissulescu4-37/+61
2019-11-20re PR target/90867 (Multiplication or typecast of integer and double always z...Jakub Jelinek1-13/+21
2019-11-20Make 0-series device specs work with older versions of avr-gcc.Georg-Johann Lay2-10/+5
2019-11-19rs6000.c (move_to_end_of_ready): New, factored out from common code.Pat Haugen1-213/+211
2019-11-19[MIPS] Prevent MSA branches from being put into delay slotsDragan Mladjenovic2-4/+12
2019-11-19[AArch64] PR79262: Adjust vector costWilco Dijkstra1-1/+1
2019-11-19[Arm] Set Armv7-A tune to Cortex-A53Wilco Dijkstra1-3/+3
2019-11-19[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsicsDennis Zhang8-3/+372
2019-11-19arm: Fixes for asm-flags vs thumb1 and ilp32Richard Henderson2-1/+27
2019-11-19re PR target/92549 (Use x86 xchg instruction more)Jakub Jelinek1-0/+11
2019-11-19Initialize a variable due to -Wmaybe-uninitialized.Martin Liska1-1/+1
2019-11-18Add optabs for accelerating RAW and WAR alias checksRichard Sandiford4-1/+78
2019-11-18Remove vestiges of MODIFY_JNI_METHOD_CALLTom Tromey1-8/+0
2019-11-18s390: add musl supportSzabolcs Nagy1-0/+3
2019-11-18re PR target/92545 (avr: support ATmega devices from the 0-series)Georg-Johann Lay1-1/+1
2019-11-18Add support for AVR devices from the 0-series.Georg-Johann Lay6-333/+441
2019-11-18Split X86_TUNE_AVX128_OPTIMAL into X86_TUNE_AVX256_SPLIT_REGSHongtao Liu5-6/+10
2019-11-17rs6000: Allow mode GPR in cceq_{ior,rev}_compareSegher Boessenkool1-7/+7
2019-11-16[AArch64] Robustify aarch64_wrffrRichard Sandiford1-1/+1
2019-11-16[AArch64] Add scatter stores for partial SVE modesRichard Sandiford1-35/+62
2019-11-16[AArch64] Pattern-match SVE extending gather loadsRichard Sandiford3-128/+227
2019-11-16[AArch64] Add gather loads for partial SVE modesRichard Sandiford2-39/+105
2019-11-16[AArch64] Add truncation for partial SVE modesRichard Sandiford2-0/+44
2019-11-16[AArch64] Pattern-match SVE extending loadsRichard Sandiford3-74/+85
2019-11-16[AArch64] Add sign and zero extension for partial SVE modesRichard Sandiford2-21/+51
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