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AgeCommit message (Expand)AuthorFilesLines
2015-11-03remove unused config/arm/coff.hTrevor Saunders1-82/+0
2015-11-03[AARCH64][PATCH 1/3] Implementing the variants of the vmulx_ NEON intrinsicBilyan Borisov4-68/+51
2015-11-03[AArch64] Fix ICE on (const_double:HF 0.0)Alan Lawrence1-1/+1
2015-11-02freebsd64.h (ASM_SPEC32): Adust spec to handle PIE executables.Andreas Tobler1-1/+1
2015-11-02[ARM] neon-testgen.ml typoJulian Brown1-7/+7
2015-11-01* config/mcore/mcore.c: Include regs.h.Jeff Law1-0/+1
2015-10-31rs6000: Rewrite rs6000_reg_live_or_pic_offset_pSegher Boessenkool1-15/+20
2015-10-31rs6000: Another PIC LRA fixSegher Boessenkool1-1/+3
2015-10-30nvptx.h (HARD_REGNO_NREGS): Avoid warning on unused args.Jeff Law1-2/+2
2015-10-30Makefile.in (OBJS): Add multiple_target.o.Evgeny Stupachenko1-18/+0
2015-10-30Fix comment typo.Jim Wilson1-1/+1
2015-10-30[ARM] Fix checking RTL error in cortex_a9_sched_adjust_costKyrylo Tkachov1-3/+1
2015-10-30libgcc changes for AMD znver1.Venkataramanan Kumar1-0/+6
2015-10-30[AArch64] Fix insn types.Evandro Menezes1-4/+4
2015-10-29[PATCH 8/9] ENABLE_CHECKING refactoring: target-specific partsMikhail Maltsev9-139/+126
2015-10-30sh.opt: Fix format of the help text for -mfdpicKaz Kojima1-1/+1
2015-10-30[MCORE] Hookize GO_IF_LEGITIMATE_ADDRESSAnatoly Sokolov2-85/+75
2015-10-29rs6000: Save the PIC reg when neededSegher Boessenkool1-22/+22
2015-10-29Fix target/68124Richard Henderson1-15/+21
2015-10-29rs6000.c (rs6000_init_libfuncs): Split libfunc setup into 3 functions...Michael Meissner2-277/+591
2015-10-29rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit floating point modes that ca...Michael Meissner7-93/+108
2015-10-28nvptx.c (nvptx_print_operand): Remove 'd' case.Nathan Sidwell1-19/+4
2015-10-28re PR target/67839 (Bit addressable instructions generated for invalid memory...Senthil Kumar Selvaraj1-2/+2
2015-10-28Handle noplt in call expanders for AArch64.Ramana Radhakrishnan1-10/+14
2015-10-28nvptx.h (struct machine_function): Add axis_predicate.Nathan Sidwell4-23/+1320
2015-10-27re PR rtl-optimization/67609 (Generates wrong code for SSE2 _mm_load_pd)Richard Henderson1-8/+15
2015-10-27[AArch64] PR 68102: Check that operand is REG before checking the REGNO in mo...Kyrylo Tkachov1-2/+2
2015-10-27[AArch64] Handle vector float modes properly in aarch64_output_simd_mov_immed...Kyrylo Tkachov1-1/+4
2015-10-27Properly handle -fno-plt in ix86_expand_callH.J. Lu2-17/+61
2015-10-27config.gcc: Handle --enable-fdpic.Daniel Jacobowitz9-147/+752
2015-10-27[ARM] PR target/67929 Tighten vfp3_const_double_for_bits checksKyrylo Tkachov3-15/+28
2015-10-27[PATCH] [AArch64] Distinct costs for sign and zero extensionEvandro Menezes2-6/+13
2015-10-27[AArch64] Enable autoprefetcher modelling in the schedulerKyrylo Tkachov2-0/+64
2015-10-26* config/linux.h (INCLUDE_DEFAULTS): Add INCLUDE_DEFAULTS_MUSL_LOCAL.Doug Evans1-0/+1
2015-10-26target.def (TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P): New hook.Simon Dardis1-0/+11
2015-10-26[config/sh/sh.c] Fix PR68091: Return false for non shmedia targets in sh_vect...Kaz Kojima1-1/+1
2015-10-25som.h (EH_FRAME_THROUGH_COLLECT2): Define.John David Anglin1-0/+5
2015-10-25re PR target/68084 (Inverted conditions generated for x86 inline assembly "fl...Uros Bizjak1-1/+1
2015-10-23powerpc musl libc supportGregor Richards3-7/+101
2015-10-22re PR driver/68043 (many undocumented options, missing punctuation)Martin Sebor2-8/+8
2015-10-22msp430.opt: Add -msilicon-errata and -msilicon-errata-warn.Nick Clifton2-0/+10
2015-10-22oops- omitted by accident from the previous delta.Nick Clifton1-281/+433
2015-10-22S/390: PR68015 Fix ICE in s390_emit_compareAndreas Krebbel1-2/+7
2015-10-22[Patch AArch64 63304] Fix issue with global state.Ramana Radhakrishnan3-12/+16
2015-10-21Improve --help output to generate references to option aliases.Martin Sebor74-1197/+1197
2015-10-21re PR target/68018 (ICE: in ix86_compute_frame_layout, at config/i386/i386.c:...Uros Bizjak1-3/+6
2015-10-21Pass --secure-plt to the linkerGregor Richards3-0/+11
2015-10-20musl support for shGregor Richards1-0/+21
2015-10-20[AArch64] Add support for 64-bit vector-mode ldp/stpKyrylo Tkachov3-2/+84
2015-10-20[AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisationKyrylo Tkachov5-0/+107
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