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AgeCommit message (Expand)AuthorFilesLines
2019-11-19[MIPS] Prevent MSA branches from being put into delay slotsDragan Mladjenovic2-4/+12
2019-11-19[AArch64] PR79262: Adjust vector costWilco Dijkstra1-1/+1
2019-11-19[Arm] Set Armv7-A tune to Cortex-A53Wilco Dijkstra1-3/+3
2019-11-19[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsicsDennis Zhang8-3/+372
2019-11-19arm: Fixes for asm-flags vs thumb1 and ilp32Richard Henderson2-1/+27
2019-11-19re PR target/92549 (Use x86 xchg instruction more)Jakub Jelinek1-0/+11
2019-11-19Initialize a variable due to -Wmaybe-uninitialized.Martin Liska1-1/+1
2019-11-18Add optabs for accelerating RAW and WAR alias checksRichard Sandiford4-1/+78
2019-11-18Remove vestiges of MODIFY_JNI_METHOD_CALLTom Tromey1-8/+0
2019-11-18s390: add musl supportSzabolcs Nagy1-0/+3
2019-11-18re PR target/92545 (avr: support ATmega devices from the 0-series)Georg-Johann Lay1-1/+1
2019-11-18Add support for AVR devices from the 0-series.Georg-Johann Lay6-333/+441
2019-11-18Split X86_TUNE_AVX128_OPTIMAL into X86_TUNE_AVX256_SPLIT_REGSHongtao Liu5-6/+10
2019-11-17rs6000: Allow mode GPR in cceq_{ior,rev}_compareSegher Boessenkool1-7/+7
2019-11-16[AArch64] Robustify aarch64_wrffrRichard Sandiford1-1/+1
2019-11-16[AArch64] Add scatter stores for partial SVE modesRichard Sandiford1-35/+62
2019-11-16[AArch64] Pattern-match SVE extending gather loadsRichard Sandiford3-128/+227
2019-11-16[AArch64] Add gather loads for partial SVE modesRichard Sandiford2-39/+105
2019-11-16[AArch64] Add truncation for partial SVE modesRichard Sandiford2-0/+44
2019-11-16[AArch64] Pattern-match SVE extending loadsRichard Sandiford3-74/+85
2019-11-16[AArch64] Add sign and zero extension for partial SVE modesRichard Sandiford2-21/+51
2019-11-16[AArch64] Add autovec support for partial SVE vectorsRichard Sandiford5-167/+381
2019-11-16[AArch64] Replace SVE_PARTIAL with SVE_PARTIAL_IRichard Sandiford2-12/+12
2019-11-16[AArch64] Add "FULL" to SVE mode iterator namesRichard Sandiford3-1195/+1243
2019-11-16[AArch64] Enable VECT_COMPARE_COSTS by default for SVERichard Sandiford2-1/+13
2019-11-16Optionally pick the cheapest loop_vec_infoRichard Sandiford5-6/+13
2019-11-15m68k: add musl supportSzabolcs Nagy1-0/+3
2019-11-15microblaze: fix PR65649Nick Clifton1-2/+2
2019-11-15[amdgcn] Unfix registers for frame pointerKwok Cheung Yeung1-2/+2
2019-11-15[amdgcn] Update lower bounds for the number of registers in non-leaf kernelsKwok Cheung Yeung1-6/+14
2019-11-15[amdgcn] Restrict registers available to non-kernel functionsKwok Cheung Yeung2-30/+39
2019-11-15[amdgcn] Reinitialize registers for every functionKwok Cheung Yeung1-0/+2
2019-11-15[amdgcn] Use first lane of v1 for zero offsetKwok Cheung Yeung1-14/+3
2019-11-15[rs6000] Use VIEW_CONVERT_EXPR to reinterpret vectors (PR 92515)Richard Sandiford1-3/+6
2019-11-15[amdgcn] Fix handling of VCC_CONDITIONAL_REGKwok Cheung Yeung1-1/+5
2019-11-14Update the arm-*-vxworks* supportJerome Lambourg2-19/+14
2019-11-14Housekeeping on TARGET_OS_CPP_BUILTINS for arm-vxworksJerome Lambourg1-35/+37
2019-11-14Base support for vxworks 7 on aarch64Doug Rupp2-0/+93
2019-11-14Introduce vxworks specific crtstuff supportJerome Lambourg2-10/+29
2019-11-14Common ground work for vxworks7 ports updatesPat Bernardi2-6/+28
2019-11-14Vectorise conversions between differently-sized integer vectorsRichard Sandiford2-0/+20
2019-11-14[AArch64] Support vectorising with multiple vector sizesRichard Sandiford1-0/+45
2019-11-14Replace autovectorize_vector_sizes with autovectorize_vector_modesRichard Sandiford5-42/+42
2019-11-14Pass the data vector mode to get_mask_modeRichard Sandiford3-15/+10
2019-11-14Remove build_{same_sized_,}truth_vector_typeRichard Sandiford2-2/+2
2019-11-14Add build_truth_vector_type_for_modeRichard Sandiford1-2/+2
2019-11-14Replace mode_for_int_vector with related_int_vector_modeRichard Sandiford2-5/+5
2019-11-14arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__Richard Henderson6-0/+151
2019-11-14arm: Rename CC_NOOVmode to CC_NZmodeRichard Henderson6-123/+123
2019-11-14arm: Fix the "c" constraintRichard Henderson1-2/+3
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